xref: /titanic_41/usr/src/uts/sun/sys/scsi/adapters/fasreg.h (revision 7c478bd95313f5f23a4c958a745db2134aa03244)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1996-1998 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef	_SYS_SCSI_ADAPTERS_FASREG_H
28 #define	_SYS_SCSI_ADAPTERS_FASREG_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #include <sys/note.h>
33 
34 #ifdef	__cplusplus
35 extern "C" {
36 #endif
37 
38 /*
39  * FAS register	definitions.
40  */
41 
42 /*
43  * All current Sun implementations use the following layout.
44  * That	is, the	FAS registers are always byte-wide, but	are
45  * accessed longwords apart. Notice also that the byte-ordering
46  * is big-endian.
47  */
48 
49 struct fasreg {
50 	uint8_t	fas_xcnt_lo;		/* RW: transfer	counter	(low byte) */
51 					uint8_t _pad1, _pad2, _pad3;
52 
53 	uint8_t	fas_xcnt_mid;		/* RW: transfer	counter	(mid byte) */
54 					uint8_t _pad5, _pad6, _pad7;
55 
56 	uint8_t	fas_fifo_data;		/* RW: fifo data buffer	*/
57 					uint8_t _pad9, _pad10, _pad11;
58 
59 	uint8_t	fas_cmd;		/* RW: command register	*/
60 					uint8_t _pad13, _pad14, _pad15;
61 
62 	uint8_t	fas_stat;		/* R: status register */
63 #define	fas_busid	fas_stat	/* W: bus id for sel/resel */
64 					uint8_t _pad17, _pad18, _pad19;
65 
66 
67 	uint8_t	fas_intr;		/* R: interrupt	status register	*/
68 #define	fas_timeout	fas_intr	/* W: sel/resel	timeout	*/
69 					uint8_t _pad21, _pad22, _pad23;
70 
71 
72 	uint8_t	fas_step;		/* R: sequence step register */
73 #define	fas_sync_period	fas_step	/* W: synchronous period */
74 					uint8_t _pad25, _pad26, _pad27;
75 
76 
77 	uint8_t	fas_fifo_flag;		/* R: fifo flag	register */
78 #define	fas_sync_offset	fas_fifo_flag	/* W: synchronous offset */
79 					uint8_t _pad29, _pad30, _pad31;
80 
81 
82 	uint8_t	fas_conf;		/* RW: configuration register */
83 					uint8_t _pad33, _pad34, _pad35;
84 
85 
86 	uint8_t	fas_clock_conv;		/* W: clock conversion register	*/
87 					uint8_t _pad37, _pad38, _pad39;
88 #define	fas_stat2	fas_clock_conv
89 
90 
91 	uint8_t	fas_test;		/* RW: test register */
92 					uint8_t _pad41, _pad42, _pad43;
93 #define	fas_conf4	fas_test
94 
95 
96 	uint8_t	fas_conf2;		/* FAS-II configuration	register */
97 					uint8_t _pad45, _pad46, _pad47;
98 
99 
100 	uint8_t	fas_conf3;		/* FAS-III configuration register */
101 					uint8_t _pad49, _pad50, _pad51;
102 					uint8_t _pad_reserved[4];
103 
104 	uint8_t	fas_recmd_lo;		/* RW: fifo recmd counter lo */
105 #define	fas_id_code fas_recmd_lo	/* R: part-unique id code */
106 					uint8_t _pad52, _pad53, _pad54;
107 
108 	uint8_t	fas_recmd_hi;		/* RW: fifo recmd counter lo */
109 					uint8_t _pad55, _pad56, _pad57;
110 };
111 
112 
113 /*
114  * FAS command register	definitions
115  */
116 
117 /*
118  * These commands may be used at any time with the FAS chip.
119  * None	generate an interrupt, per se, although	if you have
120  * enabled detection of	SCSI reset in setting the configuration
121  * register, a CMD_RESET_SCSI will generate an interrupt.
122  * Therefore, it is recommended	that if	you use	the CMD_RESET_SCSI
123  * command, you	at least temporarily disable recognition of
124  * SCSI	reset in the configuration register.
125  */
126 #define	CMD_NOP		0x0
127 #define	CMD_FLUSH	0x1
128 #define	CMD_RESET_FAS	0x2
129 #define	CMD_RESET_SCSI	0x3
130 
131 /*
132  * These commands will only work if the	FAS is in the
133  * 'disconnected' state:
134  */
135 #define	CMD_RESEL_SEQ	0x40
136 #define	CMD_SEL_NOATN	0x41
137 #define	CMD_SEL_ATN	0x42
138 #define	CMD_SEL_STOP	0x43
139 #define	CMD_EN_RESEL	0x44	/* (no interrupt generated) */
140 #define	CMD_DIS_RESEL	0x45
141 #define	CMD_SEL_ATN3	0x46
142 
143 /*
144  * These commands will only work if the	FAS is connected as
145  * an initiator	to a target:
146  */
147 #define	CMD_TRAN_INFO	0x10
148 #define	CMD_COMP_SEQ	0x11
149 #define	CMD_MSG_ACPT	0x12
150 #define	CMD_TRAN_PAD	0x18
151 #define	CMD_SET_ATN	0x1a	/* (no interrupt generated) */
152 #define	CMD_CLR_ATN	0x1b	/* (no interrupt generated) */
153 
154 /*
155  * These commands will only work if the	FAS is connected as
156  * a target to an initiator:
157  */
158 #define	CMD_DISCONNECT	0x27	/* (no interrupt generated) */
159 
160 /*
161  * DMA enable bit
162  */
163 #define	CMD_DMA		0x80
164 
165 /*
166  * FAS fifo register definitions (read only)
167  */
168 #define	FIFOSIZE		16
169 #define	MAX_FIFO_FLAG		(FIFOSIZE-1)
170 #define	FAS_FIFO_ONZ		0x20
171 #define	FIFO_CNT_MASK		0x1f
172 
173 /*
174  * FAS status register definitions (read only)
175  */
176 #define	FAS_STAT_IPEND	0x80	/* interrupt pending */
177 #define	FAS_STAT_GERR	0x40	/* gross error */
178 #define	FAS_STAT_PERR	0x20	/* parity error	*/
179 #define	FAS_STAT_XZERO	0x10	/* transfer counter zero */
180 #define	FAS_STAT_XCMP	0x8	/* transfer completed (target mode only) */
181 #define	FAS_STAT_MSG	0x4	/* scsi	phase bit: MSG */
182 #define	FAS_STAT_CD	0x2	/* scsi	phase bit: CD */
183 #define	FAS_STAT_IO	0x1	/* scsi	phase bit: IO */
184 
185 #define	FAS_STAT_BITS	\
186 	"\20\10IPND\07GERR\06PERR\05XZERO\04XCMP\03MSG\02CD\01IO"
187 
188 /*
189  * settings of status to reflect different information transfer	phases
190  */
191 #define	FAS_PHASE_MASK		(FAS_STAT_MSG |	FAS_STAT_CD | FAS_STAT_IO)
192 #define	FAS_PHASE_DATA_OUT	0
193 #define	FAS_PHASE_DATA_IN	(FAS_STAT_IO)
194 #define	FAS_PHASE_COMMAND	(FAS_STAT_CD)
195 #define	FAS_PHASE_STATUS	(FAS_STAT_CD | FAS_STAT_IO)
196 #define	FAS_PHASE_MSG_OUT	(FAS_STAT_MSG |	FAS_STAT_CD)
197 #define	FAS_PHASE_MSG_IN	(FAS_STAT_MSG |	FAS_STAT_CD | FAS_STAT_IO)
198 
199 /*
200  * FAS interrupt status	register definitions (read only)
201  */
202 
203 #define	FAS_INT_RESET	0x80	/* SCSI	reset detected */
204 #define	FAS_INT_ILLEGAL	0x40	/* illegal cmd */
205 #define	FAS_INT_DISCON	0x20	/* disconnect */
206 #define	FAS_INT_BUS	0x10	/* bus service */
207 #define	FAS_INT_FCMP	0x8	/* function completed */
208 #define	FAS_INT_RESEL	0x4	/* reselected */
209 #define	FAS_INT_SELATN	0x2	/* selected with ATN */
210 #define	FAS_INT_SEL	0x1	/* selected without ATN	*/
211 
212 #define	FAS_INT_BITS	\
213 	"\20\10RST\07ILL\06DISC\05BUS\04FCMP\03RESEL\02SATN\01SEL"
214 
215 /*
216  * FAS step register- only the least significant 3 bits	are valid
217  */
218 #define	FAS_STEP_MASK	0x7
219 
220 #define	FAS_STEP_ARBSEL	0	/* Arbitration and select completed. */
221 				/* Not MESSAGE OUT phase. ATN* asserted. */
222 
223 #define	FAS_STEP_SENTID	1	/* Sent	one message byte. ATN* asserted. */
224 				/* (SELECT AND STOP command only). */
225 
226 #define	FAS_STEP_NOTCMD	2	/* For SELECT WITH ATN command:	*/
227 				/*	Sent one message byte. ATN* off. */
228 				/*	Not COMMAND phase. */
229 				/* For SELECT WITHOUT ATN command: */
230 				/*	Not COMMAND phase. */
231 				/* For SELECT WITH ATN3	command: */
232 				/*	Sent one to three message bytes. */
233 				/*	Stopped	due to unexpected phase	*/
234 				/*	change.	If third message byte */
235 				/*	not sent, ATN* asserted.  */
236 
237 #define	FAS_STEP_PCMD	3	/* Not all of command bytes transferred	*/
238 				/* due to premature phase change. */
239 
240 #define	FAS_STEP_DONE	4	/* Complete sequence. */
241 
242 /*
243  * FAS configuration register definitions (read/write)
244  */
245 #define	FAS_CONF_SLOWMODE	0x80	/* slow	cable mode */
246 #define	FAS_CONF_DISRINT	0x40	/* disable reset int */
247 #define	FAS_CONF_PARTEST	0x20	/* parity test mode */
248 #define	FAS_CONF_PAREN		0x10	/* enable parity */
249 #define	FAS_CONF_CHIPTEST	0x8	/* chip	test mode */
250 #define	FAS_CONF_BUSID		0x7	/* last	3 bits to be host id */
251 
252 #define	DEFAULT_HOSTID		7
253 
254 /*
255  * FAS test register definitions (read/write)
256  */
257 #define	FAS_TEST_TGT		0x1	/* target test mode */
258 #define	FAS_TEST_INI		0x2	/* initiator test mode */
259 #define	FAS_TEST_TRI		0x4	/* tristate test mode */
260 
261 /*
262  * FAS configuration register #2 definitions (read/write)
263  */
264 #define	FAS_CONF2_XL32		0x80
265 #define	FAS_CONF2_MKDONE	0x40
266 #define	FAS_CONF2_PAUSE_INTR_DISABLE 0x20
267 #define	FAS_CONF2_FENABLE	0x10	/* Features Enable */
268 #define	FAS_CONF2_SCSI2		0x8	/* SCSI-2 mode (target mode only) */
269 #define	FAS_CONF2_TGT_BAD_PRTY_ABORT 0x4
270 #define	FAS_CONF2_DMA_PRTY_ENABLE    0x1
271 
272 /*
273  * FAS configuration #3	register definitions (read/write)
274  */
275 #define	FAS_CONF3_ODDBYTE_AUTO	0x80	/* auto push an odd-byte to dma */
276 #define	FAS_CONF3_WIDE		0x40	/* enables wide	*/
277 #define	FAS_CONF3_IDBIT3	0x20	/* extends scsi	bus ID to 4 bits */
278 #define	FAS_CONF3_IDRESCHK	0x10	/* ID message checking */
279 #define	FAS_CONF3_QUENB		0x8	/* 3-byte msg support */
280 #define	FAS_CONF3_CDB10		0x4	/* group 2 scsi-2 support */
281 #define	FAS_CONF3_FASTSCSI	0x2	/* 10 MB/S fast	scsi mode */
282 #define	FAS_CONF3_FASTCLK	0x1	/* fast	clock mode */
283 
284 /*
285  * FAS configuration #4 register definitions
286  */
287 #define	FAS_CONF4_PADMSGS	0x20
288 
289 /*
290  * FAS part-unique id code definitions (read only)
291  */
292 #define	FAS_REV_MASK		0x7	/* revision level mask */
293 #define	FAS_FCODE_MASK		0xf8	/* revision family code	mask */
294 
295 /*
296  * Macros to get/set an	integer	word into the 4 8-bit
297  * registers that constitute the FAS's counter register.
298  */
299 #define	SET_FAS_COUNT(fasreg, val) {	\
300 	fas_reg_write(fas, &fasreg->fas_xcnt_lo, (uint8_t)val); \
301 	fas_reg_write(fas, &fasreg->fas_xcnt_mid, \
302 		(uint8_t)(val >>	8)); \
303 	fas_reg_write(fas, &fasreg->fas_recmd_lo, \
304 		((uint8_t)(val >> 16)));	\
305 	fas_reg_write(fas, &fasreg->fas_recmd_hi, 0); \
306 }
307 
308 /*
309  * to save time, read back 3 registers
310  */
311 #define	GET_FAS_COUNT(fasreg, val) {	\
312 	uint8_t lo, mid, r_lo; \
313 	lo = fas_reg_read(fas, &fasreg->fas_xcnt_lo); \
314 	mid = fas_reg_read(fas,	&fasreg->fas_xcnt_mid);	\
315 	r_lo = fas_reg_read(fas, &fasreg->fas_recmd_lo); \
316 	(val) =	(uint32_t)(lo | (mid << 8) | ((r_lo) << 16)); \
317 }
318 
319 
320 
321 /*
322  * FAS Clock constants
323  */
324 
325 /*
326  * The probe routine will select amongst these values
327  * and stuff it	into the tag f_clock_conv in the private host
328  * adapter structure (see below) (as well as the the register fas_clock_conv
329  * on the chip)
330  */
331 #define	CLOCK_10MHZ		2
332 #define	CLOCK_15MHZ		3
333 #define	CLOCK_20MHZ		4
334 #define	CLOCK_25MHZ		5
335 #define	CLOCK_30MHZ		6
336 #define	CLOCK_35MHZ		7
337 #define	CLOCK_40MHZ		8	/* really 0 */
338 #define	CLOCK_MASK		0x7
339 
340 /*
341  * This	yields nanoseconds per input clock tick
342  */
343 
344 #define	CLOCK_PERIOD(mhz)	(1000 *	MEG) / (mhz / 1000)
345 #define	CONVERT_PERIOD(time)	((time) + 3) >> 2
346 
347 /*
348  * Formula to compute the select/reselect timeout register value:
349  *
350  *	Time_unit = 7682 * CCF * Input_Clock_Period
351  *
352  * where Time_unit && Input_Clock_Period should	be in the same units.
353  * CCF = Clock Conversion Factor from CLOCK_XMHZ above.
354  * Desired_Timeout_Period = 250	ms.
355  *
356  */
357 #define	FAS_CLOCK_DELAY	7682
358 #define	FAS_CLOCK_TICK(fas)	\
359 	((uint_t)FAS_CLOCK_DELAY * (uint_t)(fas)->f_clock_conv * \
360 	(uint_t)(fas)->f_clock_cycle) / (uint_t)1000
361 #define	FAS_SEL_TIMEOUT	(250 * MEG)
362 #define	FAS_CLOCK_TIMEOUT(tick,	selection_timeout) \
363 	(((selection_timeout) *	MEG) + (tick) -	1) / (tick)
364 
365 /*
366  * Max/Min number of clock cycles for synchronous period
367  */
368 #define	MIN_SYNC_FAST(fas)	4
369 #define	MIN_SYNC_SLOW(fas)	\
370 	(((fas)->e_fasconf & FAS_CONF_SLOWMODE) ? 6 : 5)
371 #define	MIN_SYNC(fas)		(MIN_SYNC_FAST((fas)))
372 #define	MAX_SYNC(fas)		35
373 #define	SYNC_PERIOD_MASK	0x1F
374 
375 /*
376  * Max/Min time	(in nanoseconds) between successive Req/Ack
377  */
378 #define	MIN_SYNC_TIME(fas)	\
379 	((uint_t)MIN_SYNC((fas)) * (uint_t)((fas)->f_clock_cycle)) / \
380 	    (uint_t)1000
381 #define	MAX_SYNC_TIME(fas)	\
382 	((uint_t)MAX_SYNC((fas)) * (uint_t)((fas)->f_clock_cycle)) / \
383 	    (uint_t)1000
384 
385 /*
386  * Max/Min Period values (appropriate for SYNCHRONOUS message).
387  * We round up here to make sure that we are always slower
388  * (longer time	period).
389  */
390 #define	MIN_SYNC_PERIOD(fas)	(CONVERT_PERIOD(MIN_SYNC_TIME((fas))))
391 #define	MAX_SYNC_PERIOD(fas)	(CONVERT_PERIOD(MAX_SYNC_TIME((fas))))
392 
393 /*
394  * According to	the Emulex application notes for this part,
395  * the ability to receive synchronous data is independent
396  * of the FAS chip's input clock rate, and is fixed at
397  * a maximum 5.6 mb/s (180 ns/byte).
398  *
399  * Therefore, we could tell targets that we can	*receive*
400  * synchronous data this fast.
401  * However, the	rest of	the transfer is	still at 5.0 MB/sec so to keep it
402  * simple, we negotiate	200 ns
403  * On a	c2,  a period of 45 and	50 result in the same register value (8) and
404  * consequently	5 MB/sec.
405  */
406 #define	DEFAULT_SYNC_PERIOD		200		/* 5.0 MB/s */
407 #define	DEFAULT_FASTSYNC_PERIOD		100		/* 10.0	MB/s */
408 #define	FASTSCSI_THRESHOLD		50		/* 5.0 MB/s */
409 
410 /*
411  * Short hand macro convert parameter in
412  * nanoseconds/byte into k-bytes/second.
413  */
414 #define	FAS_SYNC_KBPS(ns)	((((1000 * MEG) / (ns)) + 999) / 1000)
415 
416 /*
417  * Default Synchronous offset.
418  * (max	# of allowable outstanding REQ)
419  * IBS allows only 11 bytes offset
420  */
421 #define	DEFAULT_OFFSET	15
422 
423 /*
424  * Chip	type defines &&	macros
425  */
426 #define	FAS366		0
427 #define	FAST		5
428 
429 /* status register #2 definitions (read	only) */
430 #define	FAS_STAT2_SEQCNT   0x01	   /* Sequence counter bit 7-3 enabled */
431 #define	FAS_STAT2_FLATCHED 0x02	   /* FIFO flags register latched */
432 #define	FAS_STAT2_CLATCHED 0x04	   /* Xfer cntr	& recommand ctr	latched */
433 #define	FAS_STAT2_CACTIVE  0x08	   /* Command register is active */
434 #define	FAS_STAT2_SCSI16   0x10	   /* SCSI interface is	wide */
435 #define	FAS_STAT2_ISHUTTLE 0x20	   /* FIFO Top register	contains 1 byte */
436 #define	FAS_STAT2_OSHUTTLE 0x40	   /* next byte	from FIFO is MSB */
437 #define	FAS_STAT2_EMPTY	   0x80	   /* FIFO is empty */
438 
439 /*
440  * select/reselect bus id register
441  */
442 #define	FAS_BUSID_ENCODID	0x10	/* encode reselection ID */
443 #define	FAS_BUSID_32BIT_COUNTER	0x40	/* xfer	counter	is 32 bit */
444 
445 #ifdef	__cplusplus
446 }
447 #endif
448 
449 #endif	/* _SYS_SCSI_ADAPTERS_FASREG_H */
450