1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _HXGE_PFC_H 28 #define _HXGE_PFC_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 0 and 4095 are reserved */ 37 #define VLAN_ID_MIN 1 38 #define VLAN_ID_MAX 4094 39 #define VLAN_ID_IMPLICIT 0 40 41 #define HXGE_MAC_DEFAULT_ADDR_SLOT 0 42 43 #define HASH_BITS 8 44 #define NMCFILTER_BITS (1 << HASH_BITS) 45 #define HASH_REG_WIDTH 16 46 #define NMCFILTER_REGS (NMCFILTER_BITS / HASH_REG_WIDTH) 47 /* Number of multicast filter regs */ 48 #define MAC_MAX_HASH_ENTRY NMCFILTER_REGS 49 50 #define REG_PIO_WRITE64(handle, offset, value) \ 51 HXGE_REG_WR64((handle), (offset), (value)) 52 #define REG_PIO_READ64(handle, offset, val_p) \ 53 HXGE_REG_RD64((handle), (offset), (val_p)) 54 55 #define TCAM_CTL_RWC_TCAM_WR 0x0 56 #define TCAM_CTL_RWC_TCAM_CMP 0x2 57 #define TCAM_CTL_RWC_RAM_WR 0x4 58 #define TCAM_CTL_RWC_RAM_RD 0x5 59 #define TCAM_CTL_RWC_RWC_STAT 0x1 60 #define TCAM_CTL_RWC_RWC_MATCH 0x1 61 62 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 63 REG_PIO_WRITE64(handle, PFC_TCAM_CTRL, ctl) 64 65 #define READ_TCAM_REG_CTL(handle, val_p) \ 66 REG_PIO_READ64(handle, PFC_TCAM_CTRL, val_p) 67 68 #define WRITE_TCAM_REG_KEY0(handle, key) \ 69 REG_PIO_WRITE64(handle, PFC_TCAM_KEY0, key) 70 #define WRITE_TCAM_REG_KEY1(handle, key) \ 71 REG_PIO_WRITE64(handle, PFC_TCAM_KEY1, key) 72 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 73 REG_PIO_WRITE64(handle, PFC_TCAM_MASK0, mask) 74 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 75 REG_PIO_WRITE64(handle, PFC_TCAM_MASK1, mask) 76 77 #define READ_TCAM_REG_KEY0(handle, val_p) \ 78 REG_PIO_READ64(handle, PFC_TCAM_KEY0, val_p) 79 #define READ_TCAM_REG_KEY1(handle, val_p) \ 80 REG_PIO_READ64(handle, PFC_TCAM_KEY1, val_p) 81 #define READ_TCAM_REG_MASK0(handle, val_p) \ 82 REG_PIO_READ64(handle, PFC_TCAM_MASK0, val_p) 83 #define READ_TCAM_REG_MASK1(handle, val_p) \ 84 REG_PIO_READ64(handle, PFC_TCAM_MASK1, val_p) 85 86 typedef union _hxge_tcam_res_t { 87 uint64_t value; 88 struct { 89 #if defined(_BIG_ENDIAN) 90 uint32_t padding:32; 91 uint32_t padding_l:2; 92 uint32_t reserved:15; 93 uint32_t parity:1; 94 uint32_t hit_count:4; 95 uint32_t channel_d:2; 96 uint32_t channel_c:2; 97 uint32_t channel_b:2; 98 uint32_t channel_a:2; 99 uint32_t source_hash:1; 100 uint32_t discard:1; 101 #else 102 uint32_t discard:1; 103 uint32_t source_hash:1; 104 uint32_t channel_a:2; 105 uint32_t channel_b:2; 106 uint32_t channel_c:2; 107 uint32_t channel_d:2; 108 uint32_t hit_count:4; 109 uint32_t parity:1; 110 uint32_t reserved:15; 111 uint32_t padding_l:2; 112 uint32_t padding:32; 113 #endif 114 } bits; 115 } hxge_tcam_res_t, *p_hxge_tcam_res_t; 116 117 typedef struct tcam_reg { 118 #if defined(_BIG_ENDIAN) 119 uint64_t reg1; /* 99:64 */ 120 uint64_t reg0; /* 63:0 */ 121 #else 122 uint64_t reg0; /* 63:0 */ 123 uint64_t reg1; /* 99:64 */ 124 #endif 125 } hxge_tcam_reg_t; 126 127 typedef struct hxge_tcam_ipv4_S { 128 #if defined(_BIG_ENDIAN) 129 uint32_t class_code:4; /* 99:96 */ 130 uint32_t class_code_l:1; /* 95:95 */ 131 uint32_t blade_id:4; /* 94:91 */ 132 uint32_t rsrvd2:2; /* 90:89 */ 133 uint32_t noport:1; /* 88 */ 134 uint32_t protocol:8; /* 87:80 */ 135 uint32_t l4_hdr:16; /* 79:64 */ 136 uint32_t l4_hdr_l:16; /* 63:48 */ 137 uint32_t rsrvd:16; /* 47:32 */ 138 uint32_t ip_daddr; /* 31:0 */ 139 #else 140 uint32_t ip_daddr; /* 31:0 */ 141 uint32_t rsrvd:16; /* 47:32 */ 142 uint32_t l4_hdr_l:16; /* 63:48 */ 143 uint32_t l4_hdr:16; /* 79:64 */ 144 uint32_t protocol:8; /* 87:80 */ 145 uint32_t noport:1; /* 88 */ 146 uint32_t rsrvd2:2; /* 90:89 */ 147 uint32_t blade_id:4; /* 94:91 */ 148 uint32_t class_code_l:1; /* 95:95 */ 149 uint32_t class_code:4; /* 99:96 */ 150 #endif 151 } hxge_tcam_ipv4_t; 152 153 typedef struct hxge_tcam_ipv6_S { 154 #if defined(_BIG_ENDIAN) 155 uint32_t class_code:4; /* 99:96 */ 156 uint32_t class_code_l:1; /* 95:95 */ 157 uint32_t blade_id:4; /* 94:91 */ 158 uint32_t rsrvd2:3; /* 90:88 */ 159 uint32_t protocol:8; /* 87:80 */ 160 uint32_t l4_hdr:16; /* 79:64 */ 161 uint32_t l4_hdr_l:16; /* 63:48 */ 162 uint32_t rsrvd:16; /* 47:32 */ 163 uint32_t rsrvd_l:32; /* 31:0 */ 164 #else 165 uint32_t rsrvd_l:32; /* 31:0 */ 166 uint32_t rsrvd:16; /* 47:32 */ 167 uint32_t l4_hdr_l:16; /* 63:48 */ 168 uint32_t l4_hdr:16; /* 79:64 */ 169 uint32_t protocol:8; /* 87:80 */ 170 uint32_t rsrvd2:3; /* 90:88 */ 171 uint32_t blade_id:4; /* 94:91 */ 172 uint32_t class_code_l:1; /* 95:95 */ 173 uint32_t class_code:4; /* 99:96 */ 174 #endif 175 } hxge_tcam_ipv6_t; 176 177 typedef struct hxge_tcam_enet_S { 178 #if defined(_BIG_ENDIAN) 179 uint8_t class_code:4; /* 99:96 */ 180 uint8_t class_code_l:1; /* 95:95 */ 181 uint8_t blade_id:4; /* 94:91 */ 182 uint8_t rsrvd:3; /* 90:88 */ 183 uint8_t eframe[11]; /* 87:0 */ 184 #else 185 uint8_t eframe[11]; /* 87:0 */ 186 uint8_t rsrvd:3; /* 90:88 */ 187 uint8_t blade_id:4; /* 94:91 */ 188 uint8_t class_code_l:1; /* 95:95 */ 189 uint8_t class_code:4; /* 99:96 */ 190 #endif 191 } hxge_tcam_ether_t; 192 193 typedef struct hxge_tcam_spread_S { 194 #if defined(_BIG_ENDIAN) 195 uint32_t unused:28; /* 127:100 */ 196 uint32_t class_code:4; /* 99:96 */ 197 uint32_t class_code_l:1; /* 95:95 */ 198 uint32_t blade_id:4; /* 94:91 */ 199 uint32_t wild1:27; /* 90:64 */ 200 uint32_t wild; /* 63:32 */ 201 uint32_t wild_l; /* 31:0 */ 202 #else 203 uint32_t wild_l; /* 31:0 */ 204 uint32_t wild; /* 63:32 */ 205 uint32_t wild1:27; /* 90:64 */ 206 uint32_t blade_id:4; /* 94:91 */ 207 uint32_t class_code_l:1; /* 95:95 */ 208 uint32_t class_code:4; /* 99:96 */ 209 uint32_t unused:28; /* 127:100 */ 210 #endif 211 } hxge_tcam_spread_t; 212 213 typedef struct hxge_tcam_entry_S { 214 union _hxge_tcam_entry { 215 hxge_tcam_ipv4_t ipv4; 216 hxge_tcam_ipv6_t ipv6; 217 hxge_tcam_ether_t enet; 218 hxge_tcam_reg_t regs; 219 hxge_tcam_spread_t spread; 220 } key, mask; 221 hxge_tcam_res_t match_action; 222 uint16_t ether_type; 223 } hxge_tcam_entry_t; 224 225 #define key_reg0 key.regs.reg0 226 #define key_reg1 key.regs.reg1 227 #define mask_reg0 mask.regs.reg0 228 #define mask_reg1 mask.regs.reg1 229 230 #define key0 key.regs.reg0 231 #define key1 key.regs.reg1 232 #define mask0 mask.regs.reg0 233 #define mask1 mask.regs.reg1 234 235 #define ip4_class_key key.ipv4.class_code 236 #define ip4_class_key_l key.ipv4.class_code_l 237 #define ip4_blade_id_key key.ipv4.blade_id 238 #define ip4_noport_key key.ipv4.noport 239 #define ip4_proto_key key.ipv4.protocol 240 #define ip4_l4_hdr_key key.ipv4.l4_hdr 241 #define ip4_l4_hdr_key_l key.ipv4.l4_hdr_l 242 #define ip4_dest_key key.ipv4.ip_daddr 243 244 #define ip4_class_mask mask.ipv4.class_code 245 #define ip4_class_mask_l mask.ipv4.class_code_l 246 #define ip4_blade_id_mask mask.ipv4.blade_id 247 #define ip4_noport_mask mask.ipv4.noport 248 #define ip4_proto_mask mask.ipv4.protocol 249 #define ip4_l4_hdr_mask mask.ipv4.l4_hdr 250 #define ip4_l4_hdr_mask_l mask.ipv4.l4_hdr_l 251 #define ip4_dest_mask mask.ipv4.ip_daddr 252 253 #define ip6_class_key key.ipv6.class_code 254 #define ip6_class_key_l key.ipv6.class_code_l 255 #define ip6_blade_id_key key.ipv6.blade_id 256 #define ip6_proto_key key.ipv6.protocol 257 #define ip6_l4_hdr_key key.ipv6.l4_hdr 258 #define ip6_l4_hdr_key_l key.ipv6.l4_hdr_l 259 260 #define ip6_class_mask mask.ipv6.class_code 261 #define ip6_class_mask_l mask.ipv6.class_code_l 262 #define ip6_blade_id_mask mask.ipv6.blade_id 263 #define ip6_proto_mask mask.ipv6.protocol 264 #define ip6_l4_hdr_mask mask.ipv6.l4_hdr 265 #define ip6_l4_hdr_mask_l mask.ipv6.l4_hdr_l 266 267 #define ether_class_key key.enet.class_code 268 #define ether_class_key_l key.enet.class_code_l 269 #define ether_blade_id_key key.enet.blade_id 270 #define ether_ethframe_key key.enet.eframe 271 272 #define ether_class_mask mask.enet.class_code 273 #define ether_class_mask_l mask.enet.class_code_l 274 #define ether_blade_id_mask mask.enet.blade_id 275 #define ether_ethframe_mask mask.enet.eframe 276 277 typedef struct _pfc_errlog { 278 uint32_t tcp_ctrl_drop; /* pfc_drop_log */ 279 uint32_t l2_addr_drop; 280 uint32_t class_code_drop; 281 uint32_t tcam_drop; 282 uint32_t vlan_drop; 283 284 uint32_t vlan_par_err_log; /* pfc_vlan_par_err_log */ 285 uint32_t tcam_par_err_log; /* pfc_tcam_par_err_log */ 286 } pfc_errlog_t, *p_pfc_errlog_t; 287 288 typedef struct _pfc_stats { 289 uint32_t pkt_drop; /* pfc_int_status */ 290 uint32_t tcam_parity_err; 291 uint32_t vlan_parity_err; 292 293 uint32_t bad_cs_count; /* pfc_bad_cs_counter */ 294 uint32_t drop_count; /* pfc_drop_counter */ 295 pfc_errlog_t errlog; 296 } hxge_pfc_stats_t, *p_hxge_pfc_stats_t; 297 298 typedef enum pfc_tcam_class { 299 TCAM_CLASS_INVALID = 0, 300 TCAM_CLASS_DUMMY = 1, 301 TCAM_CLASS_ETYPE_1 = 2, 302 TCAM_CLASS_ETYPE_2, 303 TCAM_CLASS_RESERVED_4, 304 TCAM_CLASS_RESERVED_5, 305 TCAM_CLASS_RESERVED_6, 306 TCAM_CLASS_RESERVED_7, 307 TCAM_CLASS_TCP_IPV4, 308 TCAM_CLASS_UDP_IPV4, 309 TCAM_CLASS_AH_ESP_IPV4, 310 TCAM_CLASS_SCTP_IPV4, 311 TCAM_CLASS_TCP_IPV6, 312 TCAM_CLASS_UDP_IPV6, 313 TCAM_CLASS_AH_ESP_IPV6, 314 TCAM_CLASS_SCTP_IPV6, 315 TCAM_CLASS_ARP, 316 TCAM_CLASS_RARP, 317 TCAM_CLASS_DUMMY_12, 318 TCAM_CLASS_DUMMY_13, 319 TCAM_CLASS_DUMMY_14, 320 TCAM_CLASS_DUMMY_15, 321 TCAM_CLASS_MAX 322 } tcam_class_t; 323 324 typedef struct _tcam_key_cfg_t { 325 boolean_t lookup_enable; 326 boolean_t discard; 327 } tcam_key_cfg_t; 328 329 typedef struct _hash_filter_t { 330 uint_t hash_ref_cnt; 331 uint16_t hash_filter_regs[NMCFILTER_REGS]; 332 uint32_t hash_bit_ref_cnt[NMCFILTER_BITS]; 333 } hash_filter_t, *p_hash_filter_t; 334 335 #define HXGE_ETHER_FLOWS (FLOW_ETHER_DHOST | FLOW_ETHER_SHOST | \ 336 FLOW_ETHER_TYPE) 337 #define HXGE_VLAN_FLOWS (FLOW_ETHER_TPID | FLOW_ETHER_TCI) 338 #define HXGE_ETHERNET_FLOWS (HXGE_ETHER_FLOWS | HXGE_VLAN_FLOWS) 339 #define HXGE_PORT_FLOWS (FLOW_ULP_PORT_REMOTE | FLOW_ULP_PORT_LOCAL) 340 #define HXGE_ADDR_FLOWS (FLOW_IP_REMOTE | FLOW_IP_LOCAL) 341 #define HXGE_IP_FLOWS (FLOW_IP_VERSION | FLOW_IP_PROTOCOL | \ 342 HXGE_PORT_FLOWS | HXGE_ADDR_FLOWS) 343 #define HXGE_SUPPORTED_FLOWS (HXGE_ETHERNET_FLOWS | HXGE_IP_FLOWS) 344 345 #define CLS_CODE_MASK 0x1f 346 #define BLADE_ID_MASK 0xf 347 #define PID_MASK 0xff 348 #define IP_PORT_MASK 0xffff 349 350 #define IP_ADDR_SA_MASK 0xFFFFFFFF 351 #define IP_ADDR_DA_MASK IP_ADDR_SA_MASK 352 #define L4PT_SPI_MASK IP_ADDR_SA_MASK 353 354 #define BLADE_ID_OFFSET 127 /* Last entry in HCR_REG */ 355 356 #ifdef __cplusplus 357 } 358 #endif 359 360 #endif /* !_HXGE_PFC_H */ 361