Searched refs:XHRE (Results 1 – 6 of 6) sorted by relevance
49 #define XHRE 0x20 /* ... xmit hold buffer empty */ macro
792 while (((inb(port + LSR) & XHRE) == 0) && checks--) in serial_putchar()
107 #define XHRE 0x20 /* tx hold reg is now empty */ macro
104 #define XHRE 0x20 /* tx hold reg is now empty */ macro
700 if ((lsr & (XSRE | XHRE)) == (XSRE | XHRE)) in asydetach()1965 asy->asy_ioaddr + LSR) & (XSRE|XHRE)) == 0)); in asy_isbusy()2300 if ((lsr & XHRE) && (async->async_flags & ASYNC_BUSY) && in asyintr()3192 XHRE)) in async_nstart()3227 if (ddi_get8(asy->asy_iohandle, asy->asy_ioaddr + LSR) & XHRE) { in async_resume()4202 asy->asy_ioaddr + LSR) & XHRE) == 0) { in asyputchar()4639 (ddi_get8(asy->asy_iohandle, asy->asy_ioaddr + LSR) & XHRE)) { in async_flowcontrol_sw_input()
1529 while ((INB(LSR) & XHRE) == 0) { in asyputchar()1763 if (lsr & XHRE) { in async_txint()2719 if (INB(LSR) & XHRE) { in async_nstart()2748 if (INB(LSR) & XHRE) { in async_resume()3715 if ((ss = async->async_flowc) != '\0' && (INB(LSR) & XHRE)) { in asycheckflowcontrol_sw()