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Searched refs:XGE_HAL_OK (Results 1 – 18 of 18) sorted by relevance

/titanic_41/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-device-fp.c197 return XGE_HAL_OK; in xge_hal_device_begin_irq()
201 return XGE_HAL_OK; in xge_hal_device_begin_irq()
209 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
218 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
227 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
236 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
245 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
254 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
263 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
272 if (status != XGE_HAL_OK) { in xge_hal_device_begin_irq()
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H A Dxgehal-config.c87 return XGE_HAL_OK; in __hal_tti_config_check()
145 return XGE_HAL_OK; in __hal_rti_config_check()
200 &new_queue->tti[i])) != XGE_HAL_OK) { in __hal_fifo_queue_check()
206 return XGE_HAL_OK; in __hal_fifo_queue_check()
356 return XGE_HAL_OK; in __hal_mac_config_check()
402 &new_config->queue[i])) != XGE_HAL_OK) { in __hal_fifo_config_check()
413 return XGE_HAL_OK; in __hal_fifo_config_check()
440 != XGE_HAL_OK) { in __hal_ring_config_check()
445 return XGE_HAL_OK; in __hal_ring_config_check()
653 != XGE_HAL_OK) { in __hal_device_config_check_common()
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H A Dxgehal-mgmtaux.c92 if (status != XGE_HAL_OK) { in xge_hal_aux_bar0_read()
103 return XGE_HAL_OK; in xge_hal_aux_bar0_read()
132 if (status != XGE_HAL_OK) in xge_hal_aux_bar1_read()
141 return XGE_HAL_OK; in xge_hal_aux_bar1_read()
166 if (status != XGE_HAL_OK) { in xge_hal_aux_bar0_write()
170 return XGE_HAL_OK; in xge_hal_aux_bar0_write()
199 if (status != XGE_HAL_OK) { in xge_hal_aux_about_read()
225 return XGE_HAL_OK; in xge_hal_aux_about_read()
259 if (status != XGE_HAL_OK) { in xge_hal_aux_stats_tmac_read()
292 if (status != XGE_HAL_OK) { in xge_hal_aux_stats_tmac_read()
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H A Dxgehal-mgmt.c115 return XGE_HAL_OK; in xge_hal_mgmt_about()
171 return XGE_HAL_OK; in xge_hal_mgmt_reg_read()
228 return XGE_HAL_OK; in xge_hal_mgmt_reg_write()
264 if ((status = xge_hal_stats_hw (devh, &hw_info)) != XGE_HAL_OK) { in xge_hal_mgmt_hw_stats()
270 return XGE_HAL_OK; in xge_hal_mgmt_hw_stats()
304 if ((status = xge_hal_stats_hw (devh, &hw_info)) != XGE_HAL_OK) { in xge_hal_mgmt_hw_stats_off()
310 return XGE_HAL_OK; in xge_hal_mgmt_hw_stats_off()
346 if ((status = xge_hal_stats_pcim (devh, &pcim_info)) != XGE_HAL_OK) { in xge_hal_mgmt_pcim_stats()
353 return XGE_HAL_OK; in xge_hal_mgmt_pcim_stats()
388 if ((status = xge_hal_stats_pcim (devh, &pcim_info)) != XGE_HAL_OK) { in xge_hal_mgmt_pcim_stats_off()
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H A Dxgehal-device.c139 return XGE_HAL_OK; in __hal_device_register_poll()
141 return XGE_HAL_OK; in __hal_device_register_poll()
148 return XGE_HAL_OK; in __hal_device_register_poll()
150 return XGE_HAL_OK; in __hal_device_register_poll()
1021 XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { in __hal_device_tti_apply()
1033 return XGE_HAL_OK; in __hal_device_tti_apply()
1066 if (status != XGE_HAL_OK) in __hal_device_tti_configure()
1083 if (status != XGE_HAL_OK) in __hal_device_tti_configure()
1088 return XGE_HAL_OK; in __hal_device_tti_configure()
1181 XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { in __hal_device_rti_configure()
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H A Dxgehal-channel.c47 return XGE_HAL_OK; in __hal_channel_dtr_next_reservelist()
66 return XGE_HAL_OK; in __hal_channel_dtr_next_freelist()
92 return XGE_HAL_OK; in __hal_channel_dtr_next_not_completed()
221 return XGE_HAL_OK; in __hal_channel_initialize()
302 xge_hal_status_e status = XGE_HAL_OK; in xge_hal_channel_open()
351 if (status == XGE_HAL_OK) { in xge_hal_channel_open()
374 if (status != XGE_HAL_OK) in xge_hal_channel_open()
411 return XGE_HAL_OK; in xge_hal_channel_open()
442 while (__hal_channel_dtr_next_freelist(channelh, &dtr) == XGE_HAL_OK) { in xge_hal_channel_abort()
461 XGE_HAL_OK) { in xge_hal_channel_abort()
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H A Dxgehal-fifo-fp.c259 xge_hal_status_e status = XGE_HAL_OK; in xge_hal_fifo_dtr_reserve_many()
281 if (status != XGE_HAL_OK){ in xge_hal_fifo_dtr_reserve_many()
349 if (status == XGE_HAL_OK) { in xge_hal_fifo_dtr_reserve_many()
425 if (status == XGE_HAL_OK) { in xge_hal_fifo_dtr_reserve()
481 return XGE_HAL_OK; in xge_hal_fifo_dtr_reserve_sp()
691 return XGE_HAL_OK; in xge_hal_fifo_dtr_next_completed()
902 return XGE_HAL_OK; in xge_hal_fifo_dtr_buffer_set_aligned()
947 return XGE_HAL_OK; in xge_hal_fifo_dtr_buffer_append()
1157 return XGE_HAL_OK; in xge_hal_fifo_is_next_dtr_completed()
H A Dxgehal-ring.c205 return XGE_HAL_OK; in __hal_ring_mempool_item_alloc()
218 xge_assert(status == XGE_HAL_OK); in __hal_ring_initial_replenish()
225 if (status != XGE_HAL_OK) { in __hal_ring_initial_replenish()
236 return XGE_HAL_OK; in __hal_ring_initial_replenish()
309 if (status != XGE_HAL_OK) { in __hal_ring_open()
330 != XGE_HAL_OK) { in __hal_ring_open()
340 return XGE_HAL_OK; in __hal_ring_open()
H A Dxgehal-driver.c120 return XGE_HAL_OK; in xge_hal_driver_tracebuf_read()
206 if (status != XGE_HAL_OK) in xge_hal_driver_initialize()
243 return XGE_HAL_OK; in xge_hal_driver_initialize()
H A Dxgehal-fifo.c75 if (status != XGE_HAL_OK) { in __hal_fifo_mempool_item_alloc()
93 return XGE_HAL_OK; in __hal_fifo_mempool_item_alloc()
146 return XGE_HAL_OK; in __hal_fifo_mempool_item_free()
269 if (status != XGE_HAL_OK) { in __hal_fifo_open()
309 return XGE_HAL_OK; in __hal_fifo_open()
553 return XGE_HAL_OK; in __hal_fifo_dtr_align_alloc_map()
H A Dxgehal-mm.c151 mempool->userdata)) != XGE_HAL_OK) { in __hal_mempool_grow()
207 return XGE_HAL_OK; in __hal_mempool_grow()
335 if (status != XGE_HAL_OK) { in __hal_mempool_create()
H A Dxgehal-stats.c180 return XGE_HAL_OK; in __hal_stats_initialize()
760 return XGE_HAL_OK; in xge_hal_stats_hw()
805 return XGE_HAL_OK; in xge_hal_stats_pcim()
843 return XGE_HAL_OK; in xge_hal_stats_device()
935 return XGE_HAL_OK; in xge_hal_stats_channel()
966 return XGE_HAL_OK; in xge_hal_stats_reset()
H A Dxgehal-ring-fp.c158 if (status == XGE_HAL_OK) { in xge_hal_ring_dtr_reserve()
733 return XGE_HAL_OK; in xge_hal_ring_dtr_next_completed()
835 return XGE_HAL_OK; in xge_hal_ring_is_next_dtr_completed()
H A Dxgehal-channel-fp.c52 return XGE_HAL_OK; in __hal_channel_dtr_alloc()
/titanic_41/usr/src/uts/common/io/xge/drv/
H A Dxgell.c207 (xge_hal_ring_dtr_reserve(ring->channelh, &dtr) == XGE_HAL_OK)) { in xgell_rx_buffer_replenish_all()
557 return (XGE_HAL_OK); in xgell_rx_dtr_replenish()
844 XGE_HAL_OK); in xgell_rx_1b_callback()
861 return (XGE_HAL_OK); in xgell_rx_1b_callback()
933 XGE_HAL_OK); in xgell_xmit_compl()
938 return (XGE_HAL_OK); in xgell_xmit_compl()
983 if (status != XGE_HAL_OK) { in xgell_ring_tx()
1056 if (rc == XGE_HAL_OK) { in xgell_ring_tx()
1288 ring->mmac.mac_addr + slot) != XGE_HAL_OK) { in xgell_addmac()
1346 if (status != XGE_HAL_OK) { in xgell_remmac()
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H A Dxge.c153 if (status != XGE_HAL_OK) { in _init()
1232 if (status != XGE_HAL_OK) { in xge_attach()
/titanic_41/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-types.h346 XGE_HAL_OK = 0, enumerator
H A Dxgehal-device.h733 return XGE_HAL_OK; in xge_hal_device_mtu_check()