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Searched refs:XGE_HAL_MAX_RING_NUM (Results 1 – 8 of 8) sorted by relevance

/titanic_41/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-ring.c490 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_ring_hw_initialize()
503 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_ring_hw_initialize()
525 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) in __hal_ring_hw_initialize()
546 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_ring_hw_initialize()
604 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_ring_hw_initialize()
640 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_ring_mtu_set()
H A Dxgehal-device.c909 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) { in __hal_device_bimodal_configure()
1072 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) { in __hal_device_tti_configure()
1119 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) { in __hal_device_rti_configure()
1539 for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) { in __hal_device_rts_port_configure()
1643 for (j = 0; j < XGE_HAL_MAX_RING_NUM; j++) { in __hal_device_rts_qos_configure()
1834 int rings[XGE_HAL_MAX_RING_NUM]={0}; in __hal_device_rth_it_configure()
1857 for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) { in __hal_device_rth_it_configure()
3434 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) in __hal_update_rxufca()
3444 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) in __hal_update_rxufca()
3651 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_device_handle_txpic()
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H A Dxgehal-channel.c111 post_qid + 1 <= XGE_HAL_MAX_RING_NUM); in __hal_channel_allocate()
H A Dxgehal-config.c433 for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in __hal_ring_config_check()
H A Dxgehal-mgmtaux.c1610 for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) in xge_hal_aux_device_config_read()
1776 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) { in xge_hal_aux_device_config_read()
/titanic_41/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-device.h364 xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM];
373 xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM];
378 int irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
379 int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
380 int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
H A Dxgehal-config.h466 #define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) macro
467 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM];
/titanic_41/usr/src/uts/common/io/xge/drv/
H A Dxge.c650 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { in xge_configuration_init()
1196 for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) in xge_attach()