| /titanic_41/usr/src/uts/common/io/mr_sas/ |
| H A D | fusion.h | 21 #define U64 uint64_t macro
110 U64 Address;
124 U64 Address64;
147 U64 Address64;
161 U64 Address;
350 U64 Words;
379 U64 SystemRequestFrameBaseAddress; /* 0x28 */
380 U64 ReplyDescriptorPostQueueAddress; /* 0x30 */
381 U64 ReplyFreeQueueAddress; /* 0x38 */
382 U64 TimeStamp; /* 0x40 */
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| H A D | ld_pd_map.c | 42 typedef U64 REGION_KEY;
147 MR_GetSpanBlock(U32 ld, U64 row, U64 *span_blk, MR_FW_RAID_MAP_ALL *map, in MR_GetSpanBlock()
165 U64 blk; in MR_GetSpanBlock()
199 MR_GetPhyParams(struct mrsas_instance *instance, U32 ld, U64 stripRow, in MR_GetPhyParams()
200 U16 stripRef, U64 *pdBlock, U16 *pDevHandle, in MR_GetPhyParams()
206 U64 row; in MR_GetPhyParams()
295 U64 endLba, endStrip, endRow; in MR_BuildRaidContext()
296 U64 start_row, start_strip; in MR_BuildRaidContext()
303 U64 ldStartBlock; in MR_BuildRaidContext()
495 megasas_get_best_arm(PLD_LOAD_BALANCE_INFO lbInfo, U8 arm, U64 block, in megasas_get_best_arm()
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| H A D | ld_pd_map.h | 47 U64 word;
60 U64 last_accessed_block[2];
80 U64 regLockRowLBA; /* 0x08 - 0x0F */
220 U64 Words;
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| H A D | mr_sas_tbolt.c | 67 U64 start_blk, U32 num_blocks);
1377 (U64)cmd->sgl_phys_addr); in mr_sas_tbolt_build_sgl()
2285 (U64)cmd->frame_phys_addr); in mr_sas_tbolt_build_mfi_cmd()
2987 mrsas_tbolt_set_pd_lba(U8 cdb[], uint8_t *cdb_len_ptr, U64 start_blk, in mrsas_tbolt_set_pd_lba()
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| H A D | mr_sas.c | 4892 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */ in mrsas_dma_alloc()
4894 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */ in mrsas_dma_alloc()
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| /titanic_41/usr/src/uts/common/io/ntxn/ |
| H A D | nxhal_nic_interface.h | 255 U64 data;
336 U64 host_phys_addr; /* Ring base addr */
342 U64 host_rsp_dma_addr; /* Response dma'd here */
343 U64 cmd_cons_dma_addr; /* */
344 U64 dummy_dma_addr; /* */
419 U64 host_phys_addr; /* Ring base addr */
426 U64 host_phys_addr; /* Ring base addr */
427 U64 buff_size; /* Packet buffer size */
433 U64 host_rsp_dma_addr; /* Response dma'd here */
538 U64 host_stat_buffer; /* Where to dma stats */
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| H A D | nic_cmn.h | 204 #ifndef U64
205 typedef unsigned long long U64; typedef
318 U64 HashMethod:32,
324 U64 Unused1;
325 U64 Unused2;
587 U64 Key1[124];
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| H A D | unm_nic_ctx.c | 586 adapter->ctxDesc->CmdRingAddrHi = ((U64)hw->cmdDesc_physAddr >> 32); in netxen_init_old_ctx()
598 ((U64)rcv_desc->phys_addr>>32); in netxen_init_old_ctx()
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| H A D | unm_gem.c | 229 offsetof(unm_user_info_t, mac_addr), FLASH_NUM_PORTS * sizeof (U64), in get_flash_mac_addr()
236 FLASH_NUM_PORTS * sizeof (U64), pmac) == -1) in get_flash_mac_addr()
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| H A D | unm_inc.h | 55 typedef unsigned long long U64; typedef
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| /titanic_41/usr/src/uts/common/io/bnxe/577xx/include/ |
| H A D | bcmtype.h | 122 typedef u64_t U64; typedef
173 typedef unsigned __int64 U64; typedef
183 typedef U64 int_ptr_t;
191 typedef unsigned long long U64; typedef
201 typedef unsigned __int64 U64; typedef
212 typedef unsigned char U64[8]; typedef
228 typedef U64 u64_t;
239 typedef U64 u64;
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| /titanic_41/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/ |
| H A D | mpi2_cnfg.h | 662 U64 WWID; /* 0x00 */
663 U64 DeviceName; /* 0x08 */
817 U64 UniqueValue; /* 0x04 */
895 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
896 U64 RaidAcceleratorBufferSize; /* 0x0C */
897 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
929 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
1401 U64 SASAddress; /* 0x00 */
1410 U64 EnclosureLogicalID; /* 0x00 */
1422 U64 DeviceName; /* 0x00 */
[all …]
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| H A D | mpi2_type.h | 106 } U64; typedef
122 typedef U64 *PU64;
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| H A D | mpi2.h | 447 U64 Words;
569 U64 Words;
827 U64 Address;
837 U64 Address64;
861 U64 Address;
873 U64 Address64;
1087 U64 Address;
1123 U64 Address;
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| H A D | mpi2_raid.h | 256 U64 VolumeMaxLBA; /* 0x10 */
315 U64 TotalBlocks; /* 0x00 */
316 U64 BlocksRemaining; /* 0x08 */
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| H A D | mpi2_ioc.h | 206 U64 SystemRequestFrameBaseAddress; /* 0x28 */
207 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
208 U64 ReplyFreeQueueAddress; /* 0x38 */
209 U64 TimeStamp; /* 0x40 */
242 U64 RDPQBaseAddress; /* 0x00 */
567 U64 TimeStamp; /* 0x00 */
688 U64 SASAddress; /* 0x0C */
924 U64 SASAddress; /* 0x04 */
941 U64 SASAddress; /* 0x04 */
1027 U64 EnclosureLogicalID; /* 0x04 */
[all …]
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| H A D | mpi2_sas.h | 144 U64 SASAddress; /* 0x10 */
281 U64 LookupAddress; /* 0x18 */
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| H A D | mpi2_ra.h | 81 U64 RaidAcceleratorControlBlockAddress; /* 0x0C */
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| H A D | mpi2_hbd.h | 78 U64 SASAddress; /* 0x10 */
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| H A D | mpi2_tool.h | 450 U64 BufferAddress; /* 0x0C */
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| /titanic_41/usr/src/uts/common/sys/ |
| H A D | mdesc.h | 51 #define U64(_s) _s macro
56 #define U64(_s) ((uint64_t)(_s))
76 #define MDE_ILLEGAL_IDX U64(-1)
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| /titanic_41/usr/src/grub/grub-0.97/stage2/ |
| H A D | zfs_lz4.c | 119 #define U64 uint64_t macro
128 U64 v;
153 #define UARCH U64
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| /titanic_41/usr/src/uts/common/fs/zfs/ |
| H A D | lz4.c | 294 #define U64 unsigned __int64 macro
300 #define U64 uint64_t macro
314 U64 v;
361 #define UARCH U64
409 LZ4_NbCommonBytes(register U64 val) in LZ4_NbCommonBytes()
451 return DeBruijnBytePos[((U64) ((val & -val) * 0x0218A392CDABBD3F)) >> in LZ4_NbCommonBytes()
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