1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 #ifndef AMD8111S_MAIN_H 7 #define AMD8111S_MAIN_H 8 9 /* 10 * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * + Redistributions of source code must retain the above copyright notice, 16 * + this list of conditions and the following disclaimer. 17 * 18 * + Redistributions in binary form must reproduce the above copyright 19 * + notice, this list of conditions and the following disclaimer in the 20 * + documentation and/or other materials provided with the distribution. 21 * 22 * + Neither the name of Advanced Micro Devices, Inc. nor the names of its 23 * + contributors may be used to endorse or promote products derived from 24 * + this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 37 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 38 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Import/Export/Re-Export/Use/Release/Transfer Restrictions and 41 * Compliance with Applicable Laws. Notice is hereby given that 42 * the software may be subject to restrictions on use, release, 43 * transfer, importation, exportation and/or re-exportation under 44 * the laws and regulations of the United States or other 45 * countries ("Applicable Laws"), which include but are not 46 * limited to U.S. export control laws such as the Export 47 * Administration Regulations and national security controls as 48 * defined thereunder, as well as State Department controls under 49 * the U.S. Munitions List. Permission to use and/or 50 * redistribute the software is conditioned upon compliance with 51 * all Applicable Laws, including U.S. export control laws 52 * regarding specifically designated persons, countries and 53 * nationals of countries subject to national security controls. 54 */ 55 56 #include <sys/types.h> 57 #include <sys/errno.h> 58 #include <sys/kmem.h> 59 #include <sys/conf.h> 60 #include <sys/stat.h> 61 #include <sys/note.h> 62 #include <sys/modctl.h> 63 64 #include <sys/stream.h> 65 #include <sys/strsubr.h> 66 #include <sys/strsun.h> 67 68 #include <sys/dditypes.h> 69 #include <sys/ddi.h> 70 #include <sys/sunddi.h> 71 72 #include <sys/pci.h> 73 74 #include <sys/ethernet.h> 75 #include <sys/dlpi.h> 76 #include <sys/mac_provider.h> 77 #include <sys/mac_ether.h> 78 #include <sys/netlb.h> 79 #include "amd8111s_hw.h" 80 81 #define MEM_REQ_MAX 100 82 #define MEMSET 4 83 84 #define IOC_LINESIZE 40 85 86 /* 87 * Loopback definitions 88 */ 89 #define AMD8111S_LB_NONE 0 90 #define AMD8111S_LB_EXTERNAL_1000 1 91 #define AMD8111S_LB_EXTERNAL_100 2 92 #define AMD8111S_LB_EXTERNAL_10 3 93 #define AMD8111S_LB_INTERNAL_PHY 4 94 #define AMD8111S_LB_INTERNAL_MAC 5 95 96 /* ((2 ^ (32 - 1)) * 8) / (10 ^ 8) >= 100 */ 97 #define AMD8111S_DUMP_MIB_SECONDS_THRESHOLD 100 98 #define AMD8111S_DUMP_MIB_BYTES_THRESHOLD 0x80000000 99 100 /* Bit flags for 'attach_progress' */ 101 #define AMD8111S_ATTACH_PCI 0x0001 /* pci_config_setup() */ 102 #define AMD8111S_ATTACH_RESOURCE 0x0002 /* odlInit() */ 103 #define AMD8111S_ATTACH_REGS 0x0004 /* ddi_regs_map_setup() */ 104 #define AMD8111S_ATTACH_INTRADDED 0x0010 /* intr_add() */ 105 #define AMD8111S_ATTACH_MACREGED 0x0020 /* mac_register() */ 106 #define AMD8111S_ATTACH_RESCHED 0x0040 /* soft_intr() */ 107 108 #define AMD8111S_TRY_SEND 0x0001 109 #define AMD8111S_SEND_READY 0x0002 110 111 #define NEXT(buf, ptr) \ 112 (buf.ptr + 1 >= buf.msg_buf + \ 113 buf.ring_size ? \ 114 buf.msg_buf : \ 115 buf.ptr + 1) 116 /* 117 * (Internal) return values from ioctl subroutines 118 */ 119 enum ioc_reply { 120 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 121 IOC_DONE, /* OK, reply sent */ 122 IOC_ACK, /* OK, just send ACK */ 123 IOC_REPLY, /* OK, just send reply */ 124 IOC_RESTART_ACK, /* OK, restart & ACK */ 125 IOC_RESTART_REPLY /* OK, restart & reply */ 126 }; 127 128 typedef int (*TIMERfUNC) (struct LayerPointers *); 129 130 struct TimerStructure { 131 int Type; 132 int Period; /* in milliseconds */ 133 timeout_id_t TimerHandle; 134 int (*TimerFunptr)(struct LayerPointers *); 135 struct LayerPointers *pLayerPointers; 136 }; 137 138 struct amd8111s_statistics 139 { 140 uint64_t intr_TINT0; /* # of TINT0 (Tx interrupts) */ 141 uint64_t intr_RINT0; /* # of RINT0 (Rx interrupts) */ 142 uint64_t intr_STINT; /* # of STINT (Software Timer Intr) */ 143 uint64_t intr_OTHER; /* Intr caused by other device */ 144 145 uint64_t tx_ok_packets; 146 uint64_t tx_no_descriptor; 147 uint64_t tx_no_buffer; 148 uint64_t tx_rescheduled; 149 uint64_t tx_unrescheduled; 150 151 /* # of call amd8111s_dump_mib function */ 152 uint64_t mib_dump_counter; 153 154 /* 155 * From MIB registers (TX) 156 */ 157 uint64_t tx_mib_packets; /* # of packets */ 158 uint64_t tx_mib_multicst_packets; /* # of multicast packets */ 159 uint64_t tx_mib_broadcst_packets; /* # of broadcast packets */ 160 uint64_t tx_mib_flowctrl_packets; /* # of flow ctrl packets */ 161 162 uint64_t tx_mib_bytes; /* # of all Tx bytes */ 163 164 /* Packet drop due to Tx FIFO underrun */ 165 uint64_t tx_mib_underrun_packets; 166 uint64_t tx_mib_collision_packets; 167 /* Packets successfully transmitted after experiencing one collision */ 168 uint64_t tx_mib_one_coll_packets; 169 uint64_t tx_mib_multi_coll_packets; 170 /* # of late collisions that occur */ 171 uint64_t tx_mib_late_coll_packets; 172 uint64_t tx_mib_ex_coll_packets; /* excessive collision */ 173 uint64_t tx_mib_oversize_packets; 174 uint64_t tx_mib_defer_trans_packets; /* defer transmit */ 175 176 177 /* 178 * Some error counter after "ifconfig amd8111sX unplumb" 179 */ 180 /* 181 * Count Tx mp number from GLD even after NIC has been unplumbed. 182 * This value should always be 0. 183 */ 184 uint64_t tx_afterunplumb; 185 /* 186 * We drain all pending tx packets during unplumb operation. This 187 * variable is to count the drain time. 188 * 30 means success; =30 means fail 189 */ 190 uint64_t tx_draintime; 191 192 uint64_t rx_ok_packets; /* # of all good packets */ 193 uint64_t rx_allocfail; /* alloc memory fail during Rx */ 194 uint64_t rx_error_zerosize; 195 196 uint64_t rx_0_packets; 197 uint64_t rx_1_15_packets; 198 uint64_t rx_16_31_packets; 199 uint64_t rx_32_47_packets; 200 uint64_t rx_48_63_packets; 201 uint64_t rx_double_overflow; 202 203 uint64_t rx_desc_err; 204 uint64_t rx_desc_err_FRAM; /* Framing error */ 205 uint64_t rx_desc_err_OFLO; /* Overflow error */ 206 uint64_t rx_desc_err_CRC; /* CRC error */ 207 uint64_t rx_desc_err_BUFF; /* BCRC error */ 208 209 /* 210 * From MIB registers (RX) 211 */ 212 uint64_t rx_mib_unicst_packets; /* # of unicast packets */ 213 uint64_t rx_mib_multicst_packets; /* # of multicast packets */ 214 uint64_t rx_mib_broadcst_packets; /* # of broadcast packets */ 215 uint64_t rx_mib_macctrl_packets; /* # of mac ctrl packets */ 216 uint64_t rx_mib_flowctrl_packets; /* # of flow ctrl packets */ 217 218 uint64_t rx_mib_bytes; /* # of all Rx bytes */ 219 uint64_t rx_mib_good_bytes; /* # of all Rx bytes */ 220 /* 221 * The total number of valid frames received that are less than 64 222 * bytes long (include the FCS). 223 */ 224 uint64_t rx_mib_undersize_packets; 225 /* 226 * The total number of valid frames received that are greater than the 227 * maximum valid frame size (include the FCS). 228 */ 229 uint64_t rx_mib_oversize_packets; 230 231 uint64_t rx_mib_align_err_packets; 232 uint64_t rx_mib_fcs_err_packets; /* has a bad FCS */ 233 /* Invalid data symbol (RX_ER) */ 234 uint64_t rx_mib_symbol_err_packets; 235 /* Packets that were dropped because no descriptor was available */ 236 uint64_t rx_mib_drop_packets; 237 /* 238 * Packets that were dropped due to lack of resources. This includes 239 * the number of times a packet was dropped due to receive FIFO 240 * overflow and lack of receive descriptor. 241 */ 242 uint64_t rx_mib_miss_packets; 243 }; 244 245 struct amd8111s_msgbuf { 246 uint64_t phy_addr; 247 caddr_t vir_addr; 248 uint32_t msg_size; 249 ddi_dma_handle_t p_hdl; 250 uint32_t offset; 251 }; 252 253 struct amd8111s_dma_ringbuf { 254 ddi_dma_handle_t *dma_hdl; 255 ddi_acc_handle_t *acc_hdl; 256 ddi_dma_cookie_t *dma_cookie; 257 caddr_t *trunk_addr; 258 uint32_t buf_sz; 259 uint32_t trunk_sz; 260 uint32_t trunk_num; 261 struct amd8111s_msgbuf *msg_buf; 262 uint32_t ring_size; 263 uint32_t dma_buf_sz; 264 struct amd8111s_msgbuf *free; 265 struct amd8111s_msgbuf *next; 266 struct amd8111s_msgbuf *curr; 267 268 kmutex_t ring_lock; 269 }; 270 271 struct odl { 272 dev_info_t *devinfo; 273 274 mac_handle_t mh; /* mac module handle */ 275 276 struct amd8111s_statistics statistics; 277 278 /* Locks */ 279 kmutex_t mdlSendLock; 280 kmutex_t mdlRcvLock; 281 kmutex_t timer_lock; 282 kmutex_t send_cv_lock; 283 kcondvar_t send_cv; 284 285 ddi_softintr_t drain_id; 286 /* 287 * The chip_lock assures that the Rx/Tx process must be stopped while 288 * other functions change the hardware configuration, such as attach() 289 * detach() etc are executed. 290 */ 291 krwlock_t chip_lock; 292 293 /* 294 * HW operators and parameters on attach period 295 */ 296 ddi_iblock_cookie_t iblock; /* HW: interrupt block cookie */ 297 ddi_acc_handle_t MemBasehandle; 298 299 /* For pci configuration */ 300 ddi_acc_handle_t pci_handle; /* HW: access handle of PCI space */ 301 uint16_t vendor_id; 302 uint16_t device_id; 303 304 /* 305 * FreeQ: Transfer Rx Buffer parameters from top layer to low layers. 306 * Format of parameter: 307 * (struct RxBufInfo *, physical address) 308 */ 309 unsigned long FreeQ[2 * RX_RING_SIZE]; 310 unsigned long *FreeQStart; 311 unsigned long *FreeQEnd; 312 long *FreeQWrite; 313 long *FreeQRead; 314 315 /* For Rx descriptors */ 316 ddi_dma_handle_t rx_desc_dma_handle; 317 ddi_acc_handle_t rx_desc_acc_handle; 318 ddi_dma_cookie_t rx_desc_dma_cookie; 319 320 /* For Tx descriptors */ 321 ddi_dma_handle_t tx_desc_dma_handle; 322 ddi_acc_handle_t tx_desc_acc_handle; 323 ddi_dma_cookie_t tx_desc_dma_cookie; 324 325 /* For Tx buffers */ 326 struct amd8111s_dma_ringbuf tx_buf; 327 328 /* For Rx buffers */ 329 struct amd8111s_dma_ringbuf rx_buf; 330 331 ether_addr_t MacAddress; /* Mac address */ 332 333 /* Multicast addresses table */ 334 UCHAR MulticastAddresses 335 [MAX_MULTICAST_ADDRESSES][ETH_LENGTH_OF_ADDRESS]; 336 337 link_state_t LinkStatus; 338 339 /* Timer */ 340 timeout_id_t Timer_id; 341 int (*TimerFunc)(struct LayerPointers *); 342 int timer_run; 343 int timer_linkdown; 344 345 unsigned int dump_mib_seconds; 346 347 uint32_t loopback_mode; 348 unsigned int rx_fcs_stripped; 349 350 unsigned int rx_overflow_counter; 351 unsigned int pause_interval; 352 353 }; 354 355 #endif /* AMD8111S_MAIN_H */ 356