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Searched refs:TXDMA_REG_READ64 (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/common/io/hxge/
H A Dhpi_txdma.c105 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
112 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
129 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
136 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
151 TXDMA_REG_READ64(handle, TDC_STAT, channel, &cs.value); in hpi_txdma_channel_control()
181 TXDMA_REG_READ64(handle, TDC_STAT, channel, &cs_p->value); in hpi_txdma_control_status()
189 TXDMA_REG_READ64(handle, TDC_STAT, channel, &txcs.value); in hpi_txdma_control_status()
219 TXDMA_REG_READ64(handle, TDC_INT_MASK, channel, &mask_p->value); in hpi_txdma_event_mask()
227 TXDMA_REG_READ64(handle, TDC_INT_MASK, channel, &mask.value); in hpi_txdma_event_mask()
256 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, reg_data); in hpi_txdma_ring_config()
[all …]
H A Dhpi_txdma.h53 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ macro
H A Dhxge_txdma.c655 TXDMA_REG_READ64(handle, TDC_BYTE_CNT, tdc, &byte_cnt.value); in hxge_txdma_reclaim()
668 TXDMA_REG_READ64(handle, TDC_TDR_HEAD, tdc, &tx_head.value); in hxge_txdma_reclaim()
680 TXDMA_REG_READ64(handle, TDC_TDR_QLEN, tdc, &qlen.value); in hxge_txdma_reclaim()
2532 TXDMA_REG_READ64(handle, TDC_DROP_CNT, channel, &drop_cnt.value); in hxge_tx_err_evnts()
2589 TXDMA_REG_READ64(hxgep->hpi_handle, TDC_PREF_PAR_LOG, in hxge_tx_err_evnts()
/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_tx_rd64.h37 static void TXDMA_REG_READ64(npi_handle_t, uint64_t, int, uint64_t *);
38 #pragma inline(TXDMA_REG_READ64)
122 TXDMA_REG_READ64( in TXDMA_REG_READ64() function
H A Dnpi_txdma.c151 TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value); in npi_txdma_dump_tdc_regs()
937 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); in npi_txdma_channel_control()
959 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); in npi_txdma_channel_control()
966 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); in npi_txdma_channel_control()
979 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); in npi_txdma_channel_control()
986 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); in npi_txdma_channel_control()
996 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); in npi_txdma_channel_control()
1053 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs_p->value); in npi_txdma_control_status()
1061 TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value); in npi_txdma_control_status()
1118 TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, in npi_txdma_event_mask()
[all …]
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_txdma.c960 TXDMA_REG_READ64(handle, TX_RING_HDL_REG, tdc, &tx_head.value); in nxge_txdma_reclaim()
3656 TXDMA_REG_READ64(nxgep->npi_handle, TDMC_INTR_DBG_REG, in nxge_txdma_inject_err()