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Searched refs:TXC_FZC_CNTL_REG_WRITE64 (Results 1 – 3 of 3) sorted by relevance

/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txc.c613 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port, in npi_txc_port_dma_enable()
664 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port, in npi_txc_port_dma_channel_enable()
702 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port, in npi_txc_port_dma_channel_disable()
893 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port, in npi_txc_ro_states_get()
913 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_RO_CTL_REG, port, ctl.value); in npi_txc_ro_states_get()
923 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port, 0); in npi_txc_ro_ecc_state_clr()
976 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port, in npi_txc_sf_states_get()
995 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port, 0); in npi_txc_sf_ecc_state_clr()
H A Dnpi_txc.h79 #define TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data) \ macro
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_txc.c450 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_CTL_REG, in nxge_txc_handle_port_errors()
484 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_CTL_REG, portn, 0); in nxge_txc_handle_port_errors()
547 TXC_FZC_CNTL_REG_WRITE64(nxgep->npi_handle, TXC_ROECC_CTL_REG, in nxge_txc_inject_err()
566 TXC_FZC_CNTL_REG_WRITE64(nxgep->npi_handle, TXC_SFECC_CTL_REG, in nxge_txc_inject_err()