xref: /titanic_41/usr/src/uts/common/io/hxge/hxge_tdc_hw.h (revision fe930412c257f961ae67039de3b164b83717976a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_HXGE_TDC_HW_H
27 #define	_HXGE_TDC_HW_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #define	TDC_BASE_ADDR				0X00400000
36 
37 #define	TDC_PAGE_HANDLE				(TDC_BASE_ADDR + 0x8)
38 #define	TDC_TDR_CFG				(TDC_BASE_ADDR + 0x20)
39 #define	TDC_TDR_HEAD				(TDC_BASE_ADDR + 0x28)
40 #define	TDC_TDR_PRE_HEAD			(TDC_BASE_ADDR + 0x30)
41 #define	TDC_TDR_KICK				(TDC_BASE_ADDR + 0x38)
42 #define	TDC_INT_MASK				(TDC_BASE_ADDR + 0x40)
43 #define	TDC_STAT				(TDC_BASE_ADDR + 0x48)
44 #define	TDC_MBH					(TDC_BASE_ADDR + 0x50)
45 #define	TDC_MBL					(TDC_BASE_ADDR + 0x58)
46 #define	TDC_BYTE_CNT				(TDC_BASE_ADDR + 0x80)
47 #define	TDC_TDR_QLEN				(TDC_BASE_ADDR + 0x88)
48 #define	TDC_RTAB_PTR				(TDC_BASE_ADDR + 0x90)
49 #define	TDC_DROP_CNT				(TDC_BASE_ADDR + 0x98)
50 #define	TDC_LAST_PKT_RBUF_PTRS			(TDC_BASE_ADDR + 0xA8)
51 #define	TDC_PREF_CMD				(TDC_BASE_ADDR + 0x100)
52 #define	TDC_PREF_DATA				(TDC_BASE_ADDR + 0x108)
53 #define	TDC_PREF_PAR_DATA			(TDC_BASE_ADDR + 0x110)
54 #define	TDC_REORD_BUF_CMD			(TDC_BASE_ADDR + 0x120)
55 #define	TDC_REORD_BUF_DATA			(TDC_BASE_ADDR + 0x128)
56 #define	TDC_REORD_BUF_ECC_DATA			(TDC_BASE_ADDR + 0x130)
57 #define	TDC_REORD_TBL_CMD			(TDC_BASE_ADDR + 0x140)
58 #define	TDC_REORD_TBL_DATA_LO			(TDC_BASE_ADDR + 0x148)
59 #define	TDC_REORD_TBL_DATA_HI			(TDC_BASE_ADDR + 0x150)
60 #define	TDC_PREF_PAR_LOG			(TDC_BASE_ADDR + 0x200)
61 #define	TDC_REORD_BUF_ECC_LOG			(TDC_BASE_ADDR + 0x208)
62 #define	TDC_REORD_TBL_PAR_LOG			(TDC_BASE_ADDR + 0x210)
63 #define	TDC_FIFO_ERR_MASK			(TDC_BASE_ADDR + 0x220)
64 #define	TDC_FIFO_ERR_STAT			(TDC_BASE_ADDR + 0x228)
65 #define	TDC_FIFO_ERR_INT_DBG			(TDC_BASE_ADDR + 0x230)
66 #define	TDC_STAT_INT_DBG			(TDC_BASE_ADDR + 0x240)
67 #define	TDC_PKT_REQ_TID_TAG			(TDC_BASE_ADDR + 0x250)
68 #define	TDC_SOP_PREF_DESC_LOG			(TDC_BASE_ADDR + 0x260)
69 #define	TDC_PREF_DESC_LOG			(TDC_BASE_ADDR + 0x268)
70 #define	TDC_PEU_TXN_LOG				(TDC_BASE_ADDR + 0x270)
71 #define	TDC_DBG_TRAINING_VEC			(TDC_BASE_ADDR + 0x300)
72 #define	TDC_DBG_GRP_SEL				(TDC_BASE_ADDR + 0x308)
73 
74 
75 /*
76  * Register: TdcPageHandle
77  * Logical Page Handle
78  * Description: Upper 20 bits [63:44] to use for all accesses over
79  * the PCI-E bus. Fields in this register are part of the dma
80  * configuration and cannot be changed once the dma is enabled.
81  * Fields:
82  *     Page handle, bits [63:44] of all PCI-E transactions for this
83  *     channel.
84  */
85 typedef union {
86 	uint64_t value;
87 	struct {
88 #if defined(_BIG_ENDIAN)
89 		uint32_t	rsrvd:32;
90 		uint32_t	rsrvd_l:12;
91 		uint32_t	page_handle:20;
92 #else
93 		uint32_t	page_handle:20;
94 		uint32_t	rsrvd_l:12;
95 		uint32_t	rsrvd:32;
96 #endif
97 	} bits;
98 } tdc_page_handle_t;
99 
100 
101 /*
102  * Register: TdcTdrCfg
103  * Transmit Ring Configuration
104  * Description: Configuration parameters for transmit DMA block.
105  * Software configures the location of the transmit ring in host
106  * memory, as well as its maximum size. Fields in this register are
107  * part of the dma configuration and cannot be changed once the dma
108  * is enabled.
109  * HW does not check for all configuration errors across different
110  * fields.
111  * The usage of enable, reset, and qst is as follows. Software
112  * should use the following sequence to reset a DMA channel. First,
113  * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to
114  * 1. After DMA.reset is cleared by hardware and the DMA.qst is set
115  * to 1, software may then start configuring the DMA channel. The
116  * DMA.enable can be set or cleared while the DMA is in operation.
117  * The state machines of the DMA may not have returned to its initial
118  * states yet after the DMA.enable bit is cleared. This condition is
119  * indicated by the value of the DMA.qst. An example of DMA.enable
120  * being cleared during operation is when a fatal error occurs.
121  * Fields:
122  *     Bits [15:5] of the maximum number of entries in the Transmit
123  *     Queue ring buffer. Bits [4:0] are always 0. Maximum number of
124  *     entries is (2^16 - 32) and is limited by the staddr value.
125  *     (len + staddr) should not exceed (2^16 - 32).
126  *     Set to 1 to enable the Transmit DMA. On fatal errors, this bit
127  *     will be cleared by hardware. This bit cannot be set if sw has
128  *     not resolved any pending fatal error condition: i.e. any
129  *     TdcStat ldf1 error bits remain set.
130  *     Set to 1 to reset the DMA. Hardware will clear this bit after
131  *     reset is completed. A reset will bring the sepecific DMA back
132  *     to the power on state (including the DMA.en in this register).
133  *     When set to 1, it indicates all state associated with the DMA
134  *     are in its initial state following either dma reset or
135  *     disable. Thus, once this is set to 1, sw could start to
136  *     configure the DMA if needed. In an extreme case such as if a
137  *     parity error on an EOP descriptor prevents recognition of the
138  *     EOP, it is possible that the qst bit will not be set even
139  *     though the dma engine has been disabled.
140  *     Address bits [43:19] of the start address for the transmit
141  *     ring buffer. The value in this field is dependent on len
142  *     field. (len + staddr) should not exceed (2^16 - 32).
143  *     Bits [18:6] of the start address for the transmit ring buffer.
144  *     Bits [5:0] are assumed to be zero, or 64B aligned.
145  */
146 typedef union {
147 	uint64_t value;
148 	struct {
149 #if defined(_BIG_ENDIAN)
150 		uint32_t	len:11;
151 		uint32_t	rsrvd:5;
152 		uint32_t	enable:1;
153 		uint32_t	reset:1;
154 		uint32_t	qst:1;
155 		uint32_t	rsrvd1:1;
156 		uint32_t	staddr_base:12;
157 		uint32_t	staddr_base_l:13;
158 		uint32_t	staddr:13;
159 		uint32_t	rsrvd2:6;
160 #else
161 		uint32_t	rsrvd2:6;
162 		uint32_t	staddr:13;
163 		uint32_t	staddr_base_l:13;
164 		uint32_t	staddr_base:12;
165 		uint32_t	rsrvd1:1;
166 		uint32_t	qst:1;
167 		uint32_t	reset:1;
168 		uint32_t	enable:1;
169 		uint32_t	rsrvd:5;
170 		uint32_t	len:11;
171 #endif
172 	} bits;
173 } tdc_tdr_cfg_t;
174 
175 
176 /*
177  * Register: TdcTdrHead
178  * Transmit Ring Head
179  * Description: Read-only register software call poll to determine
180  * the current head of the transmit ring, from the tdcTxPkt block.
181  * Software uses this to know which Tdr entries have had their
182  * descriptors transmitted. These entries and their descriptors may
183  * then be reused by software.
184  * Fields:
185  *     Hardware will toggle this bit every time the head is wrapped
186  *     around the configured ring buffer.
187  *     Entry in transmit ring which will be the next descriptor
188  *     transmitted. Software should consider the Tdr full if head ==
189  *     TdcTdrKick::tail and wrap != TdcTdrKick::wrap. The ring is
190  *     empty of head == TdcTdrKick::tail and wrap ==
191  *     TdcTdrKick::wrap.
192  */
193 typedef union {
194 	uint64_t value;
195 	struct {
196 #if defined(_BIG_ENDIAN)
197 		uint32_t	rsrvd:32;
198 		uint32_t	rsrvd_l:15;
199 		uint32_t	wrap:1;
200 		uint32_t	head:16;
201 #else
202 		uint32_t	head:16;
203 		uint32_t	wrap:1;
204 		uint32_t	rsrvd_l:15;
205 		uint32_t	rsrvd:32;
206 #endif
207 	} bits;
208 } tdc_tdr_head_t;
209 
210 
211 /*
212  * Register: TdcTdrPreHead
213  * Transmit Ring Prefetch Head
214  * Description: Read-only register software call poll to determine
215  * the current prefetch head of the transmit ring, from the tdcPktReq
216  * block. Transmit descriptors are prefetched into chip memory.
217  * Indicates next descriptor to be read from host memory. For debug
218  * use only.
219  * Fields:
220  *     Hardware will toggle this bit every time the prefetch head is
221  *     wrapped around the configured ring buffer.
222  *     Entry in transmit ring which will be fetched next from host
223  *     memory.
224  */
225 typedef union {
226 	uint64_t value;
227 	struct {
228 #if defined(_BIG_ENDIAN)
229 		uint32_t	rsrvd:32;
230 		uint32_t	rsrvd_l:15;
231 		uint32_t	wrap:1;
232 		uint32_t	head:16;
233 #else
234 		uint32_t	head:16;
235 		uint32_t	wrap:1;
236 		uint32_t	rsrvd_l:15;
237 		uint32_t	rsrvd:32;
238 #endif
239 	} bits;
240 } tdc_tdr_pre_head_t;
241 
242 
243 /*
244  * Register: TdcTdrKick
245  * Transmit Ring Kick
246  * Description: After posting transmit descriptors to the Transmit
247  * Ring, software updates the tail pointer to inform Hydra of the new
248  * descriptors. Software can only post descriptors through this
249  * register when the entire packet is in the ring. Otherwise,
250  * hardware dead-lock can occur. If an overflow kick occurs when the
251  * channel is disabled, tdcStat.txRngOflow (Transmit Ring Overflow)
252  * status is not set.
253  * Fields:
254  *     Software needs to toggle this bit every time the tail is
255  *     wrapped around the configured ring buffer.
256  *     Entry where the next valid descriptor will be added (one entry
257  *     past the last valid descriptor.)
258  */
259 typedef union {
260 	uint64_t value;
261 	struct {
262 #if defined(_BIG_ENDIAN)
263 		uint32_t	rsrvd:32;
264 		uint32_t	rsrvd_l:15;
265 		uint32_t	wrap:1;
266 		uint32_t	tail:16;
267 #else
268 		uint32_t	tail:16;
269 		uint32_t	wrap:1;
270 		uint32_t	rsrvd_l:15;
271 		uint32_t	rsrvd:32;
272 #endif
273 	} bits;
274 } tdc_tdr_kick_t;
275 
276 
277 /*
278  * Register: TdcIntMask
279  * Transmit Event Mask
280  * Description: The Tx DMA can generate a number of LDF events. The
281  * events can be enabled by software by setting the corresponding bit
282  * to 0. The default value of 1 means the event is masked and no LDF
283  * event is generated.
284  * Fields:
285  *     Set to 0 to select the event to raise the LDF for packets
286  *     marked. An LDF 0 event.
287  *     Set to 0 to select the event to raise the LDF when poisoned
288  *     completion or non-zero (unsuccessful) completion status
289  *     received from PEU. An LDF 1 event.
290  *     Set to 0 to select the event to raise the LDF when total bytes
291  *     transmitted compared against pkt internal header bytes
292  *     transmitted mismatch. An LDF 1 event.
293  *     Set to 0 to select the event to raise the LDF when a runt
294  *     packet is dropped (when VMAC does not allow runt packets to be
295  *     padded). An LDF 1 event.
296  *     Set to 0 to select the event to raise the LDF when the packet
297  *     size exceeds hardware limit. An LDF 1 event.
298  *     Set to 0 to select the event to raise the LDF to indicate
299  *     Transmit Ring Overflow An LDF 1 event.
300  *     Set to 0 to select the event to raise the LDF to indicate
301  *     parity error on the tdr prefetch buffer occurred. An LDF 1
302  *     event.
303  *     Set to 0 to select the event to raise the LDF to indicate tdc
304  *     received a response completion timeout from peu for tdr
305  *     descriptor prefetch An LDF 1 event.
306  *     Set to 0 to select the event to raise the LDF to indicate tdc
307  *     received a response completion timeout from peu for packet
308  *     data request An LDF 1 event.
309  *     Set to 0 to select the event to raise the LDF to indicate tdc
310  *     did not receive an SOP in the 1st descriptor as was expected
311  *     or the numPtr in the 1st descriptor was set to 0. An LDF 1
312  *     event.
313  *     Set to 0 to select the event to raise the LDF to indicate tdc
314  *     received an unexpected SOP descriptor error. An LDF 1 event.
315  */
316 typedef union {
317 	uint64_t value;
318 	struct {
319 #if defined(_BIG_ENDIAN)
320 		uint32_t	rsrvd:32;
321 		uint32_t	rsrvd_l:16;
322 		uint32_t	marked:1;
323 		uint32_t	rsrvd1:5;
324 		uint32_t	peu_resp_err:1;
325 		uint32_t	pkt_size_hdr_err:1;
326 		uint32_t	runt_pkt_drop_err:1;
327 		uint32_t	pkt_size_err:1;
328 		uint32_t	tx_rng_oflow:1;
329 		uint32_t	pref_par_err:1;
330 		uint32_t	tdr_pref_cpl_to:1;
331 		uint32_t	pkt_cpl_to:1;
332 		uint32_t	invalid_sop:1;
333 		uint32_t	unexpected_sop:1;
334 #else
335 		uint32_t	unexpected_sop:1;
336 		uint32_t	invalid_sop:1;
337 		uint32_t	pkt_cpl_to:1;
338 		uint32_t	tdr_pref_cpl_to:1;
339 		uint32_t	pref_par_err:1;
340 		uint32_t	tx_rng_oflow:1;
341 		uint32_t	pkt_size_err:1;
342 		uint32_t	runt_pkt_drop_err:1;
343 		uint32_t	pkt_size_hdr_err:1;
344 		uint32_t	peu_resp_err:1;
345 		uint32_t	rsrvd1:5;
346 		uint32_t	marked:1;
347 		uint32_t	rsrvd_l:16;
348 		uint32_t	rsrvd:32;
349 #endif
350 	} bits;
351 } tdc_int_mask_t;
352 
353 
354 /*
355  * Register: TdcStat
356  * Transmit Control and Status
357  * Description: Combined control and status register. When writing to
358  * this register, any bit that software wishes not to change should
359  * be written to 0. The TdcStat register may be read or written only
360  * when no mailbox updates are pending. Accordingly, the expected
361  * algorithm for software to use in tracking marked packets and
362  * mailbox updates is one of the following only: 1) enable
363  * interrupts, enable mb, send a single marked packet, wait for Ldf0,
364  * clear marked, repeat or 2) disable interrupts, never enable mb,
365  * send one or more marked packets, poll TdcStat for marked/mMarked
366  * state, clear marked/mMarked bits, repeat. If interrupts are
367  * enabled, upon receiving an Ldf1 interrupt for a given channel
368  * software must wait until a channel's Qst bit has asserted before
369  * reading TdcStat for corresponding error information and before
370  * writing to TdcStat to clear error state.
371  * Fields:
372  *     A wrap-around counter to keep track of packets transmitted.
373  *     Reset to zero when the DMA is reset
374  *     The pktCnt corresponds to the last packet with the MARK bit
375  *     set. Reset to zero when the DMA is reset.
376  *     Set to 1 to cause HW to update the mailbox when the next
377  *     packet with the marked bit set is transmitted. HW clears this
378  *     bit to zero after the mailbox update has completed. Note that,
379  *     correspondingly, the TdcStat data for the Tx mailbox write
380  *     will reflect the state of mb prior to the mb bit's update for
381  *     the marked packet being sent. Software should send only one
382  *     marked packet per assertion of the mb bit. Multiple marked
383  *     packets after setting the mb bit and before receiving the
384  *     corresponding mailbox update is not supported. Precautionary
385  *     note: Emphasize HW is responsible for clearing this bit. If
386  *     software clears this bit, the behavior is undefined.
387  *     Set to 1 when a packet with the mark bit set is transmitted.
388  *     If mb is set at the time of the marked packet transmission,
389  *     marked will not be set until the corresponding mailbox write
390  *     has completed. Note that, correspondingly, the TdcStat data
391  *     for the Tx mailbox write will reflect the state of marked
392  *     prior to the marked bit's update for the marked packet being
393  *     sent. Software may read the register to clear the bit.
394  *     Alternatively, software may write a 1 to clear the MARKED bit
395  *     (Write 0 has no effect). In the case of write 1, if mMarked
396  *     bit is set, MARKED bit will NOT be cleared. This bit is used
397  *     to generate LDF 0 consistent with settings in TdcIntMask.
398  *     Overflow bit for MARKED register bit. Indicates that multiple
399  *     marked packets have been transmitted since the last clear of
400  *     the marked bit. If hardware is waiting to update MARKED until
401  *     a mailbox write has completed, when another marked packet is
402  *     transmitted, mMarked will also not be set until the mailbox
403  *     write completes. Note that, correspondingly, the TdcStat data
404  *     for the Tx mailbox write will reflect the state of mMarked
405  *     prior to the mMarked bit's update for the marked packet being
406  *     sent. Software reads to clear. A write 1 to MARKED bit will
407  *     also clear the mMarked bit. A write 0 has no effect.
408  *     Set to 1 to indicate poisoned completion or non-zero
409  *     (unsuccessful) completion status received from PEU. Part of
410  *     LDF 1.
411  *     Set to 1 to indicate tdc descriptor error: total bytes
412  *     transmitted compared against pkt internal header bytes
413  *     transmitted mismatch. Fatal error. Part of LDF 1.
414  *     Set to 1 when a runt packet is dropped (when VMAC does not
415  *     allow runt packets to be padded. Fatal error. Part of LDF1.
416  *     Set to 1 when the packet size exceeds hardware limit: the sum
417  *     of gathers exceeds the maximum transmit length (specified in
418  *     the Tx VMAC Configuration register txMaxFrameLength) or any
419  *     descriptor attempts to transmit more than 4K. Writing a 1
420  *     clears the value to 0. Writing a 0 has no effect. Part of LDF
421  *     1. Note that packet size for the purpose of this error is
422  *     determined by the actual transfer size from the Tdc to the Tdp
423  *     and not from the totXferSize field of the internal header.
424  *     Set to 1 to indicate Transmit Ring Overflow: Tail > Ringlength
425  *     or if the relative position of the shadow tail to the ring
426  *     tail is not correct with respect to the wrap bit. Transmit
427  *     Ring Overflow status is not set, if the dma is disabled. Fatal
428  *     error. Part of LDF1.
429  *     Set to 1 by HW to indicate parity error on the tdr prefetch
430  *     buffer occurred. Writing a 1 clears the parity error log
431  *     register Part of LDF 1.
432  *     Set to 1 to indicate tdc received a response completion
433  *     timeout from peu for tdr descriptor prefetch Fatal error. Part
434  *     of LDF 1.
435  *     Set to 1 to indicate tdc received a response completion
436  *     timeout from peu for packet data request Fatal error. Part of
437  *     LDF 1.
438  *     Set to 1 to indicate tdc did not receive an SOP in the 1st
439  *     descriptor as was expected or the numPtr in the 1st descriptor
440  *     was set to 0. Fatal error. Part of LDF 1.
441  *     Set to 1 to indicate tdc received an unexpected SOP descriptor
442  *     error. Fatal error. Part of LDF 1.
443  */
444 typedef union {
445 	uint64_t value;
446 	struct {
447 #if defined(_BIG_ENDIAN)
448 		uint32_t	rsrvd:4;
449 		uint32_t	pkt_cnt:12;
450 		uint32_t	rsrvd1:4;
451 		uint32_t	lastmark:12;
452 		uint32_t	rsrvd2:2;
453 		uint32_t	mb:1;
454 		uint32_t	rsrvd3:13;
455 		uint32_t	marked:1;
456 		uint32_t	m_marked:1;
457 		uint32_t	rsrvd4:4;
458 		uint32_t	peu_resp_err:1;
459 		uint32_t	pkt_size_hdr_err:1;
460 		uint32_t	runt_pkt_drop_err:1;
461 		uint32_t	pkt_size_err:1;
462 		uint32_t	tx_rng_oflow:1;
463 		uint32_t	pref_par_err:1;
464 		uint32_t	tdr_pref_cpl_to:1;
465 		uint32_t	pkt_cpl_to:1;
466 		uint32_t	invalid_sop:1;
467 		uint32_t	unexpected_sop:1;
468 #else
469 		uint32_t	unexpected_sop:1;
470 		uint32_t	invalid_sop:1;
471 		uint32_t	pkt_cpl_to:1;
472 		uint32_t	tdr_pref_cpl_to:1;
473 		uint32_t	pref_par_err:1;
474 		uint32_t	tx_rng_oflow:1;
475 		uint32_t	pkt_size_err:1;
476 		uint32_t	runt_pkt_drop_err:1;
477 		uint32_t	pkt_size_hdr_err:1;
478 		uint32_t	peu_resp_err:1;
479 		uint32_t	rsrvd4:4;
480 		uint32_t	m_marked:1;
481 		uint32_t	marked:1;
482 		uint32_t	rsrvd3:13;
483 		uint32_t	mb:1;
484 		uint32_t	rsrvd2:2;
485 		uint32_t	lastmark:12;
486 		uint32_t	rsrvd1:4;
487 		uint32_t	pkt_cnt:12;
488 		uint32_t	rsrvd:4;
489 #endif
490 	} bits;
491 } tdc_stat_t;
492 
493 
494 /*
495  * Register: TdcMbh
496  * Tx DMA Mailbox High
497  * Description: Upper bits of Tx DMA mailbox address in host memory.
498  * Fields in this register are part of the dma configuration and
499  * cannot be changed once the dma is enabled.
500  * Fields:
501  *     Bits [43:32] of the Mailbox address.
502  */
503 typedef union {
504 	uint64_t value;
505 	struct {
506 #if defined(_BIG_ENDIAN)
507 		uint32_t	rsrvd:32;
508 		uint32_t	rsrvd_l:20;
509 		uint32_t	mbaddr:12;
510 #else
511 		uint32_t	mbaddr:12;
512 		uint32_t	rsrvd_l:20;
513 		uint32_t	rsrvd:32;
514 #endif
515 	} bits;
516 } tdc_mbh_t;
517 
518 
519 /*
520  * Register: TdcMbl
521  * Tx DMA Mailbox Low
522  * Description: Lower bits of Tx DMA mailbox address in host memory.
523  * Fields in this register are part of the dma configuration and
524  * cannot be changed once the dma is enabled.
525  * Fields:
526  *     Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to
527  *     be zero, or 64B aligned.
528  */
529 typedef union {
530 	uint64_t value;
531 	struct {
532 #if defined(_BIG_ENDIAN)
533 		uint32_t	rsrvd:32;
534 		uint32_t	mbaddr:26;
535 		uint32_t	rsrvd1:6;
536 #else
537 		uint32_t	rsrvd1:6;
538 		uint32_t	mbaddr:26;
539 		uint32_t	rsrvd:32;
540 #endif
541 	} bits;
542 } tdc_mbl_t;
543 
544 
545 /*
546  * Register: TdcByteCnt
547  * Tx DMA Byte Count
548  * Description: Counts the number of bytes transmitted to the tx
549  * datapath block. This count may increment in advance of
550  * corresponding updates to TdcStat for the bytes transmitted.
551  * Fields:
552  *     Number of bytes transmitted from transmit ring. This counter
553  *     will saturate. This register is cleared on read.
554  */
555 typedef union {
556 	uint64_t value;
557 	struct {
558 #if defined(_BIG_ENDIAN)
559 		uint32_t	rsrvd:32;
560 		uint32_t	byte_count:32;
561 #else
562 		uint32_t	byte_count:32;
563 		uint32_t	rsrvd:32;
564 #endif
565 	} bits;
566 } tdc_byte_cnt_t;
567 
568 
569 /*
570  * Register: TdcTdrQlen
571  * Tdr Queue Length
572  * Description: Number of descriptors in Tdr For debug only. Note:
573  * Not analogous to either rdc.rbrQlen or tdc.tdcKick -
574  * tdc.tdcTdrHead. Indicates depth of the two intermediate descriptor
575  * usage points rather than end-to-end descriptor availability.
576  * Fields:
577  *     Current number of descriptors in Tdr, unprefetched
578  *     Current number of descriptors in Tdr in prefetch buffer, i.e.
579  *     those which have been prefetched but have not yet been
580  *     allocated to the RTab.
581  */
582 typedef union {
583 	uint64_t value;
584 	struct {
585 #if defined(_BIG_ENDIAN)
586 		uint32_t	rsrvd:32;
587 		uint32_t	tdr_qlen:16;
588 		uint32_t	tdr_pref_qlen:16;
589 #else
590 		uint32_t	tdr_pref_qlen:16;
591 		uint32_t	tdr_qlen:16;
592 		uint32_t	rsrvd:32;
593 #endif
594 	} bits;
595 } tdc_tdr_qlen_t;
596 
597 
598 /*
599  * Register: TdcRtabPtr
600  * RTAB pointers
601  * Description: Status of the reorder table pointers Writing to this
602  * register is for debug purposes only and is enabled when vnmDbgOn
603  * is set to 1
604  * Fields:
605  *     Current rtab head pointer, used in the txPkt block This
606  *     register is used to dequeue entries in the reorder table when
607  *     packets are sent out
608  *     Current rtab head pointer, used in the pktResp block This
609  *     register is used to scan entries in the reorder table when
610  *     packet data response completions arrive
611  *     Current rtab tail pointer, used in the pktReq block This
612  *     register is used to allocate entries in the reorder table when
613  *     packet data requests are made
614  */
615 typedef union {
616 	uint64_t value;
617 	struct {
618 #if defined(_BIG_ENDIAN)
619 		uint32_t	rsrvd:24;
620 		uint32_t	pkt_rtab_head:8;
621 		uint32_t	rsrvd1:7;
622 		uint32_t	rtab_head:9;
623 		uint32_t	rsrvd2:7;
624 		uint32_t	rtab_tail:9;
625 #else
626 		uint32_t	rtab_tail:9;
627 		uint32_t	rsrvd2:7;
628 		uint32_t	rtab_head:9;
629 		uint32_t	rsrvd1:7;
630 		uint32_t	pkt_rtab_head:8;
631 		uint32_t	rsrvd:24;
632 #endif
633 	} bits;
634 } tdc_rtab_ptr_t;
635 
636 
637 /*
638  * Register: TdcDropCnt
639  * Packet Drop Counter
640  * Description: Counts the number of runt, aborted and size
641  * mismatched packets dropped by the tx datapath block.
642  * Fields:
643  *     Number of dropped due to pktSizeHdrErr. This counter will
644  *     saturate. This counter is cleared on read.
645  *     Number of dropped due to packet abort bit being set. Many
646  *     different error events could be the source of packet abort
647  *     drop. Descriptor-related error events include those errors
648  *     encountered while in the middle of processing a packet
649  *     request: 1. unexpectedSop; 2. non-SOP descriptor parity error
650  *     (prefParErr); 3. ran out of non-SOP descriptors due to peu
651  *     response errors (tdrPrefCplTo or peuRespErr) or the channel
652  *     being disabled before the TDR request can be made. Packet
653  *     response errors encountered while in the middle of processing
654  *     a packet request also can trigger the packet abort: 4. packet
655  *     response did not return due to peu response errors ( pktCplTo
656  *     or peuRespErr); 5. Rtab parity error (reordTblParErr). This
657  *     counter will saturate. This counter is cleared on read. Note
658  *     that packet aborts are not counted until the packet is cleared
659  *     from the RTab, which may be an arbitrary amount of time after
660  *     the corresponding error is logged in TdcStat. In most cases,
661  *     this will occur before the channel is quiesced following
662  *     channel disable. In an extreme case such as if a parity error
663  *     on an EOP descriptor prevents recognition of the EOP, it is
664  *     possible that the quiescent bit itself will not be set
665  *     although the packet drop counter will be incremented.
666  *     Number of dropped due to runt packet size error. This counter
667  *     will saturate. This counter is cleared on read.
668  */
669 typedef union {
670 	uint64_t value;
671 	struct {
672 #if defined(_BIG_ENDIAN)
673 		uint32_t	rsrvd:32;
674 		uint32_t	rsrvd_l:8;
675 		uint32_t	hdr_size_error_count:8;
676 		uint32_t	abort_count:8;
677 		uint32_t	runt_count:8;
678 #else
679 		uint32_t	runt_count:8;
680 		uint32_t	abort_count:8;
681 		uint32_t	hdr_size_error_count:8;
682 		uint32_t	rsrvd_l:8;
683 		uint32_t	rsrvd:32;
684 #endif
685 	} bits;
686 } tdc_drop_cnt_t;
687 
688 
689 /*
690  * Register: TdcLastPktRbufPtrs
691  * Last Packet RBUF Pointers
692  * Description: Logs the RBUF head and tail pointer of the last
693  * packet sent by the tx datapath block.
694  * Fields:
695  *     Logs the RBUF tail pointer of the last packet sent
696  *     Logs the RBUF head pointer of the last packet sent
697  */
698 typedef union {
699 	uint64_t value;
700 	struct {
701 #if defined(_BIG_ENDIAN)
702 		uint32_t	rsrvd:32;
703 		uint32_t	rsrvd_l:4;
704 		uint32_t	rbuf_tail_ptr:12;
705 		uint32_t	rsrvd1:4;
706 		uint32_t	rbuf_head_ptr:12;
707 #else
708 		uint32_t	rbuf_head_ptr:12;
709 		uint32_t	rsrvd1:4;
710 		uint32_t	rbuf_tail_ptr:12;
711 		uint32_t	rsrvd_l:4;
712 		uint32_t	rsrvd:32;
713 #endif
714 	} bits;
715 } tdc_last_pkt_rbuf_ptrs_t;
716 
717 
718 /*
719  * Register: TdcPrefCmd
720  * Tx DMA Prefetch Buffer Command
721  * Description: Allows debug access to the entire prefetch buffer.
722  * For writes, software writes the tdcPrefData and tdcPrefParData
723  * registers, before writing the tdcPrefCmd register. For reads,
724  * software writes the tdcPrefCmd register, then reads the
725  * tdcPrefData and tdcPrefParData registers. The valid field should
726  * be polled by software until it goes low, indicating the read or
727  * write has completed. Writing the tdcPrefCmd triggers the access.
728  * Fields:
729  *     status of indirect access 0=busy 1=done
730  *     Command type. 1 indicates a read command, 0 a write command.
731  *     enable writing of parity bits 1=enabled, 0=disabled
732  *     DMA channel of entry to read or write
733  *     Entry in the prefetch buffer to read or write
734  */
735 typedef union {
736 	uint64_t value;
737 	struct {
738 #if defined(_BIG_ENDIAN)
739 		uint32_t	rsrvd:32;
740 		uint32_t	status:1;
741 		uint32_t	cmd:1;
742 		uint32_t	par_en:1;
743 		uint32_t	rsrvd1:23;
744 		uint32_t	dmc:2;
745 		uint32_t	entry:4;
746 #else
747 		uint32_t	entry:4;
748 		uint32_t	dmc:2;
749 		uint32_t	rsrvd1:23;
750 		uint32_t	par_en:1;
751 		uint32_t	cmd:1;
752 		uint32_t	status:1;
753 		uint32_t	rsrvd:32;
754 #endif
755 	} bits;
756 } tdc_pref_cmd_t;
757 
758 
759 /*
760  * Register: TdcPrefData
761  * Tx DMA Prefetch Buffer Data
762  * Description: See tdcPrefCmd register.
763  * Fields:
764  *     For writes, data which is written into prefetch buffer. For
765  *     reads, data read from the prefetch buffer.
766  */
767 typedef union {
768 	uint64_t value;
769 	struct {
770 #if defined(_BIG_ENDIAN)
771 		uint32_t	data:32;
772 		uint32_t	data_l:32;
773 #else
774 		uint32_t	data_l:32;
775 		uint32_t	data:32;
776 #endif
777 	} bits;
778 } tdc_pref_data_t;
779 
780 
781 /*
782  * Register: TdcPrefParData
783  * Tx DMA Prefetch Buffer Parity Data
784  * Description: See tdcPrefCmd register.
785  * Fields:
786  *     For writes, parity data which is written into prefetch buffer.
787  *     For reads, parity data read from the prefetch buffer.
788  */
789 typedef union {
790 	uint64_t value;
791 	struct {
792 #if defined(_BIG_ENDIAN)
793 		uint32_t	rsrvd:32;
794 		uint32_t	rsrvd_l:24;
795 		uint32_t	par_data:8;
796 #else
797 		uint32_t	par_data:8;
798 		uint32_t	rsrvd_l:24;
799 		uint32_t	rsrvd:32;
800 #endif
801 	} bits;
802 } tdc_pref_par_data_t;
803 
804 
805 /*
806  * Register: TdcReordBufCmd
807  * Tx DMA Reorder Buffer Command
808  * Description: Allows debug access to the entire Reorder buffer. For
809  * writes, software writes the tdcReordBufData and tdcReordBufEccData
810  * before writing the tdcReordBufCmd register. For reads, software
811  * writes the tdcReordBufCmd register, then reads the tdcReordBufData
812  * and tdcReordBufEccData registers. The valid field should be polled
813  * by software until it goes low, indicating the read or write has
814  * completed. Writing the tdcReordBufCmd triggers the access.
815  * Fields:
816  *     status of indirect access 0=busy 1=done
817  *     Command type. 1 indicates a read command, 0 a write command.
818  *     enable writing of ecc bits 1=enabled, 0=disabled
819  *     Entry in the reorder buffer to read or write
820  */
821 typedef union {
822 	uint64_t value;
823 	struct {
824 #if defined(_BIG_ENDIAN)
825 		uint32_t	rsrvd:32;
826 		uint32_t	status:1;
827 		uint32_t	cmd:1;
828 		uint32_t	ecc_en:1;
829 		uint32_t	rsrvd1:17;
830 		uint32_t	entry:12;
831 #else
832 		uint32_t	entry:12;
833 		uint32_t	rsrvd1:17;
834 		uint32_t	ecc_en:1;
835 		uint32_t	cmd:1;
836 		uint32_t	status:1;
837 		uint32_t	rsrvd:32;
838 #endif
839 	} bits;
840 } tdc_reord_buf_cmd_t;
841 
842 
843 /*
844  * Register: TdcReordBufData
845  * Tx DMA Reorder Buffer Data
846  * Description: See tdcReordBufCmd register.
847  * Fields:
848  *     For writes, data which is written into reorder buffer. For
849  *     reads, data read from the reorder buffer.
850  */
851 typedef union {
852 	uint64_t value;
853 	struct {
854 #if defined(_BIG_ENDIAN)
855 		uint32_t	data:32;
856 		uint32_t	data_l:32;
857 #else
858 		uint32_t	data_l:32;
859 		uint32_t	data:32;
860 #endif
861 	} bits;
862 } tdc_reord_buf_data_t;
863 
864 
865 /*
866  * Register: TdcReordBufEccData
867  * Tx DMA Reorder Buffer ECC Data
868  * Description: See tdcReordBufCmd register.
869  * Fields:
870  *     For writes, ecc data which is written into reorder buffer. For
871  *     reads, ecc data read from the reorder buffer.
872  */
873 typedef union {
874 	uint64_t value;
875 	struct {
876 #if defined(_BIG_ENDIAN)
877 		uint32_t	rsrvd:32;
878 		uint32_t	rsrvd_l:24;
879 		uint32_t	ecc_data:8;
880 #else
881 		uint32_t	ecc_data:8;
882 		uint32_t	rsrvd_l:24;
883 		uint32_t	rsrvd:32;
884 #endif
885 	} bits;
886 } tdc_reord_buf_ecc_data_t;
887 
888 
889 /*
890  * Register: TdcReordTblCmd
891  * Tx DMA Reorder Table Command
892  * Description: Allows debug access to the entire Reorder Table. For
893  * writes, software writes the tdcReordTblData and tdcReordTblParData
894  * before writing the tdcReordTblCmd register. For reads, software
895  * writes the tdcReordTblCmd register, then reads the tdcReordTblData
896  * and tdcReordTblParData registers. The valid field should be polled
897  * by software until it goes low, indicating the read or write has
898  * completed. Writing the tdcReordTblCmd triggers the access.
899  * Fields:
900  *     status of indirect access 0=busy 1=done
901  *     Command type. 1 indicates a read command, 0 a write command.
902  *     enable writing of par bits 1=enabled, 0=disabled
903  *     Address in the reorder table to read from or write to
904  */
905 typedef union {
906 	uint64_t value;
907 	struct {
908 #if defined(_BIG_ENDIAN)
909 		uint32_t	rsrvd:32;
910 		uint32_t	status:1;
911 		uint32_t	cmd:1;
912 		uint32_t	par_en:1;
913 		uint32_t	rsrvd1:21;
914 		uint32_t	entry:8;
915 #else
916 		uint32_t	entry:8;
917 		uint32_t	rsrvd1:21;
918 		uint32_t	par_en:1;
919 		uint32_t	cmd:1;
920 		uint32_t	status:1;
921 		uint32_t	rsrvd:32;
922 #endif
923 	} bits;
924 } tdc_reord_tbl_cmd_t;
925 
926 
927 /*
928  * Register: TdcReordTblDataLo
929  * Tx DMA Reorder Table Data Lo
930  * Description: See tdcReordTblCmd register.
931  * Fields:
932  *     For writes, data which is written into reorder table. For
933  *     reads, data read from the reorder table.
934  */
935 typedef union {
936 	uint64_t value;
937 	struct {
938 #if defined(_BIG_ENDIAN)
939 		uint32_t	data:32;
940 		uint32_t	data_l:32;
941 #else
942 		uint32_t	data_l:32;
943 		uint32_t	data:32;
944 #endif
945 	} bits;
946 } tdc_reord_tbl_data_lo_t;
947 
948 
949 /*
950  * Register: TdcReordTblDataHi
951  * Tx DMA Reorder Table Data Hi
952  * Description: See tdcReordTblCmd register.
953  * Fields:
954  *     For writes, parity data which is written into reorder table.
955  *     For reads, parity data read from the reorder table.
956  *     For writes, data which is written into reorder table. For
957  *     reads, data read from the reorder table.
958  */
959 typedef union {
960 	uint64_t value;
961 	struct {
962 #if defined(_BIG_ENDIAN)
963 		uint32_t	rsrvd:32;
964 		uint32_t	rsrvd_l:15;
965 		uint32_t	par_data:9;
966 		uint32_t	hi_data:8;
967 #else
968 		uint32_t	hi_data:8;
969 		uint32_t	par_data:9;
970 		uint32_t	rsrvd_l:15;
971 		uint32_t	rsrvd:32;
972 #endif
973 	} bits;
974 } tdc_reord_tbl_data_hi_t;
975 
976 
977 /*
978  * Register: TdcPrefParLog
979  * Tx DMA Prefetch Buffer Parity Log
980  * Description: TDC DMA Prefetch Buffer parity log register This
981  * register logs the first parity error encountered. Writing a 1 to
982  * TdcStat::prefParErr clears this register and re-arms for logging
983  * the next error
984  * Fields:
985  *     Address of parity error read data
986  */
987 typedef union {
988 	uint64_t value;
989 	struct {
990 #if defined(_BIG_ENDIAN)
991 		uint32_t	rsrvd:32;
992 		uint32_t	rsrvd1:26;
993 		uint32_t	address:6;
994 #else
995 		uint32_t	address:6;
996 		uint32_t	rsrvd1:26;
997 		uint32_t	rsrvd:32;
998 #endif
999 	} bits;
1000 } tdc_pref_par_log_t;
1001 
1002 
1003 /*
1004  * Register: TdcReordBufEccLog
1005  * Tx Reorder Buffer ECC Log
1006  * Description: TDC Reorder Buffer ECC log register This register
1007  * logs the first ECC error encountered. Writing a 1 to
1008  * tdcFifoErrStat::reordBufDedErr or tdcFifoErrStat::reordBufSecErr
1009  * clears this register and re-arms for logging
1010  * Fields:
1011  *     Address of ECC error
1012  *     Syndrome of ECC error
1013  */
1014 typedef union {
1015 	uint64_t value;
1016 	struct {
1017 #if defined(_BIG_ENDIAN)
1018 		uint32_t	rsrvd:32;
1019 		uint32_t	rsrvd1:4;
1020 		uint32_t	address:12;
1021 		uint32_t	rsrvd2:8;
1022 		uint32_t	syndrome:8;
1023 #else
1024 		uint32_t	syndrome:8;
1025 		uint32_t	rsrvd2:8;
1026 		uint32_t	address:12;
1027 		uint32_t	rsrvd1:4;
1028 		uint32_t	rsrvd:32;
1029 #endif
1030 	} bits;
1031 } tdc_reord_buf_ecc_log_t;
1032 
1033 
1034 /*
1035  * Register: TdcReordTblParLog
1036  * Tx Reorder Table Parity Log
1037  * Description: TDC Reorder Table parity log register This register
1038  * logs the first parity error encountered. Writing a 1 to
1039  * tdcFifoErrStat::reordTblParErr clears this register and re-arms
1040  * for logging
1041  * Fields:
1042  *     Address of parity error
1043  */
1044 typedef union {
1045 	uint64_t value;
1046 	struct {
1047 #if defined(_BIG_ENDIAN)
1048 		uint32_t	rsrvd:32;
1049 		uint32_t	rsrvd1:24;
1050 		uint32_t	address:8;
1051 #else
1052 		uint32_t	address:8;
1053 		uint32_t	rsrvd1:24;
1054 		uint32_t	rsrvd:32;
1055 #endif
1056 	} bits;
1057 } tdc_reord_tbl_par_log_t;
1058 
1059 
1060 /*
1061  * Register: TdcFifoErrMask
1062  * FIFO Error Mask
1063  * Description: FIFO Error Mask register. Mask status of Reorder
1064  * Buffer and Reorder Table Buffer Errors.
1065  * Fields:
1066  *     Set to 0 to select the event to raise the LDF to indicate
1067  *     reorder table ram received a parity error An Device Error 1
1068  *     event.
1069  *     Set to 0 to select the event to raise the LDF to indicate
1070  *     reorder buffer ram received a ecc double bit error An Device
1071  *     Error 1 event.
1072  *     Set to 0 to select the event to raise the LDF to indicate
1073  *     reorder buffer ram received a ecc single bit error An Device
1074  *     Error 0 event.
1075  */
1076 typedef union {
1077 	uint64_t value;
1078 	struct {
1079 #if defined(_BIG_ENDIAN)
1080 		uint32_t	rsrvd:32;
1081 		uint32_t	rsrvd_l:29;
1082 		uint32_t	reord_tbl_par_err:1;
1083 		uint32_t	reord_buf_ded_err:1;
1084 		uint32_t	reord_buf_sec_err:1;
1085 #else
1086 		uint32_t	reord_buf_sec_err:1;
1087 		uint32_t	reord_buf_ded_err:1;
1088 		uint32_t	reord_tbl_par_err:1;
1089 		uint32_t	rsrvd_l:29;
1090 		uint32_t	rsrvd:32;
1091 #endif
1092 	} bits;
1093 } tdc_fifo_err_mask_t;
1094 
1095 
1096 /*
1097  * Register: TdcFifoErrStat
1098  * FIFO Error Status
1099  * Description: FIFO Error Status register. Log status of Reorder
1100  * Buffer and Reorder Table Buffer Errors.
1101  * Fields:
1102  *     Set to 1 by HW to indicate reorder table ram received a parity
1103  *     error Writing a 1 clears this bit and also clears the
1104  *     TdcReordTblParLog register Fatal error. Part of Device Error
1105  *     1.
1106  *     Set to 1 by HW to indicate reorder buffer ram received a
1107  *     double bit ecc error Writing a 1 clears this bit and also
1108  *     clears the tdcReordBufEccLog register Fatal error. Part of
1109  *     Device Error 1.
1110  *     Set to 1 by HW to indicate reorder buffer ram received a
1111  *     single bit ecc error Writing a 1 clears this bit and also
1112  *     clears the tdcReordBufEccLog register Non-Fatal error. Part of
1113  *     Device Error 0.
1114  */
1115 typedef union {
1116 	uint64_t value;
1117 	struct {
1118 #if defined(_BIG_ENDIAN)
1119 		uint32_t	rsrvd:32;
1120 		uint32_t	rsrvd_l:29;
1121 		uint32_t	reord_tbl_par_err:1;
1122 		uint32_t	reord_buf_ded_err:1;
1123 		uint32_t	reord_buf_sec_err:1;
1124 #else
1125 		uint32_t	reord_buf_sec_err:1;
1126 		uint32_t	reord_buf_ded_err:1;
1127 		uint32_t	reord_tbl_par_err:1;
1128 		uint32_t	rsrvd_l:29;
1129 		uint32_t	rsrvd:32;
1130 #endif
1131 	} bits;
1132 } tdc_fifo_err_stat_t;
1133 
1134 
1135 /*
1136  * Register: TdcFifoErrIntDbg
1137  * FIFO Error Interrupt Debug
1138  * Description: FIFO Error Interrupt Debug register. Write this
1139  * regsiter to set bits in TdcFifoErrStat, allowing debug creation of
1140  * interrupts without needing to create the actual events. This
1141  * register holds no state. Reading this register gives the Tdc Fifo
1142  * Err Status data. Clear interrupt state by clearing TdcFifoErrStat.
1143  * For Debug only
1144  * Fields:
1145  *     Set to 1 to select the event to raise the LDF to indicate
1146  *     reorder table ram received a parity error An Device Error 1
1147  *     event.
1148  *     Set to 1 to select the event to raise the LDF to indicate
1149  *     reorder buffer ram received a ecc double bit error An Device
1150  *     Error 1 event.
1151  *     Set to 1 to select the event to raise the LDF to indicate
1152  *     reorder buffer ram received a ecc single bit error An Device
1153  *     Error 0 event.
1154  */
1155 typedef union {
1156 	uint64_t value;
1157 	struct {
1158 #if defined(_BIG_ENDIAN)
1159 		uint32_t	rsrvd:32;
1160 		uint32_t	rsrvd_l:29;
1161 		uint32_t	reord_tbl_par_err:1;
1162 		uint32_t	reord_buf_ded_err:1;
1163 		uint32_t	reord_buf_sec_err:1;
1164 #else
1165 		uint32_t	reord_buf_sec_err:1;
1166 		uint32_t	reord_buf_ded_err:1;
1167 		uint32_t	reord_tbl_par_err:1;
1168 		uint32_t	rsrvd_l:29;
1169 		uint32_t	rsrvd:32;
1170 #endif
1171 	} bits;
1172 } tdc_fifo_err_int_dbg_t;
1173 
1174 
1175 /*
1176  * Register: TdcStatIntDbg
1177  * Transmit Status Interrupt Debug
1178  * Description: Write this regsiter to set bits in TdcStat, allowing
1179  * debug creation of interrupts without needing to create the actual
1180  * events. This register holds no state. Reading this register gives
1181  * the Transmit Control and Status data. Clear interrupt state by
1182  * clearing TdcStat. For Debug only
1183  * Fields:
1184  *     Set to 1 to select the event to raise the LDF for packets
1185  *     marked. An LDF 0 event.
1186  *     Set to 1 to select the event to raise the LDF when poisoned
1187  *     completion or non-zero (unsuccessful) completion status
1188  *     received from PEU. An LDF 1 event.
1189  *     Set to 1 to select the event to raise the LDF when total bytes
1190  *     transmitted compared against pkt internal header bytes
1191  *     transmitted mismatch. An LDF 1 event.
1192  *     Set to 1 to select the event to raise the LDF when a runt
1193  *     packet is dropped (when VMAC does not allow runt packets to be
1194  *     padded). An LDF 1 event.
1195  *     Set to 1 to select the event to raise the LDF when the packet
1196  *     size exceeds hardware limit. An LDF 1 event.
1197  *     Set to 1 to select the event to raise the LDF to indicate
1198  *     Transmit Ring Overflow An LDF 1 event.
1199  *     Set to 1 to select the event to raise the LDF to indicate
1200  *     parity error on the tdr prefetch buffer occurred. An LDF 1
1201  *     event.
1202  *     Set to 1 to select the event to raise the LDF to indicate tdc
1203  *     received a response completion timeout from peu for tdr
1204  *     descriptor prefetch An LDF 1 event.
1205  *     Set to 1 to select the event to raise the LDF to indicate tdc
1206  *     received a response completion timeout from peu for packet
1207  *     data request An LDF 1 event.
1208  *     Set to 1 to select the event to raise the LDF to indicate tdc
1209  *     did not receive an SOP in the 1st descriptor as was expected
1210  *     or the numPtr in the 1st descriptor was set to 0. An LDF 1
1211  *     event.
1212  *     Set to 1 to select the event to raise the LDF to indicate tdc
1213  *     received an unexpected SOP descriptor error. An LDF 1 event.
1214  */
1215 typedef union {
1216 	uint64_t value;
1217 	struct {
1218 #if defined(_BIG_ENDIAN)
1219 		uint32_t	rsrvd:32;
1220 		uint32_t	rsrvd_l:16;
1221 		uint32_t	marked:1;
1222 		uint32_t	rsrvd1:5;
1223 		uint32_t	peu_resp_err:1;
1224 		uint32_t	pkt_size_hdr_err:1;
1225 		uint32_t	runt_pkt_drop_err:1;
1226 		uint32_t	pkt_size_err:1;
1227 		uint32_t	tx_rng_oflow:1;
1228 		uint32_t	pref_par_err:1;
1229 		uint32_t	tdr_pref_cpl_to:1;
1230 		uint32_t	pkt_cpl_to:1;
1231 		uint32_t	invalid_sop:1;
1232 		uint32_t	unexpected_sop:1;
1233 #else
1234 		uint32_t	unexpected_sop:1;
1235 		uint32_t	invalid_sop:1;
1236 		uint32_t	pkt_cpl_to:1;
1237 		uint32_t	tdr_pref_cpl_to:1;
1238 		uint32_t	pref_par_err:1;
1239 		uint32_t	tx_rng_oflow:1;
1240 		uint32_t	pkt_size_err:1;
1241 		uint32_t	runt_pkt_drop_err:1;
1242 		uint32_t	pkt_size_hdr_err:1;
1243 		uint32_t	peu_resp_err:1;
1244 		uint32_t	rsrvd1:5;
1245 		uint32_t	marked:1;
1246 		uint32_t	rsrvd_l:16;
1247 		uint32_t	rsrvd:32;
1248 #endif
1249 	} bits;
1250 } tdc_stat_int_dbg_t;
1251 
1252 
1253 /*
1254  * Register: TdcPktReqTidTag
1255  * Packet Request TID Tag
1256  * Description: Packet Request TID Tag register Track the packet
1257  * request TID currently used
1258  * Fields:
1259  *     When set to 1, it indicates the TID is currently being used
1260  */
1261 typedef union {
1262 	uint64_t value;
1263 	struct {
1264 #if defined(_BIG_ENDIAN)
1265 		uint32_t	rsrvd:32;
1266 		uint32_t	pkt_req_tid_tag:24;
1267 		uint32_t	rsrvd1:8;
1268 #else
1269 		uint32_t	rsrvd1:8;
1270 		uint32_t	pkt_req_tid_tag:24;
1271 		uint32_t	rsrvd:32;
1272 #endif
1273 	} bits;
1274 } tdc_pkt_req_tid_tag_t;
1275 
1276 
1277 /*
1278  * Register: TdcSopPrefDescLog
1279  * SOP Prefetch Descriptor Log
1280  * Description: SOP Descriptor Log register Logs the last SOP
1281  * prefetch descriptor processed by the packet request block. This
1282  * log could represent the current SOP prefetch descriptor if the
1283  * packet request block did not complete issuing the data requests
1284  * from this descriptor. Descriptors are logged to this register when
1285  * the packet request block is expecting an SOP descriptor, and it
1286  * receives it.
1287  * Fields:
1288  *     Represents the last or current SOP descriptor being processed
1289  */
1290 typedef union {
1291 	uint64_t value;
1292 	struct {
1293 #if defined(_BIG_ENDIAN)
1294 		uint32_t	sop_pref_desc_log:32;
1295 		uint32_t	sop_pref_desc_log_l:32;
1296 #else
1297 		uint32_t	sop_pref_desc_log_l:32;
1298 		uint32_t	sop_pref_desc_log:32;
1299 #endif
1300 	} bits;
1301 } tdc_sop_pref_desc_log_t;
1302 
1303 
1304 /*
1305  * Register: TdcPrefDescLog
1306  * Prefetch Descriptor Log
1307  * Description: SOP Descriptor Log register Logs the last prefetch
1308  * descriptor processed by the packet request block. This log could
1309  * represent the current prefetch descriptor if the packet request
1310  * block did not complete issuing the data requests from this
1311  * descriptor. The contents in this register could differ from the
1312  * SOP Prefetch Descriptor Log register if a particular packet
1313  * requires usage of more than 1 descriptor. Descriptors are logged
1314  * to this register when the packet request block is expecting a
1315  * descriptor after the SOP descriptor.
1316  * Fields:
1317  *     Represents the last or current descriptor being processed
1318  */
1319 typedef union {
1320 	uint64_t value;
1321 	struct {
1322 #if defined(_BIG_ENDIAN)
1323 		uint32_t	pref_desc_log:32;
1324 		uint32_t	pref_desc_log_l:32;
1325 #else
1326 		uint32_t	pref_desc_log_l:32;
1327 		uint32_t	pref_desc_log:32;
1328 #endif
1329 	} bits;
1330 } tdc_pref_desc_log_t;
1331 
1332 
1333 /*
1334  * Register: TdcPeuTxnLog
1335  * PEU Transaction Log
1336  * Description: PEU Transaction Log register. Counts the memory read
1337  * and write requests sent to peu block. For debug only.
1338  * Fields:
1339  *     Counts the memory write transactions sent to peu block. This
1340  *     counter saturates. This counter increments when vnmDbg is on
1341  *     Counts the memory read transactions sent to peu block. This
1342  *     counter saturates. This counter increments when vnmDbg is on
1343  */
1344 typedef union {
1345 	uint64_t value;
1346 	struct {
1347 #if defined(_BIG_ENDIAN)
1348 		uint32_t	rsrvd:32;
1349 		uint32_t	rsrvd1:16;
1350 		uint32_t	peu_mem_wr_count:8;
1351 		uint32_t	peu_mem_rd_count:8;
1352 #else
1353 		uint32_t	peu_mem_rd_count:8;
1354 		uint32_t	peu_mem_wr_count:8;
1355 		uint32_t	rsrvd1:16;
1356 		uint32_t	rsrvd:32;
1357 #endif
1358 	} bits;
1359 } tdc_peu_txn_log_t;
1360 
1361 
1362 /*
1363  * Register: TdcDbgTrainingVec
1364  * Debug Training Vector
1365  * Description: Debug Training Vector register. Debug Training Vector
1366  * for the coreClk domain. For the pcieClk domain, the dbgxMsb and
1367  * dbgyMsb values are flipped on the debug bus.
1368  * Fields:
1369  *     Blade Number, the value read depends on the blade this block
1370  *     resides
1371  *     debug training vector the sub-group select value of 0 selects
1372  *     this vector
1373  *     Blade Number, the value read depends on the blade this block
1374  *     resides
1375  *     debug training vector the sub-group select value of 0 selects
1376  *     this vector
1377  */
1378 typedef union {
1379 	uint64_t value;
1380 	struct {
1381 #if defined(_BIG_ENDIAN)
1382 		uint32_t	rsrvd:32;
1383 		uint32_t	dbgx_msb:1;
1384 		uint32_t	dbgx_bld_num:3;
1385 		uint32_t	dbgx_training_vec:12;
1386 		uint32_t	dbgy_msb:1;
1387 		uint32_t	dbgy_bld_num:3;
1388 		uint32_t	dbgy_training_vec:12;
1389 #else
1390 		uint32_t	dbgy_training_vec:12;
1391 		uint32_t	dbgy_bld_num:3;
1392 		uint32_t	dbgy_msb:1;
1393 		uint32_t	dbgx_training_vec:12;
1394 		uint32_t	dbgx_bld_num:3;
1395 		uint32_t	dbgx_msb:1;
1396 		uint32_t	rsrvd:32;
1397 #endif
1398 	} bits;
1399 } tdc_dbg_training_vec_t;
1400 
1401 
1402 /*
1403  * Register: TdcDbgGrpSel
1404  * Debug Group Select
1405  * Description: Debug Group Select register. Debug Group Select
1406  * register selects the group of signals brought out on the debug
1407  * port
1408  * Fields:
1409  *     high 32b sub-group select
1410  *     low 32b sub-group select
1411  */
1412 typedef union {
1413 	uint64_t value;
1414 	struct {
1415 #if defined(_BIG_ENDIAN)
1416 		uint32_t	rsrvd:32;
1417 		uint32_t	rsrvd_l:16;
1418 		uint32_t	rsrvd1:1;
1419 		uint32_t	dbg_h32_sub_sel:7;
1420 		uint32_t	rsrvd2:1;
1421 		uint32_t	dbg_l32_sub_sel:7;
1422 #else
1423 		uint32_t	dbg_l32_sub_sel:7;
1424 		uint32_t	rsrvd2:1;
1425 		uint32_t	dbg_h32_sub_sel:7;
1426 		uint32_t	rsrvd1:1;
1427 		uint32_t	rsrvd_l:16;
1428 		uint32_t	rsrvd:32;
1429 #endif
1430 	} bits;
1431 } tdc_dbg_grp_sel_t;
1432 
1433 
1434 #ifdef	__cplusplus
1435 }
1436 #endif
1437 
1438 #endif	/* _HXGE_TDC_HW_H */
1439