xref: /titanic_41/usr/src/uts/common/io/chxge/com/suni1x10gexp_regs.h (revision d39a76e7b087a3d0927cbe6898dc0a6770fa6c68)
1 
2 /*
3  * Copyright 1994-2005 The FreeBSD Project. All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT ``AS IS'' AND ANY EXPRESS
15  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17  * NO EVENT SHALL THE FREEBSD PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
18  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
21  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  *
25  * The views and conclusions contained in the software and documentation are
26  * those of the authors and should not be interpreted as representing official
27  * policies, either expressed or implied, of the FreeBSD Project.
28  */
29 
30 
31 #pragma ident	"%Z%%M%	%I%	%E% SMI"	/* suni1x10gexp_regs.h */
32 
33 #ifndef _SUNI1x10GEXP_REGS_H
34 #define _SUNI1x10GEXP_REGS_H
35 
36 
37 /*
38 ** Space allocated for each Exact Match Filter
39 **     There are 8 filter configurations
40 */
41 #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
42 
43 #define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)       ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
44 
45 /*
46 ** Space allocated for VLAN-Id Filter
47 **      There are 8 filter configurations
48 */
49 #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
50 
51 #define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)   ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
52 
53 /*
54 ** Space allocated for each MSTAT Counter
55 */
56 #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
57 
58 #define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)       ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
59 
60 
61 /******************************************************************************/
62 /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP                                     **/
63 /******************************************************************************/
64 /* Refer to the Register Bit Masks bellow for the naming of each register and */
65 /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit        */
66 /******************************************************************************/
67 
68 
69 #define SUNI1x10GEXP_REG_IDENTIFICATION                                  0x0000
70 #define SUNI1x10GEXP_REG_PRODUCT_REVISION                                0x0001
71 #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL                        0x0002
72 #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL                              0x0003
73 #define SUNI1x10GEXP_REG_DEVICE_STATUS                                   0x0004
74 #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE               0x0005
75 
76 #define SUNI1x10GEXP_REG_MDIO_COMMAND                                    0x0006
77 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE                           0x0007
78 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS                           0x0008
79 #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS                                 0x0009
80 #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA                        0x000A
81 #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA                           0x000B
82 
83 #define SUNI1x10GEXP_REG_OAM_INTF_CTRL                                   0x000C
84 #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS                         0x000D
85 #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE                         0x000E
86 #define SUNI1x10GEXP_REG_FREE                                            0x000F
87 
88 #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL                                  0x0010
89 #define SUNI1x10GEXP_REG_XRF_MISC_CTRL                                   0x0011
90 
91 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1                            0x0100
92 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2                            0x0101
93 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE                    0x0102
94 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE                   0x0103
95 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS                    0x0104
96 #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG                         0x0107
97 
98 #define SUNI1x10GEXP_REG_RXXG_CONFIG_1                                   0x2040
99 #define SUNI1x10GEXP_REG_RXXG_CONFIG_2                                   0x2041
100 #define SUNI1x10GEXP_REG_RXXG_CONFIG_3                                   0x2042
101 #define SUNI1x10GEXP_REG_RXXG_INTERRUPT                                  0x2043
102 #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH                           0x2045
103 #define SUNI1x10GEXP_REG_RXXG_SA_15_0                                    0x2046
104 #define SUNI1x10GEXP_REG_RXXG_SA_31_16                                   0x2047
105 #define SUNI1x10GEXP_REG_RXXG_SA_47_32                                   0x2048
106 #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD                     0x2049
107 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
108 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
109 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
110 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId)      (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)
111 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW                     0x204A
112 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID                     0x204B
113 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH                    0x204C
114 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW                     0x204D
115 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID                     0x204E
116 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH                    0x204F
117 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW                     0x2050
118 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID                     0x2051
119 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH                    0x2052
120 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW                     0x2053
121 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID                     0x2054
122 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH                    0x2055
123 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW                     0x2056
124 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID                     0x2057
125 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH                    0x2058
126 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW                     0x2059
127 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID                     0x205A
128 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH                    0x205B
129 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW                     0x205C
130 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID                     0x205D
131 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH                    0x205E
132 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW                     0x205F
133 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID                     0x2060
134 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH                    0x2061
135 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0                          0x2062
136 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1                          0x2063
137 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2                          0x2064
138 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3                          0x2065
139 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4                          0x2066
140 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5                          0x2067
141 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6                          0x2068
142 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7                          0x2069
143 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW                         0x206A
144 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW                      0x206B
145 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH                     0x206C
146 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH                        0x206D
147 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0                   0x206E
148 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1                   0x206F
149 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2                   0x2070
150 
151 #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL                            0x2081
152 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0                       0x2084
153 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1                       0x2085
154 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2                       0x2086
155 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3                       0x2087
156 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE                            0x2088
157 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS                            0x2089
158 #define SUNI1x10GEXP_REG_XRF_ERR_STATUS                                  0x208A
159 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE                       0x208B
160 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS                       0x208C
161 #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES                              0x2092
162 
163 #define SUNI1x10GEXP_REG_RXOAM_CONFIG                                    0x20C0
164 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG                           0x20C1
165 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG                           0x20C2
166 #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2                                  0x20C3
167 #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG                                0x20C4
168 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES                             0x20C5
169 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE                          0x20C7
170 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS                          0x20C8
171 #define SUNI1x10GEXP_REG_RXOAM_STATUS                                    0x20C9
172 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT                             0x20CA
173 #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT                       0x20CB
174 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB                 0x20CC
175 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB                 0x20CD
176 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB               0x20CE
177 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB               0x20CF
178 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB               0x20D0
179 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB               0x20D1
180 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB                     0x20D2
181 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB                     0x20D3
182 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB                     0x20D4
183 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB                     0x20D5
184 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB                 0x20D6
185 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB                 0x20D7
186 
187 #define SUNI1x10GEXP_REG_MSTAT_CONTROL                                   0x2100
188 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0                        0x2101
189 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1                        0x2102
190 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2                        0x2103
191 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3                        0x2104
192 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0                          0x2105
193 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1                          0x2106
194 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2                          0x2107
195 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3                          0x2108
196 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS                     0x2109
197 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW                    0x210A
198 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE                 0x210B
199 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH                   0x210C
200 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId)   (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
201 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId)   (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
202 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId)  (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
203 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW                             0x2110
204 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID                             0x2111
205 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH                            0x2112
206 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD                           0x2113
207 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW                             0x2114
208 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID                             0x2115
209 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH                            0x2116
210 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD                           0x2117
211 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW                             0x2118
212 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID                             0x2119
213 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH                            0x211A
214 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD                           0x211B
215 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW                             0x211C
216 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID                             0x211D
217 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH                            0x211E
218 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD                           0x211F
219 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW                             0x2120
220 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID                             0x2121
221 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH                            0x2122
222 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD                           0x2123
223 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW                             0x2124
224 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID                             0x2125
225 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH                            0x2126
226 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD                           0x2127
227 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW                             0x2128
228 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID                             0x2129
229 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH                            0x212A
230 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD                           0x212B
231 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW                             0x212C
232 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID                             0x212D
233 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH                            0x212E
234 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD                           0x212F
235 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW                             0x2130
236 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID                             0x2131
237 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH                            0x2132
238 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD                           0x2133
239 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW                             0x2134
240 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID                             0x2135
241 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH                            0x2136
242 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD                           0x2137
243 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW                            0x2138
244 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID                            0x2139
245 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH                           0x213A
246 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD                          0x213B
247 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW                            0x213C
248 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID                            0x213D
249 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH                           0x213E
250 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD                          0x213F
251 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW                            0x2140
252 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID                            0x2141
253 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH                           0x2142
254 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD                          0x2143
255 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW                            0x2144
256 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID                            0x2145
257 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH                           0x2146
258 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD                          0x2147
259 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW                            0x2148
260 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID                            0x2149
261 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH                           0x214A
262 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD                          0x214B
263 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW                            0x214C
264 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID                            0x214D
265 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH                           0x214E
266 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD                          0x214F
267 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW                            0x2150
268 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID                            0x2151
269 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH                           0x2152
270 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD                          0x2153
271 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW                            0x2154
272 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID                            0x2155
273 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH                           0x2156
274 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD                          0x2157
275 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW                            0x2158
276 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID                            0x2159
277 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH                           0x215A
278 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD                          0x215B
279 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW                            0x215C
280 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID                            0x215D
281 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH                           0x215E
282 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD                          0x215F
283 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW                            0x2160
284 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID                            0x2161
285 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH                           0x2162
286 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD                          0x2163
287 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW                            0x2164
288 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID                            0x2165
289 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH                           0x2166
290 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD                          0x2167
291 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW                            0x2168
292 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID                            0x2169
293 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH                           0x216A
294 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD                          0x216B
295 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW                            0x216C
296 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID                            0x216D
297 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH                           0x216E
298 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD                          0x216F
299 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW                            0x2170
300 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID                            0x2171
301 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH                           0x2172
302 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD                          0x2173
303 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW                            0x2174
304 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID                            0x2175
305 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH                           0x2176
306 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD                          0x2177
307 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW                            0x2178
308 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID                            0x2179
309 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH                           0x217a
310 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD                          0x217b
311 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW                            0x217c
312 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID                            0x217d
313 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH                           0x217e
314 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD                          0x217f
315 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW                            0x2180
316 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID                            0x2181
317 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH                           0x2182
318 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD                          0x2183
319 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW                            0x2184
320 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID                            0x2185
321 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH                           0x2186
322 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD                          0x2187
323 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW                            0x2188
324 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID                            0x2189
325 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH                           0x218A
326 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD                          0x218B
327 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW                            0x218C
328 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID                            0x218D
329 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH                           0x218E
330 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD                          0x218F
331 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW                            0x2190
332 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID                            0x2191
333 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH                           0x2192
334 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD                          0x2193
335 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW                            0x2194
336 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID                            0x2195
337 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH                           0x2196
338 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD                          0x2197
339 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW                            0x2198
340 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID                            0x2199
341 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH                           0x219A
342 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD                          0x219B
343 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW                            0x219C
344 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID                            0x219D
345 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH                           0x219E
346 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD                          0x219F
347 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW                            0x21A0
348 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID                            0x21A1
349 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH                           0x21A2
350 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD                          0x21A3
351 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW                            0x21A4
352 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID                            0x21A5
353 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH                           0x21A6
354 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD                          0x21A7
355 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW                            0x21A8
356 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID                            0x21A9
357 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH                           0x21AA
358 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD                          0x21AB
359 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW                            0x21AC
360 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID                            0x21AD
361 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH                           0x21AE
362 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD                          0x21AF
363 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW                            0x21B0
364 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID                            0x21B1
365 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH                           0x21B2
366 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD                          0x21B3
367 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW                            0x21B4
368 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID                            0x21B5
369 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH                           0x21B6
370 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD                          0x21B7
371 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW                            0x21B8
372 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID                            0x21B9
373 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH                           0x21BA
374 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD                          0x21BB
375 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW                            0x21BC
376 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID                            0x21BD
377 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH                           0x21BE
378 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD                          0x21BF
379 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW                            0x21C0
380 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID                            0x21C1
381 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH                           0x21C2
382 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD                          0x21C3
383 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW                            0x21C4
384 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID                            0x21C5
385 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH                           0x21C6
386 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD                          0x21C7
387 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW                            0x21C8
388 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID                            0x21C9
389 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH                           0x21CA
390 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD                          0x21CB
391 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW                            0x21CC
392 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID                            0x21CD
393 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH                           0x21CE
394 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD                          0x21CF
395 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW                            0x21D0
396 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID                            0x21D1
397 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH                           0x21D2
398 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD                          0x21D3
399 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW                            0x21D4
400 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID                            0x21D5
401 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH                           0x21D6
402 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD                          0x21D7
403 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW                            0x21D8
404 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID                            0x21D9
405 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH                           0x21DA
406 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD                          0x21DB
407 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW                            0x21DC
408 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID                            0x21DD
409 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH                           0x21DE
410 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD                          0x21DF
411 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW                            0x21E0
412 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID                            0x21E1
413 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH                           0x21E2
414 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD                          0x21E3
415 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW                            0x21E4
416 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID                            0x21E5
417 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH                           0x21E6
418 #define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM                               51
419 
420 #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG                              0x2200
421 #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION                          0x2201
422 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE                       0x2209
423 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT                    0x220A
424 #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS                      0x220D
425 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION     0x220E
426 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT              0x220F
427 #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT        0x2210
428 #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT      0x2211
429 
430 #define SUNI1x10GEXP_REG_PL4MOS_CONFIG                                   0x2240
431 #define SUNI1x10GEXP_REG_PL4MOS_MASK                                     0x2241
432 #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING                         0x2242
433 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1                                0x2243
434 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2                                0x2244
435 #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE                            0x2245
436 
437 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG                                   0x2280
438 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK                           0x2282
439 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT                                0x2283
440 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T                             0x2284
441 
442 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS                        0x2300
443 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE                        0x2301
444 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK                          0x2302
445 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS                        0x2303
446 #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS                      0x2304
447 #define SUNI1x10GEXP_REG_PL4IO_CONFIG                                    0x2305
448 
449 #define SUNI1x10GEXP_REG_TXXG_CONFIG_1                                   0x3040
450 #define SUNI1x10GEXP_REG_TXXG_CONFIG_2                                   0x3041
451 #define SUNI1x10GEXP_REG_TXXG_CONFIG_3                                   0x3042
452 #define SUNI1x10GEXP_REG_TXXG_INTERRUPT                                  0x3043
453 #define SUNI1x10GEXP_REG_TXXG_STATUS                                     0x3044
454 #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE                             0x3045
455 #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE                             0x3046
456 #define SUNI1x10GEXP_REG_TXXG_SA_15_0                                    0x3047
457 #define SUNI1x10GEXP_REG_TXXG_SA_31_16                                   0x3048
458 #define SUNI1x10GEXP_REG_TXXG_SA_47_32                                   0x3049
459 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER                                0x304D
460 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL                       0x304E
461 #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER                       0x3051
462 #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG                       0x3052
463 
464 #define SUNI1x10GEXP_REG_XTEF_CTRL                                       0x3080
465 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS                           0x3084
466 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE                           0x3085
467 #define SUNI1x10GEXP_REG_XTEF_VISIBILITY                                 0x3086
468 
469 #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG                                0x30C0
470 #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG                          0x30C1
471 #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG                      0x30C2
472 #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES                        0x30C3
473 #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES                        0x30C4
474 #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES                        0x30C5
475 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE                          0x30C6
476 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS                          0x30C7
477 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB                          0x30C8
478 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB                          0x30C9
479 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB                        0x30CA
480 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB                        0x30CB
481 #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK                            0x30CC
482 #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK                            0x30CD
483 #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK                            0x30CE
484 #define SUNI1x10GEXP_REG_TXOAM_COSET                                     0x30CF
485 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB                 0x30D0
486 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB                 0x30D1
487 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB               0x30D2
488 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB               0x30D3
489 
490 
491 #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG                              0x3200
492 #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS                         0x3201
493 #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS                      0x3202
494 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT                       0x3203
495 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT                      0x3204
496 #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT    0x3205
497 #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT  0x3206
498 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD           0x3207
499 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE                 0x320C
500 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION             0x320D
501 #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION                          0x3210
502 
503 #define SUNI1x10GEXP_REG_PL4IDU_CONFIG                                   0x3280
504 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK                           0x3282
505 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT                                0x3283
506 
507 
508 /*----------------------------------------*/
509 #define SUNI1x10GEXP_REG_MAX_OFFSET                                      0x3480
510 
511 /******************************************************************************/
512 /*                 -- End register offset definitions --                      */
513 /******************************************************************************/
514 
515 /******************************************************************************/
516 /** SUNI-1x10GE-XP REGISTER BIT MASKS                                        **/
517 /******************************************************************************/
518 
519 #define SUNI1x10GEXP_BITMSK_BITS_1   0x00001
520 #define SUNI1x10GEXP_BITMSK_BITS_2   0x00003
521 #define SUNI1x10GEXP_BITMSK_BITS_3   0x00007
522 #define SUNI1x10GEXP_BITMSK_BITS_4   0x0000f
523 #define SUNI1x10GEXP_BITMSK_BITS_5   0x0001f
524 #define SUNI1x10GEXP_BITMSK_BITS_6   0x0003f
525 #define SUNI1x10GEXP_BITMSK_BITS_7   0x0007f
526 #define SUNI1x10GEXP_BITMSK_BITS_8   0x000ff
527 #define SUNI1x10GEXP_BITMSK_BITS_9   0x001ff
528 #define SUNI1x10GEXP_BITMSK_BITS_10  0x003ff
529 #define SUNI1x10GEXP_BITMSK_BITS_11  0x007ff
530 #define SUNI1x10GEXP_BITMSK_BITS_12  0x00fff
531 #define SUNI1x10GEXP_BITMSK_BITS_13  0x01fff
532 #define SUNI1x10GEXP_BITMSK_BITS_14  0x03fff
533 #define SUNI1x10GEXP_BITMSK_BITS_15  0x07fff
534 #define SUNI1x10GEXP_BITMSK_BITS_16  0x0ffff
535 
536 #define mSUNI1x10GEXP_CLR_MSBITS_1(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
537 #define mSUNI1x10GEXP_CLR_MSBITS_2(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
538 #define mSUNI1x10GEXP_CLR_MSBITS_3(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
539 #define mSUNI1x10GEXP_CLR_MSBITS_4(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
540 #define mSUNI1x10GEXP_CLR_MSBITS_5(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
541 #define mSUNI1x10GEXP_CLR_MSBITS_6(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
542 #define mSUNI1x10GEXP_CLR_MSBITS_7(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
543 #define mSUNI1x10GEXP_CLR_MSBITS_8(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
544 #define mSUNI1x10GEXP_CLR_MSBITS_9(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
545 #define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
546 #define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
547 #define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
548 #define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
549 #define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
550 #define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
551 
552 #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
553 
554 
555 
556 /*----------------------------------------------------------------------------
557  * Register 0x0001: S/UNI-1x10GE-XP Product Revision
558  *    Bit 3-0  REVISION
559  *----------------------------------------------------------------------------*/
560 #define SUNI1x10GEXP_BITMSK_REVISION  0x000F
561 
562 /*----------------------------------------------------------------------------
563  * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
564  *    Bit 2  XAUI_ARESETB
565  *    Bit 1  PL4_ARESETB
566  *    Bit 0  DRESETB
567  *----------------------------------------------------------------------------*/
568 #define SUNI1x10GEXP_BITMSK_XAUI_ARESET  0x0004
569 #define SUNI1x10GEXP_BITMSK_PL4_ARESET   0x0002
570 #define SUNI1x10GEXP_BITMSK_DRESETB      0x0001
571 
572 /*----------------------------------------------------------------------------
573  * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
574  *    Bit 11  PL4IO_OUTCLKSEL
575  *    Bit 9   SYSPCSLB
576  *    Bit 8   LINEPCSLB
577  *    Bit 7   MSTAT_BYPASS
578  *    Bit 6   RXXG_BYPASS
579  *    Bit 5   TXXG_BYPASS
580  *    Bit 4   SOP_PAD_EN
581  *    Bit 1   LOS_INV
582  *    Bit 0   OVERRIDE_LOS
583  *----------------------------------------------------------------------------*/
584 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL  0x0800
585 #define SUNI1x10GEXP_BITMSK_SYSPCSLB         0x0200
586 #define SUNI1x10GEXP_BITMSK_LINEPCSLB        0x0100
587 #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS     0x0080
588 #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS      0x0040
589 #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS      0x0020
590 #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN       0x0010
591 #define SUNI1x10GEXP_BITMSK_LOS_INV          0x0002
592 #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS     0x0001
593 
594 /*----------------------------------------------------------------------------
595  * Register 0x0004: S/UNI-1x10GE-XP Device Status
596  *    Bit 9 TOP_SXRA_EXPIRED
597  *    Bit 8 TOP_MDIO_BUSY
598  *    Bit 7 TOP_DTRB
599  *    Bit 6 TOP_EXPIRED
600  *    Bit 5 TOP_PAUSED
601  *    Bit 4 TOP_PL4_ID_DOOL
602  *    Bit 3 TOP_PL4_IS_DOOL
603  *    Bit 2 TOP_PL4_ID_ROOL
604  *    Bit 1 TOP_PL4_IS_ROOL
605  *    Bit 0 TOP_PL4_OUT_ROOL
606  *----------------------------------------------------------------------------*/
607 #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED  0x0200
608 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY     0x0100
609 #define SUNI1x10GEXP_BITMSK_TOP_DTRB          0x0080
610 #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED       0x0040
611 #define SUNI1x10GEXP_BITMSK_TOP_PAUSED        0x0020
612 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL   0x0010
613 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL   0x0008
614 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL   0x0004
615 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL   0x0002
616 #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL  0x0001
617 
618 /*----------------------------------------------------------------------------
619  * Register 0x0005: Global Performance Update and Clock Monitors
620  *    Bit 15 TIP
621  *    Bit 8  XAUI_REF_CLKA
622  *    Bit 7  RXLANE3CLKA
623  *    Bit 6  RXLANE2CLKA
624  *    Bit 5  RXLANE1CLKA
625  *    Bit 4  RXLANE0CLKA
626  *    Bit 3  CSUCLKA
627  *    Bit 2  TDCLKA
628  *    Bit 1  RSCLKA
629  *    Bit 0  RDCLKA
630  *----------------------------------------------------------------------------*/
631 #define SUNI1x10GEXP_BITMSK_TIP            0x8000
632 #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA  0x0100
633 #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA    0x0080
634 #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA    0x0040
635 #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA    0x0020
636 #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA    0x0010
637 #define SUNI1x10GEXP_BITMSK_CSUCLKA        0x0008
638 #define SUNI1x10GEXP_BITMSK_TDCLKA         0x0004
639 #define SUNI1x10GEXP_BITMSK_RSCLKA         0x0002
640 #define SUNI1x10GEXP_BITMSK_RDCLKA         0x0001
641 
642 /*----------------------------------------------------------------------------
643  * Register 0x0006: MDIO Command
644  *    Bit 4 MDIO_RDINC
645  *    Bit 3 MDIO_RSTAT
646  *    Bit 2 MDIO_LCTLD
647  *    Bit 1 MDIO_LCTLA
648  *    Bit 0 MDIO_SPRE
649  *----------------------------------------------------------------------------*/
650 #define SUNI1x10GEXP_BITMSK_MDIO_RDINC  0x0010
651 #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT  0x0008
652 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD  0x0004
653 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA  0x0002
654 #define SUNI1x10GEXP_BITMSK_MDIO_SPRE   0x0001
655 
656 /*----------------------------------------------------------------------------
657  * Register 0x0007: MDIO Interrupt Enable
658  *    Bit 0 MDIO_BUSY_EN
659  *----------------------------------------------------------------------------*/
660 #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN  0x0001
661 
662 /*----------------------------------------------------------------------------
663  * Register 0x0008: MDIO Interrupt Status
664  *    Bit 0 MDIO_BUSYI
665  *----------------------------------------------------------------------------*/
666 #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI  0x0001
667 
668 /*----------------------------------------------------------------------------
669  * Register 0x0009: MMD PHY Address
670  *    Bit 12-8 MDIO_DEVADR
671  *    Bit 4-0 MDIO_PRTADR
672  *----------------------------------------------------------------------------*/
673 #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR  0x1F00
674 #define SUNI1x10GEXP_BITOFF_MDIO_DEVADR  8
675 #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR  0x001F
676 #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR  0
677 
678 /*----------------------------------------------------------------------------
679  * Register 0x000C: OAM Interface Control
680  *    Bit 6 MDO_OD_ENB
681  *    Bit 5 MDI_INV
682  *    Bit 4 MDI_SEL
683  *    Bit 3 RXOAMEN
684  *    Bit 2 RXOAMCLKEN
685  *    Bit 1 TXOAMEN
686  *    Bit 0 TXOAMCLKEN
687  *----------------------------------------------------------------------------*/
688 #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB  0x0040
689 #define SUNI1x10GEXP_BITMSK_MDI_INV     0x0020
690 #define SUNI1x10GEXP_BITMSK_MDI_SEL     0x0010
691 #define SUNI1x10GEXP_BITMSK_RXOAMEN     0x0008
692 #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN  0x0004
693 #define SUNI1x10GEXP_BITMSK_TXOAMEN     0x0002
694 #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN  0x0001
695 
696 /*----------------------------------------------------------------------------
697  * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
698  *    Bit 15 TOP_PL4IO_INT
699  *    Bit 14 TOP_IRAM_INT
700  *    Bit 13 TOP_ERAM_INT
701  *    Bit 12 TOP_XAUI_INT
702  *    Bit 11 TOP_MSTAT_INT
703  *    Bit 10 TOP_RXXG_INT
704  *    Bit 9 TOP_TXXG_INT
705  *    Bit 8 TOP_XRF_INT
706  *    Bit 7 TOP_XTEF_INT
707  *    Bit 6 TOP_MDIO_BUSY_INT
708  *    Bit 5 TOP_RXOAM_INT
709  *    Bit 4 TOP_TXOAM_INT
710  *    Bit 3 TOP_IFLX_INT
711  *    Bit 2 TOP_EFLX_INT
712  *    Bit 1 TOP_PL4ODP_INT
713  *    Bit 0 TOP_PL4IDU_INT
714  *----------------------------------------------------------------------------*/
715 #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT      0x8000
716 #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT       0x4000
717 #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT       0x2000
718 #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT       0x1000
719 #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT      0x0800
720 #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT       0x0400
721 #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT       0x0200
722 #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT        0x0100
723 #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT       0x0080
724 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT  0x0040
725 #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT      0x0020
726 #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT      0x0010
727 #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT       0x0008
728 #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT       0x0004
729 #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT     0x0002
730 #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT     0x0001
731 
732 /*----------------------------------------------------------------------------
733  * Register 0x000E:PM3393 Global interrupt enable
734  *    Bit 15 TOP_INTE
735  *----------------------------------------------------------------------------*/
736 #define SUNI1x10GEXP_BITMSK_TOP_INTE  0x8000
737 
738 /*----------------------------------------------------------------------------
739  * Register 0x0010: XTEF Miscellaneous Control
740  *    Bit 7 RF_VAL
741  *    Bit 6 RF_OVERRIDE
742  *    Bit 5 LF_VAL
743  *    Bit 4 LF_OVERRIDE
744  *----------------------------------------------------------------------------*/
745 #define SUNI1x10GEXP_BITMSK_RF_VAL             0x0080
746 #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE        0x0040
747 #define SUNI1x10GEXP_BITMSK_LF_VAL             0x0020
748 #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE        0x0010
749 #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL  0x00F0
750 
751 /*----------------------------------------------------------------------------
752  * Register 0x0011: XRF Miscellaneous Control
753  *    Bit 6-4 EN_IDLE_REP
754  *----------------------------------------------------------------------------*/
755 #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP  0x0070
756 
757 /*----------------------------------------------------------------------------
758  * Register 0x0100: SERDES 3125 Configuration Register 1
759  *    Bit 10 RXEQB_3
760  *    Bit 8  RXEQB_2
761  *    Bit 6  RXEQB_1
762  *    Bit 4  RXEQB_0
763  *----------------------------------------------------------------------------*/
764 #define SUNI1x10GEXP_BITMSK_RXEQB    0x0FF0
765 #define SUNI1x10GEXP_BITOFF_RXEQB_3  10
766 #define SUNI1x10GEXP_BITOFF_RXEQB_2  8
767 #define SUNI1x10GEXP_BITOFF_RXEQB_1  6
768 #define SUNI1x10GEXP_BITOFF_RXEQB_0  4
769 
770 /*----------------------------------------------------------------------------
771  * Register 0x0101: SERDES 3125 Configuration Register 2
772  *    Bit 12 YSEL
773  *    Bit  7 PRE_EMPH_3
774  *    Bit  6 PRE_EMPH_2
775  *    Bit  5 PRE_EMPH_1
776  *    Bit  4 PRE_EMPH_0
777  *----------------------------------------------------------------------------*/
778 #define SUNI1x10GEXP_BITMSK_YSEL        0x1000
779 #define SUNI1x10GEXP_BITMSK_PRE_EMPH    0x00F0
780 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3  0x0080
781 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2  0x0040
782 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1  0x0020
783 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0  0x0010
784 
785 /*----------------------------------------------------------------------------
786  * Register 0x0102: SERDES 3125 Interrupt Enable Register
787  *    Bit 3 LASIE
788  *    Bit 2 SPLL_RAE
789  *    Bit 1 MPLL_RAE
790  *    Bit 0 PLL_LOCKE
791  *----------------------------------------------------------------------------*/
792 #define SUNI1x10GEXP_BITMSK_LASIE      0x0008
793 #define SUNI1x10GEXP_BITMSK_SPLL_RAE   0x0004
794 #define SUNI1x10GEXP_BITMSK_MPLL_RAE   0x0002
795 #define SUNI1x10GEXP_BITMSK_PLL_LOCKE  0x0001
796 
797 /*----------------------------------------------------------------------------
798  * Register 0x0103: SERDES 3125 Interrupt Visibility Register
799  *    Bit 3 LASIV
800  *    Bit 2 SPLL_RAV
801  *    Bit 1 MPLL_RAV
802  *    Bit 0 PLL_LOCKV
803  *----------------------------------------------------------------------------*/
804 #define SUNI1x10GEXP_BITMSK_LASIV      0x0008
805 #define SUNI1x10GEXP_BITMSK_SPLL_RAV   0x0004
806 #define SUNI1x10GEXP_BITMSK_MPLL_RAV   0x0002
807 #define SUNI1x10GEXP_BITMSK_PLL_LOCKV  0x0001
808 
809 /*----------------------------------------------------------------------------
810  * Register 0x0104: SERDES 3125 Interrupt Status Register
811  *    Bit 3 LASII
812  *    Bit 2 SPLL_RAI
813  *    Bit 1 MPLL_RAI
814  *    Bit 0 PLL_LOCKI
815  *----------------------------------------------------------------------------*/
816 #define SUNI1x10GEXP_BITMSK_LASII      0x0008
817 #define SUNI1x10GEXP_BITMSK_SPLL_RAI   0x0004
818 #define SUNI1x10GEXP_BITMSK_MPLL_RAI   0x0002
819 #define SUNI1x10GEXP_BITMSK_PLL_LOCKI  0x0001
820 
821 /*----------------------------------------------------------------------------
822  * Register 0x0107: SERDES 3125 Test Configuration
823  *    Bit 12 DUALTX
824  *    Bit 10 HC_1
825  *    Bit  9 HC_0
826  *----------------------------------------------------------------------------*/
827 #define SUNI1x10GEXP_BITMSK_DUALTX  0x1000
828 #define SUNI1x10GEXP_BITMSK_HC      0x0600
829 #define SUNI1x10GEXP_BITOFF_HC_0    9
830 
831 /*----------------------------------------------------------------------------
832  * Register 0x2040: RXXG Configuration 1
833  *    Bit 15  RXXG_RXEN
834  *    Bit 14  RXXG_ROCF
835  *    Bit 13  RXXG_PAD_STRIP
836  *    Bit 10  RXXG_PUREP
837  *    Bit 9   RXXG_LONGP
838  *    Bit 8   RXXG_PARF
839  *    Bit 7   RXXG_FLCHK
840  *    Bit 5   RXXG_PASS_CTRL
841  *    Bit 3   RXXG_CRC_STRIP
842  *    Bit 2-0 RXXG_MIFG
843  *----------------------------------------------------------------------------*/
844 #define SUNI1x10GEXP_BITMSK_RXXG_RXEN       0x8000
845 #define SUNI1x10GEXP_BITMSK_RXXG_ROCF       0x4000
846 #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP  0x2000
847 #define SUNI1x10GEXP_BITMSK_RXXG_PUREP      0x0400
848 #define SUNI1x10GEXP_BITMSK_RXXG_LONGP      0x0200
849 #define SUNI1x10GEXP_BITMSK_RXXG_PARF       0x0100
850 #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK      0x0080
851 #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL  0x0020
852 #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP  0x0008
853 
854 /*----------------------------------------------------------------------------
855  * Register 0x02041: RXXG Configuration 2
856  *    Bit 7-0 RXXG_HDRSIZE
857  *----------------------------------------------------------------------------*/
858 #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE  0x00FF
859 
860 /*----------------------------------------------------------------------------
861  * Register 0x2042: RXXG Configuration 3
862  *    Bit 15 RXXG_MIN_LERRE
863  *    Bit 14 RXXG_MAX_LERRE
864  *    Bit 12 RXXG_LINE_ERRE
865  *    Bit 10 RXXG_RX_OVRE
866  *    Bit 9  RXXG_ADR_FILTERE
867  *    Bit 8  RXXG_ERR_FILTERE
868  *    Bit 5  RXXG_PRMB_ERRE
869  *----------------------------------------------------------------------------*/
870 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE     0x8000
871 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE     0x4000
872 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE     0x1000
873 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE       0x0400
874 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE   0x0200
875 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE  0x0100
876 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE     0x0020
877 
878 /*----------------------------------------------------------------------------
879  * Register 0x2043: RXXG Interrupt
880  *    Bit 15 RXXG_MIN_LERRI
881  *    Bit 14 RXXG_MAX_LERRI
882  *    Bit 12 RXXG_LINE_ERRI
883  *    Bit 10 RXXG_RX_OVRI
884  *    Bit 9  RXXG_ADR_FILTERI
885  *    Bit 8  RXXG_ERR_FILTERI
886  *    Bit 5  RXXG_PRMB_ERRE
887  *----------------------------------------------------------------------------*/
888 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI    0x8000
889 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI    0x4000
890 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI    0x1000
891 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI      0x0400
892 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI  0x0200
893 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI  0x0100
894 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE    0x0020
895 
896 /*----------------------------------------------------------------------------
897  * Register 0x2049: RXXG Receive FIFO Threshold
898  *    Bit 2-0 RXXG_CUT_THRU
899  *----------------------------------------------------------------------------*/
900 #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU  0x0007
901 #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU  0
902 
903 /*----------------------------------------------------------------------------
904  * Register 0x2062H - 0x2069: RXXG Exact Match VID
905  *    Bit 11-0 RXXG_VID_MATCH
906  *----------------------------------------------------------------------------*/
907 #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH  0x0FFF
908 #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH  0
909 
910 /*----------------------------------------------------------------------------
911  * Register 0x206EH - 0x206F: RXXG Address Filter Control
912  *    Bit 3 RXXG_FORWARD_ENABLE
913  *    Bit 2 RXXG_VLAN_ENABLE
914  *    Bit 1 RXXG_SRC_ADDR
915  *    Bit 0 RXXG_MATCH_ENABLE
916  *----------------------------------------------------------------------------*/
917 #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE  0x0008
918 #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE     0x0004
919 #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR        0x0002
920 #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE    0x0001
921 
922 /*----------------------------------------------------------------------------
923  * Register 0x2070: RXXG Address Filter Control 2
924  *    Bit 1 RXXG_PMODE
925  *    Bit 0 RXXG_MHASH_EN
926  *----------------------------------------------------------------------------*/
927 #define SUNI1x10GEXP_BITMSK_RXXG_PMODE     0x0002
928 #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN  0x0001
929 
930 /*----------------------------------------------------------------------------
931  * Register 0x2081: XRF Control Register 2
932  *    Bit 6   EN_PKT_GEN
933  *    Bit 4-2 PATT
934  *----------------------------------------------------------------------------*/
935 #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN  0x0040
936 #define SUNI1x10GEXP_BITMSK_PATT        0x001C
937 #define SUNI1x10GEXP_BITOFF_PATT        2
938 
939 /*----------------------------------------------------------------------------
940  * Register 0x2088: XRF Interrupt Enable
941  *    Bit 12-9 LANE_HICERE
942  *    Bit 8-5  HS_SD_LANEE
943  *    Bit 4    ALIGN_STATUS_ERRE
944  *    Bit 3-0  LANE_SYNC_STAT_ERRE
945  *----------------------------------------------------------------------------*/
946 #define SUNI1x10GEXP_BITMSK_LANE_HICERE          0x1E00
947 #define SUNI1x10GEXP_BITOFF_LANE_HICERE          9
948 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE          0x01E0
949 #define SUNI1x10GEXP_BITOFF_HS_SD_LANEE          5
950 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE    0x0010
951 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE  0x000F
952 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE  0
953 
954 /*----------------------------------------------------------------------------
955  * Register 0x2089: XRF Interrupt Status
956  *    Bit 12-9 LANE_HICERI
957  *    Bit 8-5  HS_SD_LANEI
958  *    Bit 4    ALIGN_STATUS_ERRI
959  *    Bit 3-0  LANE_SYNC_STAT_ERRI
960  *----------------------------------------------------------------------------*/
961 #define SUNI1x10GEXP_BITMSK_LANE_HICERI          0x1E00
962 #define SUNI1x10GEXP_BITOFF_LANE_HICERI          9
963 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI          0x01E0
964 #define SUNI1x10GEXP_BITOFF_HS_SD_LANEI          5
965 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI    0x0010
966 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI  0x000F
967 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI  0
968 
969 /*----------------------------------------------------------------------------
970  * Register 0x208A: XRF Error Status
971  *    Bit 8-5  HS_SD_LANE
972  *    Bit 4    ALIGN_STATUS_ERR
973  *    Bit 3-0  LANE_SYNC_STAT_ERR
974  *----------------------------------------------------------------------------*/
975 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3          0x0100
976 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2          0x0080
977 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1          0x0040
978 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0          0x0020
979 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR     0x0010
980 #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR  0x0008
981 #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR  0x0004
982 #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR  0x0002
983 #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR  0x0001
984 
985 /*----------------------------------------------------------------------------
986  * Register 0x208B: XRF Diagnostic Interrupt Enable
987  *    Bit 7-4 LANE_OVERRUNE
988  *    Bit 3-0 LANE_UNDERRUNE
989  *----------------------------------------------------------------------------*/
990 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE   0x00F0
991 #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE   4
992 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE  0x000F
993 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE  0
994 
995 /*----------------------------------------------------------------------------
996  * Register 0x208C: XRF Diagnostic Interrupt Status
997  *    Bit 7-4 LANE_OVERRUNI
998  *    Bit 3-0 LANE_UNDERRUNI
999  *----------------------------------------------------------------------------*/
1000 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI   0x00F0
1001 #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI   4
1002 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI  0x000F
1003 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI  0
1004 
1005 /*----------------------------------------------------------------------------
1006  * Register 0x20C0: RXOAM Configuration
1007  *    Bit 15    RXOAM_BUSY
1008  *    Bit 14-12 RXOAM_F2_SEL
1009  *    Bit 10-8  RXOAM_F1_SEL
1010  *    Bit 7-6   RXOAM_FILTER_CTRL
1011  *    Bit 5-0   RXOAM_PX_EN
1012  *----------------------------------------------------------------------------*/
1013 #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY         0x8000
1014 #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL       0x7000
1015 #define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL       12
1016 #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL       0x0700
1017 #define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL       8
1018 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL  0x00C0
1019 #define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL  6
1020 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN        0x003F
1021 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN        0
1022 
1023 /*----------------------------------------------------------------------------
1024  * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1025  *    Bit 15-8 RXOAM_FX_MASK
1026  *    Bit 7-0  RXOAM_FX_VAL
1027  *----------------------------------------------------------------------------*/
1028 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK  0xFF00
1029 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK  8
1030 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL   0x00FF
1031 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl   0
1032 
1033 /*----------------------------------------------------------------------------
1034  * Register 0x20C3: RXOAM Configuration Register 2
1035  *    Bit 13    RXOAM_REC_BYTE_VAL
1036  *    Bit 11-10 RXOAM_BYPASS_MODE
1037  *    Bit 5-0   RXOAM_PX_CLEAR
1038  *----------------------------------------------------------------------------*/
1039 #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL  0x2000
1040 #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE   0x0C00
1041 #define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE   10
1042 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR      0x003F
1043 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR      0
1044 
1045 /*----------------------------------------------------------------------------
1046  * Register 0x20C4: RXOAM HEC Configuration
1047  *    Bit 15-8 RXOAM_COSET
1048  *    Bit 2    RXOAM_HEC_ERR_PKT
1049  *    Bit 0    RXOAM_HEC_EN
1050  *----------------------------------------------------------------------------*/
1051 #define SUNI1x10GEXP_BITMSK_RXOAM_COSET        0xFF00
1052 #define SUNI1x10GEXP_BITOFF_RXOAM_COSET        8
1053 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT  0x0004
1054 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN       0x0001
1055 
1056 /*----------------------------------------------------------------------------
1057  * Register 0x20C7: RXOAM Interrupt Enable
1058  *    Bit 10 RXOAM_FILTER_THRSHE
1059  *    Bit 9  RXOAM_OAM_ERRE
1060  *    Bit 8  RXOAM_HECE_THRSHE
1061  *    Bit 7  RXOAM_SOPE
1062  *    Bit 6  RXOAM_RFE
1063  *    Bit 5  RXOAM_LFE
1064  *    Bit 4  RXOAM_DV_ERRE
1065  *    Bit 3  RXOAM_DATA_INVALIDE
1066  *    Bit 2  RXOAM_FILTER_DROPE
1067  *    Bit 1  RXOAM_HECE
1068  *    Bit 0  RXOAM_OFLE
1069  *----------------------------------------------------------------------------*/
1070 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE  0x0400
1071 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE       0x0200
1072 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE    0x0100
1073 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE           0x0080
1074 #define SUNI1x10GEXP_BITMSK_RXOAM_RFE            0x0040
1075 #define SUNI1x10GEXP_BITMSK_RXOAM_LFE            0x0020
1076 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE        0x0010
1077 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE  0x0008
1078 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE   0x0004
1079 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE           0x0002
1080 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE           0x0001
1081 
1082 /*----------------------------------------------------------------------------
1083  * Register 0x20C8: RXOAM Interrupt Status
1084  *    Bit 10 RXOAM_FILTER_THRSHI
1085  *    Bit 9  RXOAM_OAM_ERRI
1086  *    Bit 8  RXOAM_HECE_THRSHI
1087  *    Bit 7  RXOAM_SOPI
1088  *    Bit 6  RXOAM_RFI
1089  *    Bit 5  RXOAM_LFI
1090  *    Bit 4  RXOAM_DV_ERRI
1091  *    Bit 3  RXOAM_DATA_INVALIDI
1092  *    Bit 2  RXOAM_FILTER_DROPI
1093  *    Bit 1  RXOAM_HECI
1094  *    Bit 0  RXOAM_OFLI
1095  *----------------------------------------------------------------------------*/
1096 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI  0x0400
1097 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI       0x0200
1098 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI    0x0100
1099 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI           0x0080
1100 #define SUNI1x10GEXP_BITMSK_RXOAM_RFI            0x0040
1101 #define SUNI1x10GEXP_BITMSK_RXOAM_LFI            0x0020
1102 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI        0x0010
1103 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI  0x0008
1104 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI   0x0004
1105 #define SUNI1x10GEXP_BITMSK_RXOAM_HECI           0x0002
1106 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI           0x0001
1107 
1108 /*----------------------------------------------------------------------------
1109  * Register 0x20C9: RXOAM Status
1110  *    Bit 10 RXOAM_FILTER_THRSHV
1111  *    Bit 8  RXOAM_HECE_THRSHV
1112  *    Bit 6  RXOAM_RFV
1113  *    Bit 5  RXOAM_LFV
1114  *----------------------------------------------------------------------------*/
1115 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV  0x0400
1116 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV    0x0100
1117 #define SUNI1x10GEXP_BITMSK_RXOAM_RFV            0x0040
1118 #define SUNI1x10GEXP_BITMSK_RXOAM_LFV            0x0020
1119 
1120 /*----------------------------------------------------------------------------
1121  * Register 0x2100: MSTAT Control
1122  *    Bit 2 MSTAT_WRITE
1123  *    Bit 1 MSTAT_CLEAR
1124  *    Bit 0 MSTAT_SNAP
1125  *----------------------------------------------------------------------------*/
1126 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE  0x0004
1127 #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR  0x0002
1128 #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP   0x0001
1129 
1130 /*----------------------------------------------------------------------------
1131  * Register 0x2109: MSTAT Counter Write Address
1132  *    Bit 5-0 MSTAT_WRITE_ADDRESS
1133  *----------------------------------------------------------------------------*/
1134 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1135 #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1136 
1137 /*----------------------------------------------------------------------------
1138  * Register 0x2200: IFLX Global Configuration Register
1139  *    Bit 15   IFLX_IRCU_ENABLE
1140  *    Bit 14   IFLX_IDSWT_ENABLE
1141  *    Bit 13-0 IFLX_IFD_CNT
1142  *----------------------------------------------------------------------------*/
1143 #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE   0x8000
1144 #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE  0x4000
1145 #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT       0x3FFF
1146 #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT       0
1147 
1148 /*----------------------------------------------------------------------------
1149  * Register 0x2209: IFLX FIFO Overflow Enable
1150  *    Bit 0 IFLX_OVFE
1151  *----------------------------------------------------------------------------*/
1152 #define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1153 
1154 /*----------------------------------------------------------------------------
1155  * Register 0x220A: IFLX FIFO Overflow Interrupt
1156  *    Bit 0 IFLX_OVFI
1157  *----------------------------------------------------------------------------*/
1158 #define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1159 
1160 /*----------------------------------------------------------------------------
1161  * Register 0x220D: IFLX Indirect Channel Address
1162  *    Bit 15 IFLX_BUSY
1163  *    Bit 14 IFLX_RWB
1164  *----------------------------------------------------------------------------*/
1165 #define SUNI1x10GEXP_BITMSK_IFLX_BUSY  0x8000
1166 #define SUNI1x10GEXP_BITMSK_IFLX_RWB   0x4000
1167 
1168 /*----------------------------------------------------------------------------
1169  * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1170  *    Bit 9-0 IFLX_LOLIM
1171  *----------------------------------------------------------------------------*/
1172 #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM  0x03FF
1173 #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM  0
1174 
1175 /*----------------------------------------------------------------------------
1176  * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1177  *    Bit 9-0 IFLX_HILIM
1178  *----------------------------------------------------------------------------*/
1179 #define SUNI1x10GEXP_BITMSK_IFLX_HILIM  0x03FF
1180 #define SUNI1x10GEXP_BITOFF_IFLX_HILIM  0
1181 
1182 /*----------------------------------------------------------------------------
1183  * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1184  *    Bit 15   IFLX_FULL
1185  *    Bit 14   IFLX_AFULL
1186  *    Bit 13-0 IFLX_AFTH
1187  *----------------------------------------------------------------------------*/
1188 #define SUNI1x10GEXP_BITMSK_IFLX_FULL   0x8000
1189 #define SUNI1x10GEXP_BITMSK_IFLX_AFULL  0x4000
1190 #define SUNI1x10GEXP_BITMSK_IFLX_AFTH   0x3FFF
1191 #define SUNI1x10GEXP_BITOFF_IFLX_AFTH   0
1192 
1193 /*----------------------------------------------------------------------------
1194  * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1195  *    Bit 15   IFLX_EMPTY
1196  *    Bit 14   IFLX_AEMPTY
1197  *    Bit 13-0 IFLX_AETH
1198  *----------------------------------------------------------------------------*/
1199 #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY   0x8000
1200 #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY  0x4000
1201 #define SUNI1x10GEXP_BITMSK_IFLX_AETH    0x3FFF
1202 #define SUNI1x10GEXP_BITOFF_IFLX_AETH    0
1203 
1204 /*----------------------------------------------------------------------------
1205  * Register 0x2240: PL4MOS Configuration Register
1206  *    Bit 3 PL4MOS_RE_INIT
1207  *    Bit 2 PL4MOS_EN
1208  *    Bit 1 PL4MOS_NO_STATUS
1209  *----------------------------------------------------------------------------*/
1210 #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT          0x0008
1211 #define SUNI1x10GEXP_BITMSK_PL4MOS_EN               0x0004
1212 #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS        0x0002
1213 
1214 /*----------------------------------------------------------------------------
1215  * Register 0x2243: PL4MOS MaxBurst1 Register
1216  *    Bit 11-0 PL4MOS_MAX_BURST1
1217  *----------------------------------------------------------------------------*/
1218 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1  0x0FFF
1219 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1  0
1220 
1221 /*----------------------------------------------------------------------------
1222  * Register 0x2244: PL4MOS MaxBurst2 Register
1223  *    Bit 11-0 PL4MOS_MAX_BURST2
1224  *----------------------------------------------------------------------------*/
1225 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2  0x0FFF
1226 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2  0
1227 
1228 /*----------------------------------------------------------------------------
1229  * Register 0x2245: PL4MOS Transfer Size Register
1230  *    Bit 7-0 PL4MOS_MAX_TRANSFER
1231  *----------------------------------------------------------------------------*/
1232 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER  0x00FF
1233 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER  0
1234 
1235 /*----------------------------------------------------------------------------
1236  * Register 0x2280: PL4ODP Configuration
1237  *    Bit 15-12 PL4ODP_REPEAT_T
1238  *    Bit 8     PL4ODP_SOP_RULE
1239  *    Bit 1     PL4ODP_EN_PORTS
1240  *    Bit 0     PL4ODP_EN_DFWD
1241  *----------------------------------------------------------------------------*/
1242 #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T   0xF000
1243 #define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T   12
1244 #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE   0x0100
1245 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS   0x0002
1246 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD    0x0001
1247 
1248 /*----------------------------------------------------------------------------
1249  * Register 0x2282: PL4ODP Interrupt Mask
1250  *    Bit 0 PL4ODP_OUT_DISE
1251  *----------------------------------------------------------------------------*/
1252 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE     0x0001
1253 
1254 
1255 
1256 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE  0x0080
1257 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE  0x0040
1258 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE    0x0008
1259 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE    0x0004
1260 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE      0x0002
1261 
1262 
1263 /*----------------------------------------------------------------------------
1264  * Register 0x2283: PL4ODP Interrupt
1265  *    Bit 0 PL4ODP_OUT_DISI
1266  *----------------------------------------------------------------------------*/
1267 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI     0x0001
1268 
1269 
1270 
1271 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI  0x0080
1272 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI  0x0040
1273 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI    0x0008
1274 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI    0x0004
1275 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI      0x0002
1276 
1277 /*----------------------------------------------------------------------------
1278  * Register 0x2300:  PL4IO Lock Detect Status
1279  *    Bit 15 PL4IO_OUT_ROOLV
1280  *    Bit 12 PL4IO_IS_ROOLV
1281  *    Bit 11 PL4IO_DIP2_ERRV
1282  *    Bit 8  PL4IO_ID_ROOLV
1283  *    Bit 4  PL4IO_IS_DOOLV
1284  *    Bit 0  PL4IO_ID_DOOLV
1285  *----------------------------------------------------------------------------*/
1286 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV  0x8000
1287 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV   0x1000
1288 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV  0x0800
1289 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV   0x0100
1290 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV   0x0010
1291 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV   0x0001
1292 
1293 /*----------------------------------------------------------------------------
1294  * Register 0x2301:  PL4IO Lock Detect Change
1295  *    Bit 15 PL4IO_OUT_ROOLI
1296  *    Bit 12 PL4IO_IS_ROOLI
1297  *    Bit 11 PL4IO_DIP2_ERRI
1298  *    Bit 8  PL4IO_ID_ROOLI
1299  *    Bit 4  PL4IO_IS_DOOLI
1300  *    Bit 0  PL4IO_ID_DOOLI
1301  *----------------------------------------------------------------------------*/
1302 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI  0x8000
1303 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI   0x1000
1304 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI  0x0800
1305 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI   0x0100
1306 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI   0x0010
1307 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI   0x0001
1308 
1309 /*----------------------------------------------------------------------------
1310  * Register 0x2302:  PL4IO Lock Detect Mask
1311  *    Bit 15 PL4IO_OUT_ROOLE
1312  *    Bit 12 PL4IO_IS_ROOLE
1313  *    Bit 11 PL4IO_DIP2_ERRE
1314  *    Bit 8  PL4IO_ID_ROOLE
1315  *    Bit 4  PL4IO_IS_DOOLE
1316  *    Bit 0  PL4IO_ID_DOOLE
1317  *----------------------------------------------------------------------------*/
1318 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE  0x8000
1319 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE   0x1000
1320 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE  0x0800
1321 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE   0x0100
1322 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE   0x0010
1323 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE   0x0001
1324 
1325 /*----------------------------------------------------------------------------
1326  * Register 0x2303:  PL4IO Lock Detect Limits
1327  *    Bit 15-8 PL4IO_REF_LIMIT
1328  *    Bit 7-0  PL4IO_TRAN_LIMIT
1329  *----------------------------------------------------------------------------*/
1330 #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT   0xFF00
1331 #define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT   8
1332 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT  0x00FF
1333 #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT  0
1334 
1335 /*----------------------------------------------------------------------------
1336  * Register 0x2304:  PL4IO Calendar Repetitions
1337  *    Bit 15-8 PL4IO_IN_MUL
1338  *    Bit 7-0  PL4IO_OUT_MUL
1339  *----------------------------------------------------------------------------*/
1340 #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL   0xFF00
1341 #define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL   8
1342 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL  0x00FF
1343 #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL  0
1344 
1345 /*----------------------------------------------------------------------------
1346  * Register 0x2305:  PL4IO Configuration
1347  *    Bit 15  PL4IO_DIP2_ERR_CHK
1348  *    Bit 11  PL4IO_ODAT_DIS
1349  *    Bit 10  PL4IO_TRAIN_DIS
1350  *    Bit 9   PL4IO_OSTAT_DIS
1351  *    Bit 8   PL4IO_ISTAT_DIS
1352  *    Bit 7   PL4IO_NO_ISTAT
1353  *    Bit 6   PL4IO_STAT_OUTSEL
1354  *    Bit 5   PL4IO_INSEL
1355  *    Bit 4   PL4IO_DLSEL
1356  *    Bit 1-0 PL4IO_OUTSEL
1357  *----------------------------------------------------------------------------*/
1358 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK  0x8000
1359 #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS      0x0800
1360 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS     0x0400
1361 #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS     0x0200
1362 #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS     0x0100
1363 #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT      0x0080
1364 #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL   0x0040
1365 #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL         0x0020
1366 #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL         0x0010
1367 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL        0x0003
1368 #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL        0
1369 
1370 /*----------------------------------------------------------------------------
1371  * Register 0x3040: TXXG Configuration Register 1
1372  *    Bit 15   TXXG_TXEN0
1373  *    Bit 13   TXXG_HOSTPAUSE
1374  *    Bit 12-7 TXXG_IPGT
1375  *    Bit 5    TXXG_32BIT_ALIGN
1376  *    Bit 4    TXXG_CRCEN
1377  *    Bit 3    TXXG_FCTX
1378  *    Bit 2    TXXG_FCRX
1379  *    Bit 1    TXXG_PADEN
1380  *    Bit 0    TXXG_SPRE
1381  *----------------------------------------------------------------------------*/
1382 #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0        0x8000
1383 #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE    0x2000
1384 #define SUNI1x10GEXP_BITMSK_TXXG_IPGT         0x1F80
1385 #define SUNI1x10GEXP_BITOFF_TXXG_IPGT         7
1386 #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN  0x0020
1387 #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN        0x0010
1388 #define SUNI1x10GEXP_BITMSK_TXXG_FCTX         0x0008
1389 #define SUNI1x10GEXP_BITMSK_TXXG_FCRX         0x0004
1390 #define SUNI1x10GEXP_BITMSK_TXXG_PADEN        0x0002
1391 #define SUNI1x10GEXP_BITMSK_TXXG_SPRE         0x0001
1392 
1393 /*----------------------------------------------------------------------------
1394  * Register 0x3041: TXXG Configuration Register 2
1395  *    Bit 7-0   TXXG_HDRSIZE
1396  *----------------------------------------------------------------------------*/
1397 #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE  0x00FF
1398 
1399 /*----------------------------------------------------------------------------
1400  * Register 0x3042: TXXG Configuration Register 3
1401  *    Bit 15 TXXG_FIFO_ERRE
1402  *    Bit 14 TXXG_FIFO_UDRE
1403  *    Bit 13 TXXG_MAX_LERRE
1404  *    Bit 12 TXXG_MIN_LERRE
1405  *    Bit 11 TXXG_XFERE
1406  *----------------------------------------------------------------------------*/
1407 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE  0x8000
1408 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE  0x4000
1409 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE  0x2000
1410 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE  0x1000
1411 #define SUNI1x10GEXP_BITMSK_TXXG_XFERE      0x0800
1412 
1413 /*----------------------------------------------------------------------------
1414  * Register 0x3043: TXXG Interrupt
1415  *    Bit 15 TXXG_FIFO_ERRI
1416  *    Bit 14 TXXG_FIFO_UDRI
1417  *    Bit 13 TXXG_MAX_LERRI
1418  *    Bit 12 TXXG_MIN_LERRI
1419  *    Bit 11 TXXG_XFERI
1420  *----------------------------------------------------------------------------*/
1421 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI  0x8000
1422 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI  0x4000
1423 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI  0x2000
1424 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI  0x1000
1425 #define SUNI1x10GEXP_BITMSK_TXXG_XFERI      0x0800
1426 
1427 /*----------------------------------------------------------------------------
1428  * Register 0x3044: TXXG Status Register
1429  *    Bit 1 TXXG_TXACTIVE
1430  *    Bit 0 TXXG_PAUSED
1431  *----------------------------------------------------------------------------*/
1432 #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE  0x0002
1433 #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED    0x0001
1434 
1435 /*----------------------------------------------------------------------------
1436  * Register 0x3046: TXXG TX_MINFR -  Transmit Min Frame Size Register
1437  *    Bit 7-0 TXXG_TX_MINFR
1438  *----------------------------------------------------------------------------*/
1439 #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR  0x00FF
1440 #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR  0
1441 
1442 /*----------------------------------------------------------------------------
1443  * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1444  *    Bit 7-0 TXXG_FC_PAUSE_QNTM
1445  *----------------------------------------------------------------------------*/
1446 #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM  0x00FF
1447 #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM  0
1448 
1449 /*----------------------------------------------------------------------------
1450  * Register 0x3080: XTEF Control
1451  *    Bit 3-0 XTEF_FORCE_PARITY_ERR
1452  *----------------------------------------------------------------------------*/
1453 #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR  0x000F
1454 #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR  0
1455 
1456 /*----------------------------------------------------------------------------
1457  * Register 0x3084: XTEF Interrupt Event Register
1458  *    Bit 0 XTEF_LOST_SYNCI
1459  *----------------------------------------------------------------------------*/
1460 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI  0x0001
1461 
1462 /*----------------------------------------------------------------------------
1463  * Register 0x3085: XTEF Interrupt Enable Register
1464  *    Bit 0 XTEF_LOST_SYNCE
1465  *----------------------------------------------------------------------------*/
1466 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE  0x0001
1467 
1468 /*----------------------------------------------------------------------------
1469  * Register 0x3086: XTEF Visibility Register
1470  *    Bit 0 XTEF_LOST_SYNCV
1471  *----------------------------------------------------------------------------*/
1472 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV  0x0001
1473 
1474 /*----------------------------------------------------------------------------
1475  * Register 0x30C0: TXOAM OAM Configuration
1476  *    Bit 15   TXOAM_HEC_EN
1477  *    Bit 14   TXOAM_EMPTYCODE_EN
1478  *    Bit 13   TXOAM_FORCE_IDLE
1479  *    Bit 12   TXOAM_IGNORE_IDLE
1480  *    Bit 11-6 TXOAM_PX_OVERWRITE
1481  *    Bit 5-0  TXOAM_PX_SEL
1482  *----------------------------------------------------------------------------*/
1483 #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN        0x8000
1484 #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN  0x4000
1485 #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE    0x2000
1486 #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE   0x1000
1487 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE  0x0FC0
1488 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE  6
1489 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL        0x003F
1490 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL        0
1491 
1492 /*----------------------------------------------------------------------------
1493  * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1494  *    Bit 15   TXOAM_MINIDIS
1495  *    Bit 14   TXOAM_BUSY
1496  *    Bit 13   TXOAM_TRANS_EN
1497  *    Bit 10-0 TXOAM_MINIRATE
1498  *----------------------------------------------------------------------------*/
1499 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS   0x8000
1500 #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY      0x4000
1501 #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN  0x2000
1502 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE  0x07FF
1503 
1504 /*----------------------------------------------------------------------------
1505  * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1506  *    Bit 13-10 TXOAM_FTHRESH
1507  *    Bit 9-6   TXOAM_MINIPOST
1508  *    Bit 5-0   TXOAM_MINIPRE
1509  *----------------------------------------------------------------------------*/
1510 #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH   0x3C00
1511 #define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH   10
1512 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST  0x03C0
1513 #define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST  6
1514 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE   0x003F
1515 
1516 /*----------------------------------------------------------------------------
1517  * Register 0x30C6: TXOAM Interrupt Enable
1518  *    Bit 2 TXOAM_SOP_ERRE
1519  *    Bit 1 TXOAM_OFLE
1520  *    Bit 0 TXOAM_ERRE
1521  *----------------------------------------------------------------------------*/
1522 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE    0x0004
1523 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE        0x0002
1524 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE        0x0001
1525 
1526 /*----------------------------------------------------------------------------
1527  * Register 0x30C7: TXOAM Interrupt Status
1528  *    Bit 2 TXOAM_SOP_ERRI
1529  *    Bit 1 TXOAM_OFLI
1530  *    Bit 0 TXOAM_ERRI
1531  *----------------------------------------------------------------------------*/
1532 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI    0x0004
1533 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI        0x0002
1534 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI        0x0001
1535 
1536 /*----------------------------------------------------------------------------
1537  * Register 0x30CF: TXOAM Coset
1538  *    Bit 7-0 TXOAM_COSET
1539  *----------------------------------------------------------------------------*/
1540 #define SUNI1x10GEXP_BITMSK_TXOAM_COSET  0x00FF
1541 
1542 /*----------------------------------------------------------------------------
1543  * Register 0x3200: EFLX Global Configuration
1544  *    Bit 15 EFLX_ERCU_EN
1545  *    Bit 7  EFLX_EN_EDSWT
1546  *----------------------------------------------------------------------------*/
1547 #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN   0x8000
1548 #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT  0x0080
1549 
1550 /*----------------------------------------------------------------------------
1551  * Register 0x3201: EFLX ERCU Global Status
1552  *    Bit 13 EFLX_OVF_ERR
1553  *----------------------------------------------------------------------------*/
1554 #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR  0x2000
1555 
1556 /*----------------------------------------------------------------------------
1557  * Register 0x3202: EFLX Indirect Channel Address
1558  *    Bit 15 EFLX_BUSY
1559  *    Bit 14 EFLX_RDWRB
1560  *----------------------------------------------------------------------------*/
1561 #define SUNI1x10GEXP_BITMSK_EFLX_BUSY   0x8000
1562 #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB  0x4000
1563 
1564 /*----------------------------------------------------------------------------
1565  * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1566  *----------------------------------------------------------------------------*/
1567 #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM                    0x03FF
1568 #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM                    0
1569 
1570 /*----------------------------------------------------------------------------
1571  * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1572  *----------------------------------------------------------------------------*/
1573 #define SUNI1x10GEXP_BITMSK_EFLX_HILIM                    0x03FF
1574 #define SUNI1x10GEXP_BITOFF_EFLX_HILIM                    0
1575 
1576 /*----------------------------------------------------------------------------
1577  * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1578  *    Bit 15   EFLX_FULL
1579  *    Bit 14   EFLX_AFULL
1580  *    Bit 13-0 EFLX_AFTH
1581  *----------------------------------------------------------------------------*/
1582 #define SUNI1x10GEXP_BITMSK_EFLX_FULL   0x8000
1583 #define SUNI1x10GEXP_BITMSK_EFLX_AFULL  0x4000
1584 #define SUNI1x10GEXP_BITMSK_EFLX_AFTH   0x3FFF
1585 #define SUNI1x10GEXP_BITOFF_EFLX_AFTH   0
1586 
1587 /*----------------------------------------------------------------------------
1588  * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1589  *    Bit 15   EFLX_EMPTY
1590  *    Bit 14   EFLX_AEMPTY
1591  *    Bit 13-0 EFLX_AETH
1592  *----------------------------------------------------------------------------*/
1593 #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY   0x8000
1594 #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY  0x4000
1595 #define SUNI1x10GEXP_BITMSK_EFLX_AETH    0x3FFF
1596 #define SUNI1x10GEXP_BITOFF_EFLX_AETH    0
1597 
1598 /*----------------------------------------------------------------------------
1599  * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1600  *----------------------------------------------------------------------------*/
1601 #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU                 0x3FFF
1602 #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU                 0
1603 
1604 /*----------------------------------------------------------------------------
1605  * Register 0x320C: EFLX FIFO Overflow Error Enable
1606  *    Bit 0 EFLX_OVFE
1607  *----------------------------------------------------------------------------*/
1608 #define SUNI1x10GEXP_BITMSK_EFLX_OVFE  0x0001
1609 
1610 /*----------------------------------------------------------------------------
1611  * Register 0x320D: EFLX FIFO Overflow Error Indication
1612  *    Bit 0 EFLX_OVFI
1613  *----------------------------------------------------------------------------*/
1614 #define SUNI1x10GEXP_BITMSK_EFLX_OVFI  0x0001
1615 
1616 /*----------------------------------------------------------------------------
1617  * Register 0x3210: EFLX Channel Provision
1618  *    Bit 0 EFLX_PROV
1619  *----------------------------------------------------------------------------*/
1620 #define SUNI1x10GEXP_BITMSK_EFLX_PROV  0x0001
1621 
1622 /*----------------------------------------------------------------------------
1623  * Register 0x3280: PL4IDU Configuration
1624  *    Bit 2 PL4IDU_SYNCH_ON_TRAIN
1625  *    Bit 1 PL4IDU_EN_PORTS
1626  *    Bit 0 PL4IDU_EN_DFWD
1627  *----------------------------------------------------------------------------*/
1628 #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN  0x0004
1629 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS        0x0002
1630 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD         0x0001
1631 
1632 /*----------------------------------------------------------------------------
1633  * Register 0x3282: PL4IDU Interrupt Mask
1634  *    Bit 1 PL4IDU_DIP4E
1635  *----------------------------------------------------------------------------*/
1636 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E       0x0002
1637 
1638 /*----------------------------------------------------------------------------
1639  * Register 0x3283: PL4IDU Interrupt
1640  *    Bit 1 PL4IDU_DIP4I
1641  *----------------------------------------------------------------------------*/
1642 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I       0x0002
1643 
1644 
1645 
1646 #endif /* _SUNI1x10GEXP_REGS_H */
1647 
1648