1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_1394_S1394_H 28 #define _SYS_1394_S1394_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * s1394.h 34 * Contains all of the structures used (internally) by the 1394 35 * Software Framework 36 */ 37 38 #include <sys/types.h> 39 #include <sys/dditypes.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/sunndi.h> 43 #include <sys/callb.h> 44 #include <sys/note.h> 45 46 #include <sys/1394/s1394_impl.h> 47 #include <sys/1394/t1394.h> 48 #include <sys/1394/h1394.h> 49 #include <sys/1394/cmd1394.h> 50 #include <sys/1394/ieee1212.h> 51 #include <sys/1394/ieee1394.h> 52 53 #ifdef __cplusplus 54 extern "C" { 55 #endif 56 57 /* SelfID buffer size */ 58 #define S1394_SELFID_BUF_SIZE 8192 59 60 /* Maximum number of allocated commands per target */ 61 #define MAX_NUMBER_ALLOC_CMDS 256 62 63 /* Maximum number of lock retries */ 64 #define MAX_NUMBER_OF_LOCK_RETRIES 256 65 66 #define S1394_INITIAL_STATES 2 67 68 /* Invalid entry in the Speed Map */ 69 #define SPEED_MAP_INVALID 0xFF 70 71 /* Invalid node num */ 72 #define S1394_INVALID_NODE_NUM 0x3F 73 74 /* Node state */ 75 #define S1394_NODE_OFFLINE 1 76 #define S1394_NODE_ONLINE 2 77 78 /* Where are commands inserted onto the pending Q? */ 79 #define S1394_PENDING_Q_FRONT 1 80 #define S1394_PENDING_Q_REAR 2 81 82 /* Number of self-initiated bus resets until HAL fails */ 83 #define NUM_BR_FAIL 5 84 85 /* Reasons for Self-Initiated Bus Reset */ 86 #define NON_CRITICAL 0 87 #define CRITICAL 1 88 89 /* Bus Mgr (IRM) defines */ 90 #define ROOT_HOLDOFF (1 << 0) 91 #define GAP_COUNT (1 << 1) 92 93 /* Root Node has no parents */ 94 #define NO_PARENT -1 95 96 /* Maximum number of Hops between Nodes on the Bus */ 97 #define MAX_HOPS 23 98 99 /* Invalid lo and hi addresses used in s1394_init_addr_space() */ 100 #define ADDR_LO_INVALID 0x0000000000000001 101 #define ADDR_HI_INVALID 0x0000000000000000 102 103 /* Time to delay after CYCLE_TOO_LONG before enabling cycle master */ 104 #define CYCLE_MASTER_TIMER 1000 /* 1 second */ 105 106 /* Size of directory stack used during config rom scan */ 107 #define S1394_DIR_STACK_SIZE 16 108 109 /* 110 * P1394a (Draft 2.x) proposes to disallow a 111 * Config ROM "generation" to be repeated within 112 * a 60 second window. 113 * Because of that, this value should not be set 114 * to any value smaller than 5 seconds without 115 * another method in place to ensure that this 116 * "generation" reuse can not happen. 117 */ 118 119 /* 120 * Time delay (in ms) from Config ROM update to 121 * software-initiated bus reset. 122 */ 123 #define CONFIG_ROM_UPDATE_DELAY 5000 /* 5 seconds */ 124 125 #define S1394_ROOT_TEXT_LEAF_SZ 36 126 #define S1394_ROOT_TEXT_LEAF_QUAD_SZ 9 127 #define S1394_ROOT_TEXT_KEY 0x81 128 129 #define S1394_NODE_UNIQUE_ID_SZ 12 130 #define S1394_NODE_UNIQUE_ID_QUAD_SZ 3 131 #define S1394_NODE_UNIQUE_ID_KEY 0x8D 132 133 #define S1394_UNIT_DIR_SZ 56 134 #define S1394_UNIT_DIR_QUAD_SZ 14 135 #define S1394_UNIT_DIR_KEY 0xD1 136 137 /* The Organizationally Unique Identifier for Sun Microsystems, Inc. */ 138 #define S1394_SUNW_OUI 0x080020 139 140 /* Number of retries in reading the Config ROM */ 141 #define CFGROM_READ_RETRIES 5 142 143 /* Delay time between reads of the Config ROM */ 144 #define CFGROM_READ_DELAY 20000 /* 20ms */ 145 146 /* Error message for serious HBA hardware shutdowns */ 147 #define HALT_ERROR_MESSAGE "%s%d: Unexpected Error: Shutting down HBA -" \ 148 " Hardware disabled until next reboot" 149 150 /* Command Transaction Type */ 151 #define S1394_CMD_READ 0 152 #define S1394_CMD_WRITE 1 153 #define S1394_CMD_LOCK 2 154 155 /* Channel allocations */ 156 #define S1394_CHANNEL_ALLOC_HI 1 157 #define S1394_CHANNEL_ALLOC_LO 0 158 159 /* Maximum number of bus resets allowed in isoch rsrc alloc */ 160 #define S1394_ISOCH_ALLOC_RETRIES 5 161 162 #define ADDR_RESERVED 1 163 164 /* Flags used by the used tree (red-black tree) */ 165 #define BLACK 0 166 #define RED 1 167 #define LEFT 0 168 #define RIGHT 1 169 170 /* Isoch Bandwidth Allocation Units conversion */ 171 #define ISOCH_SPEED_FACTOR_S100 16 172 #define ISOCH_SPEED_FACTOR_S200 8 173 #define ISOCH_SPEED_FACTOR_S400 4 174 175 /* TNF probes */ 176 #define S1394_TNF_SL "1394 s1394 " 177 #define S1394_TNF_SL_ERROR "1394 s1394 error " 178 #define S1394_TNF_SL_STACK "1394 s1394 stacktrace " 179 #define S1394_TNF_SL_ARREQ_STACK "1394 s1394 arreq stacktrace " 180 #define S1394_TNF_SL_ARREQ_ERROR "1394 s1394 arreq error " 181 #define S1394_TNF_SL_ATREQ_STACK "1394 s1394 atreq stacktrace " 182 #define S1394_TNF_SL_ATREQ_ERROR "1394 s1394 atreq error " 183 #define S1394_TNF_SL_ATRESP_STACK "1394 s1394 atresp stacktrace " 184 #define S1394_TNF_SL_ATRESP_ERROR "1394 s1394 atresp error " 185 #define S1394_TNF_SL_ATREQ_ATRESP_STACK "1394 s1394 atreq atresp stacktrace " 186 #define S1394_TNF_SL_ATREQ_ATRESP_ERROR "1394 s1394 atreq atresp error " 187 #define S1394_TNF_SL_BR_STACK "1394 s1394 bus_reset stacktrace " 188 #define S1394_TNF_SL_BR_ERROR "1394 s1394 bus_reset error " 189 #define S1394_TNF_SL_IOCTL_STACK "1394 s1394 ioctl stacktrace " 190 #define S1394_TNF_SL_HOTPLUG_STACK "1394 s1394 hotplug stacktrace " 191 #define S1394_TNF_SL_HOTPLUG_ERROR "1394 s1394 hotplug error " 192 #define S1394_TNF_SL_NX1394_STACK "1394 s1394 nx1394 stacktrace " 193 #define S1394_TNF_SL_CSR_ERROR "1394 s1394 csr error " 194 #define S1394_TNF_SL_CSR_STACK "1394 s1394 csr stacktrace " 195 #define S1394_TNF_SL_BR_CSR_STACK "1394 s1394 bus_reset csr stacktrace " 196 #define S1394_TNF_SL_CFGROM_ERROR "1394 s1394 cfgrom error " 197 #define S1394_TNF_SL_CFGROM_STACK "1394 s1394 cfgrom stacktrace " 198 #define S1394_TNF_SL_ISOCH_ERROR "1394 s1394 isoch error " 199 #define S1394_TNF_SL_ISOCH_STACK "1394 s1394 isoch stacktrace " 200 #define S1394_TNF_SL_NEXUS_ERROR "1394 s1394 nexus error " 201 #define S1394_TNF_SL_NEXUS_STACK "1394 s1394 nexus stacktrace " 202 #define S1394_TNF_SL_FA_STACK "1394 s1394 FA stacktrace " 203 #define S1394_TNF_SL_FA_ERROR "1394 s1394 FA error " 204 #define S1394_TNF_SL_FCP_STACK "1394 s1394 FCP stacktrace " 205 #define S1394_TNF_SL_FCP_ERROR "1394 s1394 FCP error " 206 #define S1394_TNF_SL_CMP_STACK "1394 s1394 CMP stacktrace " 207 #define S1394_TNF_SL_CMP_ERROR "1394 s1394 CMP error " 208 209 /* s1394_hal_state_t */ 210 typedef enum { 211 S1394_HAL_INIT, 212 S1394_HAL_RESET, 213 S1394_HAL_NORMAL, 214 S1394_HAL_DREQ, 215 S1394_HAL_SHUTDOWN 216 } s1394_hal_state_t; 217 218 /* s1394_isoch_cec_type_t */ 219 typedef enum { 220 S1394_SINGLE = 1, 221 S1394_PEER_TO_PEER = 2 222 } s1394_isoch_cec_type_t; 223 224 /* s1394_isoch_cec_state_t */ 225 typedef enum { 226 ISOCH_CEC_FREE = (1 << 0), 227 ISOCH_CEC_JOIN = (1 << 1), 228 ISOCH_CEC_LEAVE = (1 << 2), 229 ISOCH_CEC_SETUP = (1 << 3), 230 ISOCH_CEC_TEARDOWN = (1 << 4), 231 ISOCH_CEC_START = (1 << 5), 232 ISOCH_CEC_STOP = (1 << 6) 233 } s1394_isoch_cec_state_t; 234 235 /* s1394_status_t */ 236 typedef enum { 237 S1394_NOSTATUS = (1 << 0), 238 S1394_LOCK_FAILED = (1 << 1), 239 S1394_CMD_ALLOC_FAILED = (1 << 2), 240 S1394_XFER_FAILED = (1 << 3), 241 S1394_UNKNOWN = (1 << 4), 242 S1394_CMD_INFLIGHT = (1 << 5) 243 } s1394_status_t; 244 245 /* s1394_free_cfgrom_t */ 246 typedef enum { 247 S1394_FREE_CFGROM_BOTH, 248 S1394_FREE_CFGROM_NEW, 249 S1394_FREE_CFGROM_OLD 250 } s1394_free_cfgrom_t; 251 252 typedef struct s1394_node_s s1394_node_t; 253 typedef struct s1394_target_s s1394_target_t; 254 typedef struct s1394_hal_s s1394_hal_t; 255 typedef struct s1394_addr_space_blk_s s1394_addr_space_blk_t; 256 typedef struct s1394_config_rom_s s1394_config_rom_t; 257 typedef struct s1394_kstat_s s1394_kstat_t; 258 typedef struct s1394_isoch_cec_s s1394_isoch_cec_t; 259 typedef struct s1394_isoch_cec_member_s s1394_isoch_cec_member_t; 260 261 /* cfgrom_dir_t */ 262 typedef struct { 263 ushort_t dir_start; 264 ushort_t dir_size; 265 ushort_t dir_next_quad; 266 } cfgrom_dir_t; 267 268 /* s1394_selfid_pkt_t */ 269 typedef struct s1394_selfid_pkt_s { 270 uint32_t spkt_data; 271 uint32_t spkt_inverse; 272 } s1394_selfid_pkt_t; 273 274 /* s1394_node_t */ 275 struct s1394_node_s { 276 s1394_selfid_pkt_t *selfid_packet; 277 s1394_node_t *phy_port[IEEE1394_MAX_NUM_PORTS]; 278 s1394_node_t *old_node; 279 s1394_node_t *cur_node; 280 s1394_target_t *target_list; 281 ushort_t cfgrom_size; /* in quads */ 282 ushort_t cfgrom_valid_size; /* in quads */ 283 uchar_t link_active; 284 uchar_t node_num; 285 uchar_t max_1st; 286 uchar_t max_2nd; 287 uchar_t last_port_checked; 288 uchar_t parent_port; 289 uchar_t is_a_leaf; 290 /* All fields above can be zero'd while initing the topology tree */ 291 uint32_t *cfgrom; 292 #define node_guid_hi cfgrom[3] 293 #define node_guid_lo cfgrom[4] 294 #define node_root_dir cfgrom[5] 295 uint_t node_state; 296 uint_t cfgrom_state; 297 uint_t bus_enum_flags; 298 /* fields dir_stack through expected_dir_quad constitute dir stack */ 299 cfgrom_dir_t dir_stack[S1394_DIR_STACK_SIZE]; 300 ushort_t cur_dir_start; 301 ushort_t cur_dir_size; 302 char dir_stack_top; 303 uchar_t expected_type; 304 uchar_t expected_dir_quad; 305 ushort_t cfgrom_quad_to_read; 306 ushort_t cfgrom_quad_read_cnt; /* if rdg blk */ 307 uchar_t rescan_cnt; 308 uchar_t cfgrom_read_fails; 309 uchar_t cfgrom_read_delay; /* in ms */ 310 }; 311 312 /* defines used during enumeration */ 313 #define NODE_DIR_SIZE(data) ((data) & 0xff) 314 #define NODE_DIR_START(data) (((data) >> 8) & 0xff) 315 #define NODE_DIR_QUAD(data) (((data) >> 16) & 0xff) 316 317 /* defines for link_active */ 318 #define SET_LINK_ACTIVE(n) ((n)->link_active = 1) 319 #define CLEAR_LINK_ACTIVE(n) ((n)->link_active = 0) 320 #define LINK_ACTIVE(n) \ 321 (((n)->link_active == 0) ? B_FALSE : B_TRUE) 322 /* defines for state */ 323 #define S1394_NODE_CONSUMING_PWR 0x00000001 324 #define S1394_NODE_ACTIVE 0x00000010 325 #define S1394_NODE_BUS_PWR_CONSUMER(n) \ 326 ((IEEE1394_SELFID_POWER((n)->selfid_packet) > 0x3) ? B_TRUE : B_FALSE) 327 328 /* defines for cfgrom_state */ 329 #define S1394_CFGROM_NEW_ALLOC 0x00000001 /* fresh alloc */ 330 #define S1394_CFGROM_BIB_READ 0x00000002 /* bus info blocks read */ 331 #define S1394_CFGROM_ALL_READ 0x00000004 /* read all of it */ 332 #define S1394_CFGROM_BLK_READ_OK 0x00000008 /* can be read in blocks */ 333 #define S1394_CFGROM_GEN_CHANGED 0x00000010 /* config rom gen changed */ 334 #define S1394_CFGROM_PARSED 0x00000020 /* rom enumerated */ 335 #define S1394_CFGROM_DIR_STACK_OFF 0x00000040 /* dir stack turned off */ 336 #define S1394_CFGROM_SIZE_IS_CRCSIZE 0x00000080 /* crc size == cfgrom size */ 337 338 #define S1394_CFGROM_READ_MASK (S1394_CFGROM_BIB_READ | S1394_CFGROM_ALL_READ) 339 340 #define S1394_VALID_MASK \ 341 (S1394_CFGROM_READ_MASK | S1394_CFGROM_BLK_READ_OK | \ 342 S1394_CFGROM_GEN_CHANGED | S1394_CFGROM_PARSED) 343 344 #define CLEAR_CFGROM_STATE(n) ((n)->cfgrom_state &= ~S1394_VALID_MASK) 345 #define CFGROM_VALID(n) \ 346 ((((n)->cfgrom_state & S1394_CFGROM_READ_MASK) != 0 && (n)->cfgrom != \ 347 NULL) ? B_TRUE : B_FALSE) 348 349 /* macros for cfgrom_state */ 350 #define SET_CFGROM_NEW_ALLOC(n) ((n)->cfgrom_state |= S1394_CFGROM_NEW_ALLOC) 351 #define CLEAR_CFGROM_NEW_ALLOC(n) ((n)->cfgrom_state &= ~S1394_CFGROM_NEW_ALLOC) 352 #define CFGROM_NEW_ALLOC(n) \ 353 (((n)->cfgrom_state & S1394_CFGROM_NEW_ALLOC) != 0 ? B_TRUE : B_FALSE) 354 355 #define SET_CFGROM_BIB_READ(n) ((n)->cfgrom_state |= S1394_CFGROM_BIB_READ) 356 #define CLEAR_CFGROM_BIB_READ(n) ((n)->cfgrom_state &= ~S1394_CFGROM_BIB_READ) 357 #define CFGROM_BIB_READ(n) \ 358 (((n)->cfgrom_state & S1394_CFGROM_BIB_READ) != 0 ? B_TRUE : B_FALSE) 359 360 #define SET_CFGROM_ALL_READ(n) ((n)->cfgrom_state |= S1394_CFGROM_ALL_READ) 361 #define CLEAR_CFGROM_ALL_READ(n) ((n)->cfgrom_state &= \ 362 ~S1394_CFGROM_ALL_READ) 363 #define CFGROM_ALL_READ(n) \ 364 (((n)->cfgrom_state & S1394_CFGROM_ALL_READ) != 0 ? B_TRUE : B_FALSE) 365 366 #define SET_CFGROM_BLK_READ_OK(n) \ 367 ((n)->cfgrom_state |= S1394_CFGROM_BLK_READ_OK) 368 #define CLEAR_CFGROM_BLK_READ_OK(n) \ 369 ((n)->cfgrom_state &= ~S1394_CFGROM_BLK_READ_OK) 370 #define CFGROM_BLK_READ_OK(n) \ 371 (((n)->cfgrom_state & S1394_CFGROM_BLK_READ_OK) != 0 : B_TRUE : B_FALSE) 372 373 #define SET_CFGROM_GEN_CHANGED(n) \ 374 ((n)->cfgrom_state |= S1394_CFGROM_GEN_CHANGED) 375 #define CLEAR_CFGROM_GEN_CHANGED(n) \ 376 ((n)->cfgrom_state &= ~S1394_CFGROM_GEN_CHANGED) 377 #define CFGROM_GEN_CHANGED(n) \ 378 (((n)->cfgrom_state & S1394_CFGROM_GEN_CHANGED) != 0 ? B_TRUE : B_FALSE) 379 380 #define SET_CFGROM_PARSED(n) ((n)->cfgrom_state |= S1394_CFGROM_PARSED) 381 #define CLEAR_CFGROM_PARSED(n) ((n)->cfgrom_state &= ~S1394_CFGROM_PARSED) 382 #define CFGROM_PARSED(n) \ 383 (((n)->cfgrom_state & S1394_CFGROM_PARSED) != 0 ? B_TRUE : B_FALSE) 384 385 #define SET_CFGROM_DIR_STACK_OFF(n) \ 386 ((n)->cfgrom_state |= S1394_CFGROM_DIR_STACK_OFF) 387 #define CLEAR_CFGROM_DIR_STACK_OFF(n) \ 388 ((n)->cfgrom_state &= ~S1394_CFGROM_DIR_STACK_OFF) 389 #define CFGROM_DIR_STACK_OFF(n) \ 390 (((n)->cfgrom_state & S1394_CFGROM_DIR_STACK_OFF) != 0 ? B_TRUE : \ 391 B_FALSE) 392 393 #define SET_CFGROM_SIZE_IS_CRCSIZE(n) \ 394 ((n)->cfgrom_state |= S1394_CFGROM_SIZE_IS_CRCSIZE) 395 #define CLEAR_CFGROM_SIZE_IS_CRCSIZE(n) \ 396 ((n)->cfgrom_state &= ~S1394_CFGROM_SIZE_IS_CRCSIZE) 397 #define CFGROM_SIZE_IS_CRCSIZE(n) \ 398 (((n)->cfgrom_state & S1394_CFGROM_SIZE_IS_CRCSIZE) != 0 ? B_TRUE : \ 399 B_FALSE) 400 401 /* defines for bus_enum_flags */ 402 #define S1394_NODE_VISITED 0x00000001 403 #define S1394_NODE_MATCHED 0x00000010 404 405 /* macros that set/clear bus_enum_flags */ 406 #define SET_NODE_VISITED(n) ((n)->bus_enum_flags |= S1394_NODE_VISITED) 407 #define CLEAR_NODE_VISITED(n) ((n)->bus_enum_flags &= ~S1394_NODE_VISITED) 408 #define NODE_VISITED(n) \ 409 (((n)->bus_enum_flags & S1394_NODE_VISITED) != 0 ? B_TRUE : B_FALSE) 410 411 #define SET_NODE_MATCHED(n) ((n)->bus_enum_flags |= S1394_NODE_MATCHED) 412 #define CLEAR_NODE_MATCHED(n) ((n)->bus_enum_flags &= ~S1394_NODE_MATCHED) 413 #define NODE_MATCHED(n) \ 414 (((n)->bus_enum_flags & S1394_NODE_MATCHED) != 0 ? B_TRUE : B_FALSE) 415 416 #define SET_NODE_IDENTIFIED(n) ((n)->bus_enum_flags |= S1394_NODE_IDENTIFIED) 417 #define CLEAR_NODE_IDENTIFIED(n) ((n)->bus_enum_flags &= ~S1394_NODE_IDENTIFIED) 418 #define NODE_IDENTIFIED(n) \ 419 (((n)->bus_enum_flags & S1394_NODE_IDENTIFIED) != 0 ? B_TRUE : B_FALSE) 420 421 /* 422 * s1394_fa_type_t - FA types, used as index into target_fa and hal_fa 423 */ 424 typedef enum { 425 S1394_FA_TYPE_FCP_CTL, /* FCP controller */ 426 S1394_FA_TYPE_FCP_TGT, /* FCP target */ 427 S1394_FA_TYPE_CMP_OMPR, /* CMP oMPR */ 428 S1394_FA_TYPE_CMP_IMPR, /* CMP iMPR */ 429 S1394_FA_NTYPES, /* should remain the last field */ 430 S1394_FA_TYPE_CMP = S1394_FA_TYPE_CMP_OMPR /* common CMP type */ 431 } s1394_fa_type_t; 432 433 434 /* 435 * s1394_fa_descr_t - FA type descriptor 436 */ 437 typedef struct s1394_fa_descr_s { 438 uint64_t fd_addr; /* address space */ 439 size_t fd_size; /* address space size */ 440 t1394_addr_enable_t fd_enable; /* access types */ 441 t1394_addr_evts_t fd_evts; /* event callbacks */ 442 uint64_t fd_conv_base; /* address conversion base */ 443 } s1394_fa_descr_t; 444 445 /* 446 * s1394_fcp_target_t - per-target data required for FCP support 447 */ 448 typedef struct s1394_fcp_target_s { 449 t1394_fcp_evts_t fc_evts; 450 } s1394_fcp_target_t; 451 452 /* 453 * s1394_cmp_target_t - per-target data required for CMP support 454 */ 455 typedef struct s1394_cmp_target_s { 456 t1394_cmp_evts_t cm_evts; 457 } s1394_cmp_target_t; 458 459 /* 460 * s1394_fa_target_t - per-target data required for fixed address support 461 */ 462 typedef struct s1394_fa_target_s { 463 s1394_target_t *fat_next; /* next in the list */ 464 /* type-specific data */ 465 union { 466 s1394_fcp_target_t fcp; 467 s1394_cmp_target_t cmp; 468 } fat_u; 469 } s1394_fa_target_t; 470 471 /* s1394_target_t - fields protected by the HAL's target_list_rwlock */ 472 struct s1394_target_s { 473 int target_version; 474 475 dev_info_t *target_dip; 476 477 /* Pointers to the node and HAL on which the target exists */ 478 s1394_node_t *on_node; 479 s1394_hal_t *on_hal; 480 481 s1394_target_t *target_next; 482 s1394_target_t *target_prev; 483 484 /* target_list is a copy of target_list pointer in the node */ 485 s1394_target_t *target_list; 486 s1394_target_t *target_sibling; 487 488 uint_t unit_dir; 489 490 /* The max_payload sizes - max and current conditions */ 491 uint_t dev_max_payload; 492 uint_t current_max_payload; 493 494 /* Number of asynch command target has allocated */ 495 uint_t target_num_cmds; 496 497 /* 498 * Are physical AR requests allowed from this target's node? 499 * This field keeps track of the number of allocated blocks 500 * of physical memory the target has. 501 */ 502 uint_t physical_arreq_enabled; 503 504 uint_t target_state; 505 506 /* FCP controller and target */ 507 s1394_fa_target_t target_fa[S1394_FA_NTYPES]; 508 }; 509 #define S1394_TARG_HP_NODE 0x00000001 /* on a hp node */ 510 #define S1394_TARG_GONE 0x00000002 /* unplugged */ 511 #define S1394_TARG_USING_BUS_PWR 0x00000004 /* consuming pwr now */ 512 #define S1394_TARG_BUS_PWR_CONSUMER 0x00000008 /* power consumer */ 513 #define S1394_TARG_ACTIVE 0x00000010 /* active */ 514 515 /* 516 * s1394_fa_hal_t - per-hal data required for fixed address support 517 */ 518 typedef struct s1394_fa_hal_s { 519 /* 520 * each hal keeps a list of registered fixed address clients 521 */ 522 s1394_target_t *fal_head; 523 s1394_target_t *fal_tail; 524 uint_t fal_gen; /* list generation */ 525 526 s1394_fa_descr_t *fal_descr; /* type descriptor */ 527 s1394_addr_space_blk_t *fal_addr_blk; /* address space block */ 528 } s1394_fa_hal_t; 529 530 /* 531 * s1394_cmp_hal_t - per-hal data required for fixed address support 532 */ 533 typedef struct s1394_cmp_hal_s { 534 /* oMPR */ 535 krwlock_t cmp_ompr_rwlock; 536 uint32_t cmp_ompr_val; 537 /* iMPR */ 538 krwlock_t cmp_impr_rwlock; 539 uint32_t cmp_impr_val; 540 } s1394_cmp_hal_t; 541 542 /* s1394_hal_t */ 543 struct s1394_hal_s { 544 s1394_hal_t *hal_next; 545 s1394_hal_t *hal_prev; 546 547 /* Target list */ 548 s1394_target_t *target_head; 549 s1394_target_t *target_tail; 550 krwlock_t target_list_rwlock; 551 552 /* halinfo structure given at attach time */ 553 h1394_halinfo_t halinfo; 554 555 boolean_t hal_was_suspended; 556 557 /* Bus reset thread */ 558 kthread_t *br_thread; 559 kmutex_t br_thread_mutex; 560 kcondvar_t br_thread_cv; 561 uint_t br_thread_ev_type; 562 uint32_t br_cfgrom_read_gen; 563 kmutex_t br_cmplq_mutex; 564 kcondvar_t br_cmplq_cv; 565 cmd1394_cmd_t *br_cmplq_head; 566 cmd1394_cmd_t *br_cmplq_tail; 567 568 s1394_hal_state_t hal_state; 569 570 /* kstats - kernel statistics for the Services Layer */ 571 s1394_kstat_t *hal_kstats; 572 kstat_t *hal_ksp; 573 574 /* CSR STATE register bits (DREQ and ABDICATE) */ 575 uint_t disable_requests_bit; 576 uint_t abdicate_bus_mgr_bit; 577 578 boolean_t initiated_bus_reset; 579 int initiated_br_reason; 580 uint32_t num_bus_reset_till_fail; 581 582 /* IRM and Bus Manager */ 583 int IRM_node; 584 kmutex_t bus_mgr_node_mutex; 585 kcondvar_t bus_mgr_node_cv; 586 int bus_mgr_node; 587 boolean_t incumbent_bus_mgr; 588 timeout_id_t bus_mgr_timeout_id; 589 timeout_id_t bus_mgr_query_timeout_id; 590 591 /* 1394 Bus stats */ 592 int gap_count; 593 int optimum_gap_count; 594 uint8_t slowest_node_speed; 595 596 /* Local Config ROM */ 597 kmutex_t local_config_rom_mutex; 598 uint32_t *local_config_rom; 599 uint32_t *temp_config_rom_buf; 600 s1394_config_rom_t *root_directory; 601 uint_t free_space; 602 uint_t config_rom_update_amount; 603 boolean_t config_rom_timer_set; 604 timeout_id_t config_rom_timer; 605 606 /* Cycle Master - CYCLE_TOO_LONG timer */ 607 kmutex_t cm_timer_mutex; 608 boolean_t cm_timer_set; 609 timeout_id_t cm_timer; 610 611 /* Incoming (AR) request and 1394 address space */ 612 kmutex_t addr_space_free_mutex; 613 s1394_addr_space_blk_t *addr_space_free_list; 614 kmutex_t addr_space_used_mutex; 615 s1394_addr_space_blk_t *addr_space_used_tree; 616 uint64_t physical_addr_lo; 617 uint64_t physical_addr_hi; 618 uint64_t csr_addr_lo; 619 uint64_t csr_addr_hi; 620 uint64_t normal_addr_lo; 621 uint64_t normal_addr_hi; 622 uint64_t posted_write_addr_lo; 623 uint64_t posted_write_addr_hi; 624 625 /* Outgoing (AT) request queues */ 626 kmutex_t outstanding_q_mutex; 627 cmd1394_cmd_t *outstanding_q_head; 628 cmd1394_cmd_t *outstanding_q_tail; 629 kmutex_t pending_q_mutex; 630 cmd1394_cmd_t *pending_q_head; 631 cmd1394_cmd_t *pending_q_tail; 632 633 /* SelfID buffers */ 634 void *selfid_buf0; 635 void *selfid_buf1; 636 int current_buffer; 637 s1394_selfid_pkt_t *selfid_ptrs[IEEE1394_MAX_NODES]; 638 639 /* Topology trees and local bus stats */ 640 kmutex_t topology_tree_mutex; 641 uint32_t cfgroms_being_read; 642 s1394_node_t *topology_tree; 643 s1394_node_t *old_tree; 644 uint32_t generation_count; 645 ushort_t number_of_nodes; 646 ushort_t node_id; 647 boolean_t topology_tree_valid; 648 boolean_t topology_tree_processed; 649 uint32_t old_generation_count; 650 ushort_t old_number_of_nodes; 651 ushort_t old_node_id; 652 s1394_node_t current_tree[IEEE1394_MAX_NODES]; 653 s1394_node_t last_valid_tree[IEEE1394_MAX_NODES]; 654 boolean_t old_tree_valid; 655 656 /* TOPOLOGY_MAP backing store buffer */ 657 uint32_t *CSR_topology_map; 658 659 /* Speed Map */ 660 uint8_t speed_map[IEEE1394_MAX_NODES][IEEE1394_MAX_NODES]; 661 662 /* Stack, Queue, and Node Number list */ 663 void *hal_stack[IEEE1394_MAX_NODES]; 664 int hal_stack_depth; 665 void *hal_queue[IEEE1394_MAX_NODES]; 666 int hal_queue_front; 667 int hal_queue_back; 668 int hal_node_number_list[IEEE1394_MAX_NODES]; 669 int hal_node_number_list_size; 670 671 /* Isoch CEC list */ 672 kmutex_t isoch_cec_list_mutex; 673 s1394_isoch_cec_t *isoch_cec_list_head; 674 s1394_isoch_cec_t *isoch_cec_list_tail; 675 676 struct kmem_cache *hal_kmem_cachep; 677 678 ndi_event_hdl_t hal_ndi_event_hdl; 679 680 callb_cpr_t hal_cprinfo; 681 682 /* FCP controllers and targets */ 683 s1394_fa_hal_t hal_fa[S1394_FA_NTYPES]; 684 685 /* CMP support */ 686 s1394_cmp_hal_t hal_cmp; 687 }; 688 689 _NOTE(SCHEME_PROTECTS_DATA("No lock needed to start/stop timer", \ 690 s1394_hal_s::cm_timer)) 691 692 /* defines for br_thread_ev_type */ 693 #define BR_THR_CFGROM_SCAN 0x00000001 /* start reading */ 694 #define BR_THR_GO_AWAY 0x00000002 /* clean & exit */ 695 696 /* 697 * FCP command and response address space 698 */ 699 #define IEC61883_FCP_BASE_ADDR 0xFFFFF0000B00 700 #define IEC61883_FCP_CMD_ADDR IEC61883_FCP_BASE_ADDR 701 #define IEC61883_FCP_CMD_SIZE 0x200 702 #define IEC61883_FCP_RESP_ADDR (IEC61883_FCP_CMD_ADDR + IEC61883_FCP_CMD_SIZE) 703 #define IEC61883_FCP_RESP_SIZE 0x200 704 #define IEC61883_FCP_END_ADDR (IEC61883_FCP_RESP_ADDR + IEC61883_FCP_RESP_SIZE) 705 706 /* CMP master plugs */ 707 #define IEC61883_CMP_OMPR_ADDR 0xFFFFF0000900 708 #define IEC61883_CMP_IMPR_ADDR 0xFFFFF0000980 709 #define IEC61883_CMP_OMPR_INIT_VAL 0xBFFFFF00 710 #define IEC61883_CMP_IMPR_INIT_VAL 0x80FFFF00 711 #define IEC61883_CMP_OMPR_LOCK_MASK 0x3FFFFF00 712 #define IEC61883_CMP_IMPR_LOCK_MASK 0x00FFFF00 713 714 /* s1394_addr_space_blk_t */ 715 struct s1394_addr_space_blk_s { 716 /* Pointers and coloring for Red-Black tree */ 717 s1394_addr_space_blk_t *asb_parent; 718 s1394_addr_space_blk_t *asb_left; 719 s1394_addr_space_blk_t *asb_right; 720 uint32_t asb_color; 721 boolean_t free_kmem_bufp; 722 723 /* Addr Blk info - callbacks, permissions, backing store, etc. */ 724 uint64_t addr_lo; 725 uint64_t addr_hi; 726 uint32_t addr_reserved; 727 t1394_addr_enable_t addr_enable; 728 t1394_addr_type_t addr_type; 729 t1394_addr_evts_t addr_events; 730 caddr_t kmem_bufp; 731 void *addr_arg; 732 }; 733 734 /* s1394_config_rom_t */ 735 struct s1394_config_rom_s { 736 boolean_t cfgrom_used; 737 uint32_t cfgrom_addr_lo; 738 uint32_t cfgrom_addr_hi; 739 740 uint_t root_dir_offset; 741 742 s1394_config_rom_t *cfgrom_next; 743 s1394_config_rom_t *cfgrom_prev; 744 }; 745 746 /* s1394_kstat_t */ 747 struct s1394_kstat_s { 748 /* Asynch Receive (AR) requests */ 749 uint_t arreq_quad_rd; 750 uint_t arreq_blk_rd; 751 uint_t arreq_quad_wr; 752 uint_t arreq_blk_wr; 753 uint_t arreq_lock32; 754 uint_t arreq_lock64; 755 756 uint_t arreq_blk_rd_size; 757 uint_t arreq_blk_wr_size; 758 759 uint_t arreq_posted_write_error; 760 761 /* Failure responses to AR requests (sent) */ 762 uint_t arresp_quad_rd_fail; 763 uint_t arresp_blk_rd_fail; 764 uint_t arresp_quad_wr_fail; 765 uint_t arresp_blk_wr_fail; 766 uint_t arresp_lock32_fail; 767 uint_t arresp_lock64_fail; 768 769 /* Asynch Transmit (AT) requests */ 770 uint_t atreq_quad_rd; 771 uint_t atreq_blk_rd; 772 uint_t atreq_quad_wr; 773 uint_t atreq_blk_wr; 774 uint_t atreq_lock32; 775 uint_t atreq_lock64; 776 777 uint_t atreq_blk_rd_size; 778 uint_t atreq_blk_wr_size; 779 780 /* Failure responses to AT requests (received) */ 781 uint_t atresp_quad_rd_fail; 782 uint_t atresp_blk_rd_fail; 783 uint_t atresp_quad_wr_fail; 784 uint_t atresp_blk_wr_fail; 785 uint_t atresp_lock32_fail; 786 uint_t atresp_lock64_fail; 787 788 789 /* Allocate & free requests */ 790 uint_t cmd_alloc; 791 uint_t cmd_alloc_fail; 792 uint_t cmd_free; 793 uint_t addr_phys_alloc; 794 uint_t addr_posted_alloc; 795 uint_t addr_normal_alloc; 796 uint_t addr_csr_alloc; 797 uint_t addr_alloc_fail; 798 uint_t addr_space_free; 799 800 /* Bus reset and miscellaneous */ 801 uint_t bus_reset; 802 uint_t selfid_complete; 803 uint_t selfid_buffer_error; 804 uint_t pending_q_insert; 805 uint64_t guid; 806 }; 807 808 _NOTE(SCHEME_PROTECTS_DATA("Statistics", \ 809 s1394_kstat_s::{arreq_blk_rd arreq_blk_wr arreq_quad_rd arreq_quad_wr \ 810 cmd_free selfid_buffer_error arreq_posted_write_error})) 811 812 /* s1394_isoch_cec_t */ 813 struct s1394_isoch_cec_s { 814 s1394_isoch_cec_t *cec_next; 815 s1394_isoch_cec_t *cec_prev; 816 817 kmutex_t isoch_cec_mutex; 818 819 /* Isoch CEC member list */ 820 s1394_isoch_cec_type_t cec_type; 821 s1394_isoch_cec_member_t *cec_member_list_head; 822 s1394_isoch_cec_member_t *cec_member_list_tail; 823 s1394_isoch_cec_member_t *cec_member_talker; 824 825 /* Properties given in t1394_alloc_isoch_cec() */ 826 t1394_isoch_cec_props_t cec_alloc_props; 827 828 /* Current state of Isoch CEC */ 829 uint_t filter_min_speed; 830 uint_t filter_max_speed; 831 uint_t filter_current_speed; 832 uint64_t filter_channel_mask; 833 uint_t bandwidth; 834 t1394_cec_options_t cec_options; 835 s1394_isoch_cec_state_t state_transitions; 836 boolean_t in_callbacks; 837 boolean_t in_fail_callbacks; 838 kcondvar_t in_callbacks_cv; 839 boolean_t cec_want_wakeup; 840 841 boolean_t realloc_valid; 842 boolean_t realloc_failed; 843 t1394_isoch_rsrc_error_t realloc_fail_reason; 844 uint_t realloc_chnl_num; 845 uint_t realloc_bandwidth; 846 uint_t realloc_speed; 847 }; 848 #define CEC_IN_ANY_CALLBACKS(cec) (((cec)->in_callbacks == B_TRUE) || \ 849 ((cec)->in_fail_callbacks == B_TRUE)) 850 851 #define CEC_TRANSITION_LEGAL(cec, tran) ((cec)->state_transitions & (tran)) 852 #define CEC_SET_LEGAL(cec, tran) ((cec)->state_transitions |= (tran)) 853 #define CEC_SET_ILLEGAL(cec, tran) ((cec)->state_transitions &= ~(tran)) 854 855 856 /* s1394_isoch_cec_member_t */ 857 struct s1394_isoch_cec_member_s { 858 s1394_isoch_cec_member_t *cec_mem_next; 859 s1394_isoch_cec_member_t *cec_mem_prev; 860 861 /* Events for Isoch CEC member - given in t1394_join_isoch_cec() */ 862 t1394_isoch_cec_evts_t isoch_cec_evts; 863 opaque_t isoch_cec_evts_arg; 864 uint64_t req_channel_mask; 865 uint_t req_max_speed; 866 t1394_jii_options_t cec_mem_options; 867 s1394_target_t *cec_mem_target; 868 }; 869 870 /* cmd1394_fa_cmd_priv_t - per-command data for fixed address support */ 871 typedef struct s1394_fa_cmd_priv_s { 872 s1394_fa_type_t type; 873 void (*completion_callback)(); 874 opaque_t callback_arg; 875 } s1394_fa_cmd_priv_t; 876 877 /* s1394_cmd_priv_t */ 878 typedef struct s1394_cmd_priv_s { 879 /* Services Layer private structure for asynch commands */ 880 cmd1394_cmd_t *cmd_priv_next; 881 cmd1394_cmd_t *cmd_priv_prev; 882 883 uint32_t cmd_priv_xfer_type; 884 s1394_target_t *sent_by_target; 885 s1394_hal_t *sent_on_hal; 886 887 int lock_req_step; 888 int temp_num_retries; 889 890 size_t data_remaining; 891 892 kmutex_t blocking_mutex; 893 kcondvar_t blocking_cv; 894 boolean_t blocking_flag; 895 896 boolean_t cmd_in_use; 897 boolean_t posted_write; 898 boolean_t arreq_valid_addr; 899 900 /* 901 * Commands can be extended to support additional functionality. 902 * The only extension at this time is FA (currently used only for FCP). 903 * The downside here is that every command should carry FA overhead 904 * even if the target doesn't use FA. However, alternative approaches 905 * would require separate allocation of FA overhead per command, which 906 * complicates the code and fragments the memory -- seems not worth it 907 * given that FA overhead is just a few bytes and there's a limit of 908 * 256 commands per target. 909 */ 910 int cmd_ext_type; 911 union { 912 s1394_fa_cmd_priv_t fa; 913 } cmd_ext; 914 915 h1394_cmd_priv_t hal_cmd_private; 916 } s1394_cmd_priv_t; 917 #define S1394_GET_CMD_PRIV(cmd) \ 918 ((s1394_cmd_priv_t *)((uchar_t *)(cmd) + sizeof (cmd1394_cmd_t))) 919 920 /* command extension types */ 921 enum { 922 S1394_CMD_EXT_FA = 1 923 }; 924 #define S1394_GET_FA_CMD_PRIV(cmd) (&(S1394_GET_CMD_PRIV(cmd)->cmd_ext.fa)) 925 926 #define S1394_IS_CMD_FCP(s_priv) \ 927 ((s_priv->cmd_ext.fa.type == S1394_FA_TYPE_FCP_CTL) || \ 928 (s_priv->cmd_ext.fa.type == S1394_FA_TYPE_FCP_TGT)) 929 930 _NOTE(SCHEME_PROTECTS_DATA("Unique per command", \ 931 s1394_cmd_priv_s::cmd_priv_xfer_type)) 932 933 934 /* s1394_state_t */ 935 typedef struct s1394_state_s { 936 /* HAL list */ 937 kmutex_t hal_list_mutex; 938 s1394_hal_t *hal_head; 939 s1394_hal_t *hal_tail; 940 } s1394_state_t; 941 942 /* Service Layer Global State Pointer */ 943 extern s1394_state_t *s1394_statep; 944 945 946 /* 1394 Services Layer Internals - 1394 Address Space Routines */ 947 int s1394_request_addr_blk(s1394_hal_t *hal, t1394_alloc_addr_t *addr_allocp); 948 949 int s1394_claim_addr_blk(s1394_hal_t *hal, t1394_alloc_addr_t *addr_allocp); 950 951 int s1394_free_addr_blk(s1394_hal_t *hal, s1394_addr_space_blk_t *blk); 952 953 int s1394_reserve_addr_blk(s1394_hal_t *hal, t1394_alloc_addr_t *addr_allocp); 954 955 int s1394_init_addr_space(s1394_hal_t *hal); 956 957 void s1394_destroy_addr_space(s1394_hal_t *hal); 958 959 void s1394_free_list_insert(s1394_hal_t *hal, s1394_addr_space_blk_t *new_blk); 960 961 s1394_addr_space_blk_t *s1394_used_tree_search(s1394_hal_t *hal, 962 uint64_t addr); 963 964 s1394_addr_space_blk_t *s1394_used_tree_delete(s1394_hal_t *hal, 965 s1394_addr_space_blk_t *z); 966 967 boolean_t s1394_is_posted_write(s1394_hal_t *hal, uint64_t addr); 968 969 boolean_t s1394_is_physical_addr(s1394_hal_t *hal, uint64_t addr); 970 971 boolean_t s1394_is_csr_addr(s1394_hal_t *hal, uint64_t addr); 972 973 boolean_t s1394_is_normal_addr(s1394_hal_t *hal, uint64_t addr); 974 975 /* 1394 Services Layer Internals - Asynchronous Communications Routines */ 976 int s1394_alloc_cmd(s1394_hal_t *hal, uint_t flags, cmd1394_cmd_t **cmdp); 977 978 int s1394_free_cmd(s1394_hal_t *hal, cmd1394_cmd_t **cmdp); 979 980 int s1394_xfer_asynch_command(s1394_hal_t *hal, cmd1394_cmd_t *cmd, int *err); 981 982 int s1394_setup_asynch_command(s1394_hal_t *hal, s1394_target_t *target, 983 cmd1394_cmd_t *cmd, uint32_t xfer_type, int *err); 984 985 void s1394_insert_q_asynch_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 986 987 void s1394_remove_q_asynch_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 988 989 void s1394_atreq_cmd_complete(s1394_hal_t *hal, cmd1394_cmd_t *req, 990 int status); 991 992 void s1394_atresp_cmd_complete(s1394_hal_t *hal, cmd1394_cmd_t *resp, 993 int status); 994 995 int s1394_send_response(s1394_hal_t *hal, cmd1394_cmd_t *resp); 996 997 int s1394_compare_swap(s1394_hal_t *hal, s1394_target_t *target, 998 cmd1394_cmd_t *cmd); 999 1000 int s1394_split_lock_req(s1394_hal_t *hal, s1394_target_t *target, 1001 cmd1394_cmd_t *cmd); 1002 1003 void s1394_pending_q_insert(s1394_hal_t *hal, cmd1394_cmd_t *cmd, uint_t flags); 1004 1005 void s1394_resend_pending_cmds(s1394_hal_t *hal); 1006 1007 /* 1394 Services Layer Internals - Bus Reset Routines */ 1008 int s1394_parse_selfid_buffer(s1394_hal_t *hal, void *selfid_buf_addr, 1009 uint32_t selfid_size); 1010 1011 void s1394_sort_selfids(s1394_hal_t *hal); 1012 1013 void s1394_init_topology_tree(s1394_hal_t *hal, boolean_t copied, 1014 ushort_t number_of_nodes); 1015 1016 int s1394_topology_tree_build(s1394_hal_t *hal); 1017 1018 void s1394_topology_tree_mark_all_unvisited(s1394_hal_t *hal); 1019 1020 void s1394_old_tree_mark_all_unvisited(s1394_hal_t *hal); 1021 1022 void s1394_old_tree_mark_all_unmatched(s1394_hal_t *hal); 1023 1024 void s1394_copy_old_tree(s1394_hal_t *hal); 1025 1026 void s1394_match_tree_nodes(s1394_hal_t *hal); 1027 1028 int s1394_topology_tree_calculate_diameter(s1394_hal_t *hal); 1029 1030 int s1394_gap_count_optimize(int diameter); 1031 1032 int s1394_get_current_gap_count(s1394_hal_t *hal); 1033 1034 void s1394_speed_map_fill(s1394_hal_t *hal); 1035 1036 uint8_t s1394_speed_map_get(s1394_hal_t *hal, uint32_t from_node, 1037 uint32_t to_node); 1038 1039 void s1394_update_speed_map_link_speeds(s1394_hal_t *hal); 1040 1041 int s1394_get_isoch_rsrc_mgr(s1394_hal_t *hal); 1042 1043 void s1394_physical_arreq_setup_all(s1394_hal_t *hal); 1044 1045 void s1394_physical_arreq_set_one(s1394_target_t *target); 1046 1047 void s1394_physical_arreq_clear_one(s1394_target_t *target); 1048 1049 s1394_node_t *s1394_topology_tree_get_root_node(s1394_hal_t *hal); 1050 1051 /* 1394 Services Layer Internals - CSR and Config ROM Routines */ 1052 int s1394_setup_CSR_space(s1394_hal_t *hal); 1053 1054 void s1394_CSR_topology_map_update(s1394_hal_t *hal); 1055 1056 void s1394_CSR_topology_map_disable(s1394_hal_t *hal); 1057 1058 int s1394_init_local_config_rom(s1394_hal_t *hal); 1059 1060 void s1394_destroy_local_config_rom(s1394_hal_t *hal); 1061 1062 int s1394_add_config_rom_entry(s1394_hal_t *hal, uint8_t key, 1063 uint32_t *buffer, uint_t size, void **handle, int *status); 1064 1065 int s1394_remove_config_rom_entry(s1394_hal_t *hal, void **handle, 1066 int *status); 1067 1068 void s1394_update_config_rom_callback(void *arg); 1069 1070 /* In s1394_dev_disc.c */ 1071 void s1394_br_thread(s1394_hal_t *hal); 1072 1073 void s1394_free_cfgrom(s1394_hal_t *hal, s1394_node_t *node, 1074 s1394_free_cfgrom_t options); 1075 1076 void s1394_copy_cfgrom(s1394_node_t *to, s1394_node_t *from); 1077 1078 int s1394_read_rest_of_cfgrom(s1394_hal_t *hal, s1394_node_t *node, 1079 s1394_status_t *status); 1080 1081 void s1394_cfgrom_parse_unit_dir(uint32_t *unit_dir, uint32_t *addr_hi, 1082 uint32_t *addr_lo, uint32_t *size_hi, uint32_t *size_lo); 1083 1084 boolean_t s1394_valid_cfgrom(s1394_hal_t *hal, s1394_node_t *node); 1085 1086 boolean_t s1394_valid_dir(s1394_hal_t *hal, s1394_node_t *node, uint32_t key, 1087 uint32_t *dir); 1088 1089 void s1394_get_maxpayload(s1394_target_t *target, uint_t *dev_max_payload, 1090 uint_t *current_max_payload); 1091 1092 int s1394_lock_tree(s1394_hal_t *hal); 1093 1094 void s1394_unlock_tree(s1394_hal_t *hal); 1095 1096 /* 1394 Services Layer Driver - Hotplug Routines */ 1097 dev_info_t *s1394_devi_find(dev_info_t *pdip, char *name, char *caddr); 1098 1099 int s1394_update_devinfo_tree(s1394_hal_t *hal, s1394_node_t *node); 1100 1101 int s1394_offline_node(s1394_hal_t *hal, s1394_node_t *node); 1102 1103 int s1394_process_topology_tree(s1394_hal_t *hal, int *wait_for_cbs, 1104 uint_t *wait_gen); 1105 1106 int s1394_process_old_tree(s1394_hal_t *hal); 1107 1108 void s1394_add_target_to_node(s1394_target_t *target); 1109 1110 void s1394_remove_target_from_node(s1394_target_t *target); 1111 1112 /* fixed address support */ 1113 int s1394_fa_claim_addr(s1394_hal_t *hal, s1394_fa_type_t type, 1114 s1394_fa_descr_t *descr); 1115 1116 void s1394_fa_free_addr(s1394_hal_t *hal, s1394_fa_type_t type); 1117 1118 void s1394_fa_list_add(s1394_hal_t *hal, s1394_target_t *target, 1119 s1394_fa_type_t type); 1120 1121 int s1394_fa_list_remove(s1394_hal_t *hal, s1394_target_t *target, 1122 s1394_fa_type_t type); 1123 1124 boolean_t s1394_fa_list_is_empty(s1394_hal_t *hal, s1394_fa_type_t type); 1125 1126 uint_t s1394_fa_list_gen(s1394_hal_t *hal, s1394_fa_type_t type); 1127 1128 void s1394_fa_init_cmd(s1394_cmd_priv_t *s_priv, s1394_fa_type_t type); 1129 1130 void s1394_fa_convert_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 1131 1132 void s1394_fa_restore_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 1133 1134 void s1394_fa_check_restore_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 1135 1136 /* FCP */ 1137 int s1394_fcp_hal_init(s1394_hal_t *hal); 1138 1139 int s1394_fcp_register_ctl(s1394_target_t *target, t1394_fcp_evts_t *evts); 1140 1141 int s1394_fcp_register_tgt(s1394_target_t *target, t1394_fcp_evts_t *evts); 1142 1143 int s1394_fcp_unregister_ctl(s1394_target_t *target); 1144 1145 int s1394_fcp_unregister_tgt(s1394_target_t *target); 1146 1147 int s1394_fcp_write_check_cmd(cmd1394_cmd_t *cmd); 1148 1149 /* CMP */ 1150 int s1394_cmp_register(s1394_target_t *target, t1394_cmp_evts_t *evts); 1151 1152 int s1394_cmp_unregister(s1394_target_t *target); 1153 1154 int s1394_cmp_read(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t *valp); 1155 1156 int s1394_cmp_cas(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t arg_val, 1157 uint32_t new_val, uint32_t *old_valp); 1158 1159 /* 1394 Services Layer Internals - Isochronous Communication Routines */ 1160 void s1394_isoch_rsrc_realloc(s1394_hal_t *hal); 1161 1162 void s1394_isoch_rsrc_realloc_notify(s1394_hal_t *hal); 1163 1164 int s1394_channel_alloc(s1394_hal_t *hal, uint32_t channel_mask, 1165 uint_t generation, uint_t flags, uint32_t *old_channels, int *result); 1166 1167 int s1394_channel_free(s1394_hal_t *hal, uint32_t channel_mask, 1168 uint_t generation, uint_t flags, uint32_t *old_channels, int *result); 1169 1170 int s1394_bandwidth_alloc(s1394_hal_t *hal, uint32_t bw_alloc_units, 1171 uint_t generation, int *result); 1172 1173 uint_t s1394_compute_bw_alloc_units(s1394_hal_t *hal, uint_t bandwidth, 1174 uint_t speed); 1175 1176 int s1394_bandwidth_free(s1394_hal_t *hal, uint32_t bw_alloc_units, 1177 uint_t generation, int *result); 1178 1179 void s1394_isoch_cec_list_insert(s1394_hal_t *hal, s1394_isoch_cec_t *cec); 1180 1181 void s1394_isoch_cec_list_remove(s1394_hal_t *hal, s1394_isoch_cec_t *cec); 1182 1183 void s1394_isoch_cec_member_list_insert(s1394_hal_t *hal, 1184 s1394_isoch_cec_t *cec, s1394_isoch_cec_member_t *member); 1185 1186 void s1394_isoch_cec_member_list_remove(s1394_hal_t *hal, 1187 s1394_isoch_cec_t *cec, s1394_isoch_cec_member_t *member); 1188 1189 /* 1394 Services Layer Internals - Miscellaneous Routines */ 1190 void s1394_cleanup_for_detach(s1394_hal_t *hal, uint_t cleanup_level); 1191 1192 void s1394_hal_shutdown(s1394_hal_t *hal, boolean_t disable_hal); 1193 1194 void s1394_initiate_hal_reset(s1394_hal_t *hal, int reason); 1195 1196 boolean_t s1394_on_br_thread(s1394_hal_t *hal); 1197 1198 void s1394_destroy_br_thread(s1394_hal_t *hal); 1199 1200 void s1394_tickle_bus_reset_thread(s1394_hal_t *hal); 1201 1202 void s1394_block_on_asynch_cmd(cmd1394_cmd_t *cmd); 1203 1204 int s1394_HAL_asynch_error(s1394_hal_t *hal, cmd1394_cmd_t *cmd, 1205 s1394_hal_state_t state); 1206 1207 boolean_t s1394_mblk_too_small(cmd1394_cmd_t *cmd); 1208 1209 boolean_t s1394_address_rollover(cmd1394_cmd_t *cmd); 1210 1211 uint_t s1394_stoi(char *p, int len, int base); 1212 1213 uint_t s1394_CRC16(uint_t *d, uint_t crc_length); 1214 1215 uint_t s1394_CRC16_old(uint_t *d, uint_t crc_length); 1216 1217 int s1394_ioctl(s1394_hal_t *hal, int cmd, intptr_t arg, int mode, 1218 cred_t *cred_p, int *rval_p); 1219 1220 void s1394_check_pwr_mgmt(s1394_hal_t *hal, s1394_target_t *target, 1221 boolean_t add); 1222 1223 int s1394_kstat_init(s1394_hal_t *hal); 1224 1225 int s1394_kstat_delete(s1394_hal_t *hal); 1226 1227 int s1394_kstat_update(kstat_t *ksp, int rw); 1228 1229 void s1394_addr_alloc_kstat(s1394_hal_t *hal, uint64_t addr); 1230 1231 void s1394_print_node_info(s1394_hal_t *hal); 1232 1233 s1394_hal_t *s1394_dip_to_hal(dev_info_t *dip); 1234 1235 s1394_target_t *s1394_target_from_dip(s1394_hal_t *hal, dev_info_t *tdip); 1236 s1394_target_t *s1394_target_from_dip_locked(s1394_hal_t *hal, 1237 dev_info_t *tdip); 1238 1239 void s1394_destroy_timers(s1394_hal_t *hal); 1240 1241 void s1394_cycle_too_long_callback(void *arg); 1242 1243 #ifdef __cplusplus 1244 } 1245 #endif 1246 1247 #endif /* _SYS_1394_S1394_H */ 1248