xref: /titanic_41/usr/src/uts/sun4u/sys/sysioerr.h (revision 7c478bd95313f5f23a4c958a745db2134aa03244)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1991-1999 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef	_SYS_SYSIOERR_H
28 #define	_SYS_SYSIOERR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * Sbus error interrupt priorities
38  */
39 #define	SBUS_UE_PIL		12
40 #define	SBUS_CE_PIL		11
41 #define	SBUS_ERR_PIL		12
42 #define	SBUS_THERMAL_PIL	9
43 #define	SBUS_PF_PIL		12
44 #define	SBUS_PM_PIL		12
45 
46 /*
47  * Bits of Sun5 SYSIO Control/Status Register
48  */
49 #define	SYSIO_IMPL	0xF000000000000000ULL /* implementation number */
50 #define	SYSIO_VER	0x0F00000000000000ULL /* revision number */
51 #define	SYSIO_MID	0x00F8000000000000ULL /* UPA mid for SYSIO */
52 #define	SYSIO_INTGN	0x0007C00000000000ULL /* interrupt group number */
53 #define	SYSIO_APCKEN	0x0000000000000008ULL /* address parity check enable */
54 #define	SYSIO_APERR	0x0000000000000004ULL /* system address parity error */
55 #define	SYSIO_IAP	0x0000000000000002ULL /* invert UPA address parity */
56 #define	SYSIO_MODE	0x0000000000000001ULL /* speed of SYSIO clock */
57 
58 /*
59  * Bits of Sun5 SBus ECC Control Register
60  */
61 #define	SECR_ECC_EN	0x8000000000000000ULL /* enable ECC checking */
62 #define	SECR_UE_INTEN	0x4000000000000000ULL /* enable UE_INT interrupt */
63 #define	SECR_CE_INTEN	0x2000000000000000ULL /* enable CE_INT interrupt */
64 
65 /*
66  * Bits of Sun5 SBus UE Asynchronous Fault Status Register
67  */
68 #define	SB_UE_AFSR_P_PIO 0x8000000000000000ULL /* primary UE, PIO access */
69 #define	SB_UE_AFSR_P_DRD 0x4000000000000000ULL /* primary UE, DVMA read */
70 #define	SB_UE_AFSR_P_DWR 0x2000000000000000ULL /* primary UE, DVMA write */
71 #define	SB_UE_AFSR_P	 0xE000000000000000ULL /* primary UE */
72 #define	SB_UE_AFSR_S_PIO 0x1000000000000000ULL /* secondary UE, PIO access */
73 #define	SB_UE_AFSR_S_DRD 0x0800000000000000ULL /* secondary UE, DVMA read */
74 #define	SB_UE_AFSR_S_DWR 0x0400000000000000ULL /* secondary UE, DVMA write */
75 #define	SB_UE_AFSR_S	 0x1C00000000000000ULL /* secondary UE */
76 #define	SB_UE_AFSR_OFF   0x0000E00000000000ULL /* offset of dword w/pri. UE */
77 #define	SB_UE_AFSR_SIZE  0x00001C0000000000ULL /* 2**size of bad transfer */
78 #define	SB_UE_AFSR_MID   0x000003E000000000ULL /* master ID for pri. error */
79 #define	SB_UE_AFSR_ISAP	 0x0000001000000000ULL /* system parity error */
80 
81 /*
82  * Shifts for SBus Sysio UE Asynchronous Fault Status Register
83  */
84 #define	SB_UE_DW_SHIFT		(45)
85 #define	SB_UE_SIZE_SHIFT	(42)
86 #define	SB_UE_MID_SHIFT		(37)
87 
88 /*
89  * Bits of Fusion Desktop SBus UE Asynchronous Fault Address Register
90  */
91 #define	SB_UE_AFAR_PA	0x000001FFFFFFFFFF    /* PA<40:0>: physical address */
92 
93 /*
94  * Bits of Sun5 SBus CE Asynchronous Fault Status Register
95  */
96 #define	SB_CE_AFSR_P_PIO 0x8000000000000000ULL /* primary CE, PIO access */
97 #define	SB_CE_AFSR_P_DRD 0x4000000000000000ULL /* primary CE, DVMA read */
98 #define	SB_CE_AFSR_P_DWR 0x2000000000000000ULL /* primary CE, DVMA write */
99 #define	SB_CE_AFSR_P	 0xE000000000000000ULL /* primary CE */
100 #define	SB_CE_AFSR_S_PIO 0x1000000000000000ULL /* secondary CE, PIO access */
101 #define	SB_CE_AFSR_S_DRD 0x0800000000000000ULL /* secondary CE, DVMA read */
102 #define	SB_CE_AFSR_S_DWR 0x0400000000000000ULL /* secondary CE, DVMA write */
103 #define	SB_CE_AFSR_S	 0x1C00000000000000ULL /* secondary CE */
104 #define	SB_CE_AFSR_SYND  0x00FF000000000000ULL /* CE syndrome bits */
105 #define	SB_CE_AFSR_OFF   0x0000E00000000000ULL /* offset of dword w/pri. CE */
106 #define	SB_CE_AFSR_SIZE	 0x00001C0000000000ULL /* 2**size of failed transfer */
107 #define	SB_CE_AFSR_MID	 0x000003E000000000ULL /* master ID for primary error */
108 
109 /*
110  * Shifts for Sun5 SBus CE Asynchronous Fault Status Register
111  */
112 #define	SB_CE_SYND_SHIFT	(48)
113 #define	SB_CE_OFFSET_SHIFT	(45)
114 #define	SB_CE_SIZE_SHIFT	(42)
115 #define	SB_CE_MID_SHIFT		(37)
116 
117 /*
118  * Bits of Sun5 Fusion Desktop SBus CE Asynchronous Fault Address Register
119  * Note: Fusion Desktop does not support E_SYND2.
120  */
121 #define	SB_CE_E_SYND2	0xFF00000000000000ULL /* syndrome of prim. CE */
122 #define	SB_CE_AFAR_PA	0x000001FFFFFFFFFFULL /* PA<40:0>: physical address */
123 
124 /*
125  * Shift for Sun5 SBus CE Asynchronous Fault Address Register
126  */
127 #define	SB_CE_SYND2_SHIFT	(56)
128 
129 /*
130  * Bits of Sun5 SBus Control and Status Register
131  * See Fusion Desktop System Spec. Table 3-63 for details on slots 13-15
132  */
133 #define	SB_CSR_IMPL	 0xF000000000000000ULL /* host adapter impl. number */
134 #define	SB_CSR_REV	 0x0F00000000000000ULL /* host adapter rev. number */
135 #define	SB_CSR_DPERR_S14 0x0020000000000000ULL /* SBus slot 14 aka Happy Meal */
136 #define	SB_CSR_DPERR_S13 0x0010000000000000ULL /* SBus slot 13 aka APC */
137 #define	SB_CSR_DPERR_S3  0x0008000000000000ULL /* SBus slot 3 DVMA parity err */
138 #define	SB_CSR_DPERR_S2  0x0004000000000000ULL /* SBus slot 2 DVMA parity err */
139 #define	SB_CSR_DPERR_S1  0x0002000000000000ULL /* SBus slot 1 DVMA parity err */
140 #define	SB_CSR_DPERR_S0  0x0001000000000000ULL /* SBus slot 0 DVMA parity err */
141 #define	SB_CSR_PIO_PERRS 0x00007F0000000000ULL /* SBus parity errors */
142 #define	SB_CSR_PPERR_S15 0x0000400000000000ULL /* SBus slot 15 aka slavio */
143 #define	SB_CSR_PPERR_S14 0x0000200000000000ULL /* SBus slot 14 aka Happy Meal */
144 #define	SB_CSR_PPERR_S13 0x0000100000000000ULL /* SBus slot 13 aka APC */
145 #define	SB_CSR_PPERR_S3  0x0000080000000000ULL /* SBus slot 3 PIO parity err */
146 #define	SB_CSR_PPERR_S2  0x0000040000000000ULL /* SBus slot 2 PIO parity err */
147 #define	SB_CSR_PPERR_S1  0x0000020000000000ULL /* SBus slot 1 PIO parity err */
148 #define	SB_CSR_PPERR_S0  0x0000010000000000ULL /* SBus slot 0 PIO parity err */
149 #define	SB_CSR_FAST_SBUS 0x0000000000000400ULL /* shorten PIO access latency */
150 #define	SB_CSR_WAKEUP_EN 0x0000000000000200ULL /* power-management bit */
151 #define	SB_CSR_ERRINT_EN 0x0000000000000100ULL /* enable intr. for SBus errs */
152 #define	SB_CSR_ARBEN_MAC 0x0000000000000020ULL /* enable DVMA for Macio */
153 #define	SB_CSR_ARBEN_APC 0x0000000000000010ULL /* enable DVMA for APC */
154 #define	SB_CSR_ARBEN_SLT 0x000000000000000FULL /* enable DVMA for SBus slots */
155 
156 /*
157  * Shifts for Sun5 SBus Control and Status Register
158  */
159 #define	SB_CSR_IMPL_SHIFT	(60)
160 #define	SB_CSR_REV_SHIFT	(56)
161 #define	SB_CSR_DVMA_PERR_SHIFT	(48)
162 #define	SB_CSR_PIO_PERR_SHIFT	(40)
163 
164 /*
165  * Bits of Sun5 SBus Asynchronous Fault Status Register
166  */
167 #define	SB_AFSR_P_ERRS	0xE000000000000000ULL /* primary errors */
168 #define	SB_AFSR_P_LE	0x8000000000000000ULL /* primary LATE_ERR */
169 #define	SB_AFSR_P_TO	0x4000000000000000ULL /* primary SBus TIMEOUT */
170 #define	SB_AFSR_P_BERR	0x2000000000000000ULL /* primary SBus ERR ack */
171 #define	SB_AFSR_S_ERRS	0x1C00000000000000ULL /* secondary errors */
172 #define	SB_AFSR_S_LE	0x1000000000000000ULL /* secondary LATE_ERR */
173 #define	SB_AFSR_S_TO	0x0800000000000000ULL /* secondary SBus TIMEOUT */
174 #define	SB_AFSR_S_BERR	0x0400000000000000ULL /* secondary SBus ERR ack */
175 #define	SB_AFSR_RD	0x0000800000000000ULL /* primary error was READ op. */
176 #define	SB_AFSR_SIZE	0x00001C0000000000ULL /* 2**size of failed transfer */
177 #define	SB_AFSR_MID	0x000003E000000000ULL /* master ID for primary error */
178 
179 /*
180  * Shifts for Sun5 SBus Asynchronous Fault Status Register
181  */
182 #define	SB_AFSR_SIZE_SHIFT	(42)
183 #define	SB_AFSR_MID_SHIFT	(37)
184 
185 /*
186  * Bits of Fusion Desktop SBus Asynchronous Fault Address Register
187  */
188 #define	SB_AFAR_PA	0x000001FFFFFFFFFFULL /* PA<40:0>: physical address */
189 
190 /*
191  * Function prototypes
192  */
193 extern int
194 sysio_err_init(struct sbus_soft_state *softsp, caddr_t address);
195 extern int
196 sysio_err_resume_init(struct sbus_soft_state *softsp);
197 
198 #ifdef	__cplusplus
199 }
200 #endif
201 
202 #endif	/* _SYS_SYSIOERR_H */
203