xref: /titanic_41/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_queue.h (revision d478d0a82b5f273f7eac89c8df47960d9d22820b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at
9  * http://www.opensource.org/licenses/cddl1.txt.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2004-2012 Emulex. All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_QUEUE_H
28 #define	_EMLXS_QUEUE_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 
35 /* Queue entry defines */
36 
37 /* EQ entries */
38 typedef struct EQE
39 {
40 #ifdef EMLXS_BIG_ENDIAN
41 	uint32_t	CQId: 16;
42 	uint32_t	MinorCode: 12;
43 	uint32_t	MajorCode: 3;
44 	uint32_t	Valid: 1;
45 #endif
46 #ifdef EMLXS_LITTLE_ENDIAN
47 	uint32_t	Valid: 1;
48 	uint32_t	MajorCode: 3;
49 	uint32_t	MinorCode: 12;
50 	uint32_t	CQId: 16;
51 #endif
52 
53 } EQE_t;
54 
55 typedef union
56 {
57 	uint32_t	word;
58 	EQE_t		entry;
59 
60 } EQE_u;
61 
62 #define	EQE_VALID	0x00000001  /* Mask for EQE valid */
63 #define	EQE_CQID	0xFFFF0000  /* Mask for EQE CQID */
64 
65 /* CQ entries */
66 typedef struct CQE_CmplWQ
67 {
68 #ifdef EMLXS_BIG_ENDIAN
69 	uint16_t	RequestTag;	/* Word 0 */
70 	uint8_t		Status;
71 	uint8_t		hw_status;
72 
73 	uint32_t	CmdSpecific;	/* Word 1 */
74 	uint32_t	Parameter;	/* Word 2 */
75 
76 	uint32_t	Valid: 1;	/* Word 3 */
77 	uint32_t	Rsvd1: 2;
78 	uint32_t	XB: 1;
79 	uint32_t	PV: 1;
80 	uint32_t	Priority: 3;
81 	uint32_t	Code: 8;
82 	uint32_t	Rsvd2: 16;
83 #endif
84 #ifdef EMLXS_LITTLE_ENDIAN
85 	uint8_t		hw_status;
86 	uint8_t		Status;
87 	uint16_t	RequestTag;	/* Word 0 */
88 
89 	uint32_t	CmdSpecific;	/* Word 1 */
90 	uint32_t	Parameter;	/* Word 2 */
91 
92 	uint32_t	Rsvd2: 16;
93 	uint32_t	Code: 8;
94 	uint32_t	Priority: 3;
95 	uint32_t	PV: 1;
96 	uint32_t	XB: 1;
97 	uint32_t	Rsvd1: 2;
98 	uint32_t	Valid: 1;	/* Word 3 */
99 #endif
100 } CQE_CmplWQ_t;
101 
102 typedef struct CQE_RelWQ
103 {
104 #ifdef EMLXS_BIG_ENDIAN
105 	uint32_t	Reserved1;	/* Word 0 */
106 	uint32_t	Reserved2;	/* Word 1 */
107 
108 	uint16_t	WQid;		/* Word 2 */
109 	uint16_t	WQindex;
110 
111 	uint32_t	Valid: 1;	/* Word 3 */
112 	uint32_t	Rsvd1: 7;
113 	uint32_t	Code: 8;
114 	uint32_t	Rsvd2: 16;
115 #endif
116 #ifdef EMLXS_LITTLE_ENDIAN
117 	uint32_t	Reserved1;	/* Word 0 */
118 	uint32_t	Reserved2;	/* Word 1 */
119 
120 	uint16_t	WQindex;
121 	uint16_t	WQid;		/* Word 2 */
122 
123 	uint32_t	Rsvd2: 16;
124 	uint32_t	Code: 8;
125 	uint32_t	Rsvd1: 7;
126 	uint32_t	Valid: 1;	/* Word 3 */
127 #endif
128 } CQE_RelWQ_t;
129 
130 typedef struct CQE_UnsolRcv
131 {
132 #ifdef EMLXS_BIG_ENDIAN
133 	uint16_t	RQindex;	/* Word 0 */
134 	uint8_t		Status;
135 	uint8_t		Rsvd1;
136 
137 	uint32_t	Rsvd2;		/* Word 1 */
138 
139 	uint32_t	data_size: 16;	/* Word 2 */
140 	uint32_t	RQid: 10;
141 	uint32_t	FCFId: 6;
142 
143 	uint32_t	Valid: 1;	/* Word 3 */
144 	uint32_t	Rsvd3: 1;
145 	uint32_t	hdr_size: 6;
146 	uint32_t	Code: 8;
147 	uint32_t	eof: 8;
148 	uint32_t	sof: 8;
149 #endif
150 #ifdef EMLXS_LITTLE_ENDIAN
151 	uint8_t		Rsvd1;
152 	uint8_t		Status;
153 	uint16_t	RQindex;	/* Word 0 */
154 
155 	uint32_t	Rsvd2;		/* Word 1 */
156 
157 	uint32_t	FCFId: 6;
158 	uint32_t	RQid: 10;
159 	uint32_t	data_size: 16;	/* Word 2 */
160 
161 	uint32_t	sof: 8;
162 	uint32_t	eof: 8;
163 	uint32_t	Code: 8;
164 	uint32_t	hdr_size: 6;
165 	uint32_t	Rsvd3: 1;
166 	uint32_t	Valid: 1;	/* Word 3 */
167 #endif
168 } CQE_UnsolRcv_t;
169 
170 
171 typedef struct CQE_UnsolRcvV1
172 {
173 #ifdef EMLXS_BIG_ENDIAN
174 	uint16_t	RQindex;	/* Word 0 */
175 	uint8_t		Status;
176 	uint8_t		Rsvd1;
177 
178 	uint32_t	Rsvd2: 26;	/* Word 1 */
179 	uint32_t	FCFId: 6;
180 
181 	uint16_t	data_size;	/* Word 2 */
182 	uint16_t	RQid;
183 
184 	uint32_t	Valid: 1;	/* Word 3 */
185 	uint32_t	Rsvd3: 1;
186 	uint32_t	hdr_size: 6;
187 	uint32_t	Code: 8;
188 	uint32_t	eof: 8;
189 	uint32_t	sof: 8;
190 #endif
191 #ifdef EMLXS_LITTLE_ENDIAN
192 	uint8_t		Rsvd1;
193 	uint8_t		Status;
194 	uint16_t	RQindex;	/* Word 0 */
195 
196 	uint32_t	FCFId: 6;
197 	uint32_t	Rsvd2: 26;	/* Word 1 */
198 
199 	uint16_t	RQid;
200 	uint16_t	data_size;	/* Word 2 */
201 
202 	uint32_t	sof: 8;
203 	uint32_t	eof: 8;
204 	uint32_t	Code: 8;
205 	uint32_t	hdr_size: 6;
206 	uint32_t	Rsvd3: 1;
207 	uint32_t	Valid: 1;	/* Word 3 */
208 #endif
209 } CQE_UnsolRcvV1_t;
210 
211 /* Status defines */
212 #define	RQ_STATUS_SUCCESS		0x10
213 #define	RQ_STATUS_BUFLEN_EXCEEDED	0x11
214 #define	RQ_STATUS_NEED_BUFFER		0x12
215 #define	RQ_STATUS_FRAME_DISCARDED	0x13
216 
217 
218 typedef struct CQE_XRI_Abort
219 {
220 #ifdef EMLXS_BIG_ENDIAN
221 	uint16_t	Rsvd1;		/* Word 0 */
222 	uint8_t		Status;
223 	uint8_t		Rsvd2;
224 
225 	uint32_t	rjtStatus;	/* Word 1 */
226 
227 	uint16_t	RemoteXID;	/* Word 2 */
228 	uint16_t	XRI;
229 
230 	uint32_t	Valid: 1;	/* Word 3 */
231 	uint32_t	IA: 1;
232 	uint32_t	BR: 1;
233 	uint32_t	EO: 1;
234 	uint32_t	Rsvd3: 4;
235 	uint32_t	Code: 8;
236 	uint32_t	Rsvd4: 16;
237 #endif
238 #ifdef EMLXS_LITTLE_ENDIAN
239 	uint8_t		Rsvd2;
240 	uint8_t		Status;
241 	uint16_t	Rsvd1;		/* Word 0 */
242 
243 	uint32_t	rjtStatus;	/* Word 1 */
244 
245 	uint16_t	XRI;
246 	uint16_t	RemoteXID;	/* Word 2 */
247 
248 	uint32_t	Rsvd4: 16;
249 	uint32_t	Code: 8;
250 	uint32_t	Rsvd3: 4;
251 	uint32_t	EO: 1;
252 	uint32_t	BR: 1;
253 	uint32_t	IA: 1;
254 	uint32_t	Valid: 1;	/* Word 3 */
255 #endif
256 } CQE_XRI_Abort_t;
257 
258 
259 
260 #define	CQE_VALID    0x80000000  /* Mask for CQE valid */
261 
262 /* Defines for CQE Codes */
263 #define	CQE_TYPE_WQ_COMPLETION	1
264 #define	CQE_TYPE_RELEASE_WQE	2
265 #define	CQE_TYPE_UNSOL_RCV	4
266 #define	CQE_TYPE_XRI_ABORTED	5
267 #define	CQE_TYPE_UNSOL_RCV_V1	9
268 
269 
270 typedef struct CQE_ASYNC_FCOE
271 {
272 #ifdef EMLXS_BIG_ENDIAN
273 	uint32_t	ref_index;	/* Word 0 */
274 
275 	uint16_t	evt_type;	/* Word 1 */
276 	uint16_t	fcf_count;
277 
278 	uint32_t	event_tag;	/* Word 2 */
279 #endif
280 #ifdef EMLXS_LITTLE_ENDIAN
281 	uint32_t	ref_index;	/* Word 0 */
282 
283 	uint16_t	fcf_count;
284 	uint16_t	evt_type;	/* Word 1 */
285 
286 	uint32_t	event_tag;	/* Word 2 */
287 #endif
288 } CQE_ASYNC_FCOE_t;
289 
290 typedef struct CQE_ASYNC_LINK_STATE
291 {
292 #ifdef EMLXS_BIG_ENDIAN
293 	uint8_t		port_speed;	/* Word 0 */
294 	uint8_t		port_duplex;
295 	uint8_t		link_status;
296 	uint8_t		phys_port;
297 
298 	uint16_t	qos_link_speed;	/* Word 1 */
299 	uint8_t		Rsvd1;
300 	uint8_t		port_fault;
301 
302 	uint32_t	event_tag;	/* Word 2 */
303 #endif
304 #ifdef EMLXS_LITTLE_ENDIAN
305 	uint8_t		phys_port;
306 	uint8_t		link_status;
307 	uint8_t		port_duplex;
308 	uint8_t		port_speed;	/* Word 0 */
309 
310 	uint8_t		port_fault;	/* Word 1 */
311 	uint8_t		Rsvd1;
312 	uint16_t	qos_link_speed;
313 
314 	uint32_t	event_tag;	/* Word 2 */
315 #endif
316 } CQE_ASYNC_LINK_STATE_t;
317 
318 typedef struct CQE_ASYNC_GRP_5_QOS
319 {
320 #ifdef EMLXS_BIG_ENDIAN
321 	uint8_t		Rsvd2;
322 	uint8_t		Rsvd1;
323 	uint8_t		Rsvd0;
324 	uint8_t		phys_port;	/* Word 0 */
325 
326 	uint16_t	qos_link_speed;
327 	uint8_t		Rsvd4;
328 	uint8_t		Rsvd3;		/* Word 1 */
329 
330 	uint32_t	event_tag;	/* Word 2 */
331 #endif
332 #ifdef EMLXS_LITTLE_ENDIAN
333 	uint8_t		phys_port;
334 	uint8_t		Rsvd0;
335 	uint8_t		Rsvd1;
336 	uint8_t		Rsvd2;		/* Word 0 */
337 
338 	uint8_t		Rsvd3;
339 	uint8_t		Rsvd4;
340 	uint16_t	qos_link_speed;	/* Word 1 */
341 
342 	uint32_t	event_tag;	/* Word 2 */
343 #endif
344 } CQE_ASYNC_GRP_5_QOS_t;
345 
346 
347 typedef struct CQE_ASYNC_FC_LINK_ATT
348 {
349 #ifdef EMLXS_BIG_ENDIAN
350 	uint8_t		port_speed;	/* Word 0 */
351 	uint8_t		topology;
352 	uint8_t		att_type;
353 	uint8_t		link_number;
354 
355 	uint16_t	link_speed;	/* Word 1 */
356 	uint8_t		shared_link_status;
357 	uint8_t		port_fault;
358 
359 	uint32_t	event_tag;	/* Word 2 */
360 #endif
361 #ifdef EMLXS_LITTLE_ENDIAN
362 	uint8_t		link_number;
363 	uint8_t		att_type;
364 	uint8_t		topology;
365 	uint8_t		port_speed;	/* Word 0 */
366 
367 	uint8_t		port_fault;
368 	uint8_t		shared_link_status;
369 	uint16_t	link_speed;	/* Word 1 */
370 
371 	uint32_t	event_tag;	/* Word 2 */
372 #endif
373 } CQE_ASYNC_FC_LINK_ATT_t;
374 
375 typedef struct CQE_ASYNC_PORT
376 {
377 	uint8_t		link_status[4];
378 	uint32_t	data_word2;
379 	uint32_t	Rsvd;
380 } CQE_ASYNC_PORT_t;
381 
382 /* topology */
383 #define	TOPOLOGY_UNKNOWN	0
384 #define	TOPOLOGY_NPORT		1
385 #define	TOPOLOGY_LPORT		2
386 #define	TOPOLOGY_INTERNAL_LB	3
387 #define	TOPOLOGY_SERDES_LB	4
388 
389 /* att_type */
390 #define	ATT_TYPE_LINK_UP	1
391 #define	ATT_TYPE_LINK_DOWN	2
392 #define	ATT_TYPE_NO_HARD_ALPA	3
393 
394 /* shared_link_status */
395 #define	SHARED_STATUS_NONE			0
396 #define	SHARED_STATUS_LD_UNUSABLE		1
397 #define	SHARED_STATUS_LD_TRAN_FAULT		2
398 #define	SHARED_STATUS_LD_NO_SIGNAL		3
399 #define	SHARED_STATUS_LD_MGMT_DISABLED		4
400 #define	SHARED_STATUS_LU_FAILED_P2P		5
401 #define	SHARED_STATUS_LU_FAILED_FLOGI_TMO	6
402 #define	SHARED_STATUS_LU_FAILED_NO_FPORT	7
403 #define	SHARED_STATUS_LU_FAILED_NO_NPIV		8
404 #define	SHARED_STATUS_LU_FAILED_FLOGO		9
405 #define	SHARED_STATUS_LU_LOOPBACK		20
406 #define	SHARED_STATUS_LU_NORMAL			40
407 
408 /* port_fault */
409 #define	PORT_FAULT_NONE		0
410 #define	PORT_FAULT_LOCAL	1
411 #define	PORT_FAULT_REMOTE	2
412 
413 typedef struct CQE_ASYNC
414 {
415 	/* Words 0-2 */
416 	union
417 	{
418 		CQE_ASYNC_LINK_STATE_t	link;
419 		CQE_ASYNC_FCOE_t	fcoe;
420 		CQE_ASYNC_GRP_5_QOS_t	qos;
421 		CQE_ASYNC_FC_LINK_ATT_t fc;
422 		CQE_ASYNC_PORT_t 	port;
423 	} un;
424 
425 #ifdef EMLXS_BIG_ENDIAN
426 	uint32_t	valid: 1;
427 	uint32_t	async_evt: 1;
428 	uint32_t	Rsvd2: 6;
429 	uint32_t	event_type: 8;
430 	uint32_t	event_code: 8;
431 	uint32_t	Rsvd3: 8;	/* Word 3 */
432 #endif
433 #ifdef EMLXS_LITTLE_ENDIAN
434 	uint32_t	Rsvd3: 8;
435 	uint32_t	event_code: 8;
436 	uint32_t	event_type: 8;
437 	uint32_t	Rsvd2: 6;
438 	uint32_t	async_evt: 1;
439 	uint32_t	valid: 1;	/* Word 3 */
440 #endif
441 } CQE_ASYNC_t;
442 
443 /* port_speed defines */
444 #define	PHY_1GHZ_LINK			3
445 #define	PHY_10GHZ_LINK			4
446 
447 /* event_code defines */
448 #define	ASYNC_EVENT_CODE_FCOE_LINK_STATE	0x01
449 #define	ASYNC_EVENT_CODE_FCOE_FIP		0x02
450 #define	ASYNC_EVENT_CODE_DCBX			0x03
451 #define	ASYNC_EVENT_CODE_ISCSI			0x04
452 #define	ASYNC_EVENT_CODE_GRP_5			0x05
453 #define	ASYNC_EVENT_CODE_FC_EVENT		0x10
454 #define	ASYNC_EVENT_CODE_PORT			0x11
455 #define	ASYNC_EVENT_CODE_VF			0x12
456 #define	ASYNC_EVENT_CODE_MR			0x13
457 
458 /* FC Event */
459 #define	ASYNC_EVENT_FC_LINK_ATT		1
460 #define	ASYNC_EVENT_FC_SHARED_LINK_ATT	2
461 
462 /* LINK_STATE - link_status defines */
463 #define	ASYNC_EVENT_PHYS_LINK_DOWN	0
464 #define	ASYNC_EVENT_PHYS_LINK_UP	1
465 #define	ASYNC_EVENT_LOGICAL_LINK_DOWN	2
466 #define	ASYNC_EVENT_LOGICAL_LINK_UP	3
467 
468 /* FCOE_FIP - evt_type defines */
469 #define	ASYNC_EVENT_NEW_FCF_DISC	1
470 #define	ASYNC_EVENT_FCF_TABLE_FULL	2
471 #define	ASYNC_EVENT_FCF_DEAD		3
472 #define	ASYNC_EVENT_VIRT_LINK_CLEAR	4
473 #define	ASYNC_EVENT_FCF_MODIFIED	5
474 
475 /* GRP_5 - evt_type defines */
476 #define	ASYNC_EVENT_QOS_SPEED		1
477 
478 /* PORT - evt_type defines */
479 #define	ASYNC_EVENT_MISCONFIG_PORT	9
480 
481 typedef struct CQE_MBOX
482 {
483 #ifdef EMLXS_BIG_ENDIAN
484 	uint16_t	extend_status;	/* Word 0 */
485 	uint16_t	cmpl_status;
486 
487 	uint32_t	tag_low;	/* Word 1 */
488 	uint32_t	tag_high;	/* Word 2 */
489 
490 	uint32_t	valid: 1;	/* Word 3 */
491 	uint32_t	async_evt: 1;
492 	uint32_t	hpi: 1;
493 	uint32_t	completed: 1;
494 	uint32_t	consumed: 1;
495 	uint32_t	Rsvd1: 27;
496 #endif
497 #ifdef EMLXS_LITTLE_ENDIAN
498 	uint16_t	cmpl_status;
499 	uint16_t	extend_status;	/* Word 0 */
500 
501 	uint32_t	tag_low;	/* Word 1 */
502 	uint32_t	tag_high;	/* Word 2 */
503 
504 	uint32_t	Rsvd1: 27;
505 	uint32_t	consumed: 1;
506 	uint32_t	completed: 1;
507 	uint32_t	hpi: 1;
508 	uint32_t	async_evt: 1;
509 	uint32_t	valid: 1;	/* Word 3 */
510 #endif
511 } CQE_MBOX_t;
512 
513 typedef union
514 {
515 	uint32_t	word[4];
516 
517 	/* Group 1 types */
518 	CQE_ASYNC_t	cqAsyncEntry;
519 	CQE_ASYNC_FCOE_t cqAsyncFCOEEntry;
520 	CQE_MBOX_t	cqMboxEntry;
521 
522 	/* Group 2 types */
523 	CQE_CmplWQ_t	cqCmplEntry;
524 	CQE_RelWQ_t	cqRelEntry;
525 	CQE_UnsolRcv_t	cqUnsolRcvEntry;
526 	CQE_UnsolRcvV1_t cqUnsolRcvEntryV1;
527 	CQE_XRI_Abort_t	cqXRIEntry;
528 } CQE_u;
529 
530 /* RQ entries */
531 typedef struct RQE
532 {
533 	uint32_t	AddrHi;
534 	uint32_t	AddrLo;
535 
536 } RQE_t;
537 
538 
539 /* Definitions for WQEs */
540 typedef struct
541 {
542 	/* Word 0 - 2 */
543 	ULP_BDE64	Payload;
544 
545 	/* Word 3 */
546 	uint32_t	PayloadLength;
547 
548 #ifdef EMLXS_BIG_ENDIAN
549 	/* Word 4 */
550 	uint32_t	Rsvd1: 6;
551 	uint32_t	VF: 1;
552 	uint32_t	SP: 1;
553 	uint32_t	LocalId: 24;
554 
555 	/* Word 5 */
556 	uint32_t	Rsvd2:  8;
557 	uint32_t	RemoteId: 24;
558 #endif
559 #ifdef EMLXS_LITTLE_ENDIAN
560 	/* Word 4 */
561 	uint32_t	LocalId: 24;
562 	uint32_t	SP: 1;
563 	uint32_t	VF: 1;
564 	uint32_t	Rsvd1: 6;
565 
566 	/* Word 5 */
567 	uint32_t	RemoteId: 24;
568 	uint32_t	Rsvd2:  8;
569 #endif
570 
571 } ELS_REQ_WQE;
572 
573 typedef struct
574 {
575 	/* Word 0 - 2 */
576 	ULP_BDE64	Payload;
577 
578 	/* Word 3 */
579 	uint32_t	PayloadLength;
580 
581 	/* Word 4 */
582 	uint32_t	Rsvd1;
583 
584 #ifdef EMLXS_BIG_ENDIAN
585 	/* Word 5 */
586 	uint32_t	Rsvd2: 8;
587 	uint32_t	RemoteId: 24;
588 #endif
589 #ifdef EMLXS_LITTLE_ENDIAN
590 	/* Word 5 */
591 	uint32_t	RemoteId: 24;
592 	uint32_t	Rsvd2: 8;
593 #endif
594 
595 } ELS_RSP_WQE;
596 
597 typedef struct
598 {
599 	/* Word 0 - 2 */
600 	ULP_BDE64	Payload;
601 
602 	/* Word 3 */
603 	uint32_t	PayloadLength;
604 
605 	/* Word 4 */
606 	uint32_t	Parameter;
607 
608 #ifdef EMLXS_BIG_ENDIAN
609 	/* Word 5 */
610 	uint32_t	Rctl: 8;
611 	uint32_t	Type: 8;
612 	uint32_t	DFctl: 8;
613 	uint32_t	Rsvd1: 4;
614 	uint32_t	la: 1;
615 	uint32_t	Rsvd2: 3;
616 #endif
617 #ifdef EMLXS_LITTLE_ENDIAN
618 	/* Word 5 */
619 	uint32_t	Rsvd2: 3;
620 	uint32_t	la: 1;
621 	uint32_t	Rsvd1: 4;
622 	uint32_t	DFctl: 8;
623 	uint32_t	Type: 8;
624 	uint32_t	Rctl: 8;
625 #endif
626 
627 } GEN_REQ_WQE;
628 
629 typedef struct
630 {
631 	/* Word 0 - 2 */
632 	ULP_BDE64	Payload;
633 
634 	/* Word 3 */
635 	uint32_t	Rsvd0;
636 
637 	/* Word 4 */
638 	uint32_t	Parameter;
639 
640 #ifdef EMLXS_BIG_ENDIAN
641 	/* Word 5 */
642 	uint32_t	Rctl: 8;
643 	uint32_t	Type: 8;
644 	uint32_t	DFctl: 8;
645 	uint32_t	ls: 1;
646 	uint32_t	xo: 1;
647 	uint32_t	Rsvd1: 2;
648 	uint32_t	ft: 1;
649 	uint32_t	si: 1;
650 	uint32_t	Rsvd2: 2;
651 #endif
652 #ifdef EMLXS_LITTLE_ENDIAN
653 	/* Word 5 */
654 	uint32_t	Rsvd2: 2;
655 	uint32_t	si: 1;
656 	uint32_t	ft: 1;
657 	uint32_t	Rsvd1: 2;
658 	uint32_t	xo: 1;
659 	uint32_t	ls: 1;
660 	uint32_t	DFctl: 8;
661 	uint32_t	Type: 8;
662 	uint32_t	Rctl: 8;
663 #endif
664 
665 } XMIT_SEQ_WQE;
666 
667 typedef struct
668 {
669 	/* Word 0 - 2 */
670 	ULP_BDE64	  Payload;
671 
672 	/* Word 3 */
673 	uint32_t	  PayloadLength;
674 
675 	/* Word 4 */
676 	uint32_t	TotalTransferCount;
677 
678 	/* Word 5 */
679 	uint32_t	Rsvd1;
680 
681 } FCP_WQE;
682 
683 
684 typedef struct
685 {
686 	/* Word 0 - 2 */
687 	uint32_t	Rsvd1[3];
688 
689 #ifdef EMLXS_BIG_ENDIAN
690 	/* Word 3 */
691 	uint32_t	Rsvd2: 16;
692 	uint32_t	Criteria: 8;
693 	uint32_t	Rsvd3: 7;
694 	uint32_t	IA: 1;
695 #endif
696 #ifdef EMLXS_LITTLE_ENDIAN
697 	/* Word 3 */
698 	uint32_t	IA: 1;
699 	uint32_t	Rsvd3: 7;
700 	uint32_t	Criteria: 8;
701 	uint32_t	Rsvd2: 16;
702 #endif
703 
704 	/* Word 4 - 5 */
705 	uint32_t	Rsvd4[2];
706 
707 } ABORT_WQE;
708 
709 #define	ABORT_XRI_TAG	1	/* Abort tag is a XRITag */
710 #define	ABORT_ABT_TAG	2	/* Abort tag is a AbortTag */
711 #define	ABORT_REQ_TAG	3	/* Abort tag is a RequestTag */
712 
713 typedef struct
714 {
715 #ifdef EMLXS_BIG_ENDIAN
716 	/* Word 0 */
717 	uint8_t		Payload0;
718 	uint8_t		Payload1;
719 	uint8_t		Payload2;
720 	uint8_t		Payload3;
721 
722 	/* Word 1 */
723 	uint32_t	OXId: 16;
724 	uint32_t	RXId: 16;
725 
726 	/* Word 2 */
727 	uint32_t	SeqCntLow: 16;
728 	uint32_t	SeqCntHigh: 16;
729 
730 	/* Word 3 */
731 	uint32_t	Rsvd1;
732 
733 	/* Word 4 */
734 	uint32_t	Rsvd2: 8;
735 	uint32_t	LocalId: 24;
736 
737 	/* Word 5 */
738 	uint32_t	XO: 1;
739 	uint32_t	AR: 1;
740 	uint32_t	Rsvd3: 6;
741 	uint32_t	RemoteId: 24;
742 #endif
743 #ifdef EMLXS_LITTLE_ENDIAN
744 	/* Word 0 */
745 	uint8_t		Payload3;
746 	uint8_t		Payload2;
747 	uint8_t		Payload1;
748 	uint8_t		Payload0;
749 
750 	/* Word 1 */
751 	uint32_t	RXId: 16;
752 	uint32_t	OXId: 16;
753 
754 	/* Word 2 */
755 	uint32_t	SeqCntHigh: 16;
756 	uint32_t	SeqCntLow: 16;
757 
758 	/* Word 3 */
759 	uint32_t	Rsvd1;
760 
761 	/* Word 4 */
762 	uint32_t	LocalId: 24;
763 	uint32_t	Rsvd2: 8;
764 
765 	/* Word 5 */
766 	uint32_t	RemoteId: 24;
767 	uint32_t	Rsvd3: 6;
768 	uint32_t	AR: 1;
769 	uint32_t	XO: 1;
770 #endif
771 
772 } BLS_WQE;
773 
774 
775 typedef struct
776 {
777 	/* Word 0 - 4 */
778 	uint32_t	Rsvd1[5];
779 
780 #ifdef EMLXS_BIG_ENDIAN
781 	/* Word 5 */
782 	uint32_t	XO: 1;
783 	uint32_t	Rsvd2: 31;
784 #endif
785 #ifdef EMLXS_LITTLE_ENDIAN
786 	/* Word 5 */
787 	uint32_t	Rsvd2: 31;
788 	uint32_t	XO: 1;
789 #endif
790 
791 } CREATE_XRI_WQE;
792 
793 typedef struct emlxs_wqe
794 {
795 	/* Words 0-5 */
796 	union
797 	{
798 		uint32_t	word[6];	/* Words 0-5: cmd specific */
799 		ELS_REQ_WQE	ElsCmd;		/* ELS command overlay */
800 		GEN_REQ_WQE	GenReq;		/* CT command overlay */
801 		FCP_WQE		FcpCmd;		/* FCP command overlay */
802 		ELS_RSP_WQE	ElsRsp;		/* ELS response overlay */
803 		ABORT_WQE	Abort;		/* Abort overlay */
804 		BLS_WQE		BlsRsp;		/* BLS overlay */
805 		CREATE_XRI_WQE	CreateXri;	/* Create XRI */
806 		XMIT_SEQ_WQE	XmitSeq;	/* Xmit Sequence */
807 	} un;
808 
809 #ifdef EMLXS_BIG_ENDIAN
810 	/* Word 6 */
811 	uint16_t	ContextTag;	/* Context Tag */
812 	uint16_t	XRITag;		/* XRItag */
813 	/* Word 7 */
814 	uint32_t	Timer: 8;	/* TOV */
815 	uint32_t	Rsvd1: 1;
816 	uint32_t	ERP: 1;		/* ERP */
817 	uint32_t	PU: 2;		/* PU */
818 	uint32_t	AR: 1;		/* Auto Response */
819 	uint32_t	Class: 3;	/* COS */
820 	uint32_t	Command: 8;	/* Command Code */
821 	uint32_t	Rsvd0: 1;
822 	uint32_t	BsType: 3;	/* DIF Block Size type */
823 	uint32_t	ContextType: 2;	/* Context Type */
824 	uint32_t	DIF: 2;
825 	/* Word 8 */
826 	uint32_t	AbortTag;	/* Abort Tag */
827 	/* Word 9 */
828 	uint16_t	OXId;		/* OXId on xmitted rsp */
829 	uint16_t	RequestTag;	/* Request Tag */
830 	/* Word 10 */
831 	uint32_t	CCP: 8;		/* CCP */
832 	uint32_t	CCPE: 1;	/* CCPEnabled */
833 	uint32_t	CMD: 1;
834 	uint32_t	XC: 1;		/* Exchange Create */
835 	uint32_t	Rsvd5: 1;
836 	uint32_t	PV: 1;		/* PRIValid */
837 	uint32_t	PRI: 3;		/* PRI */
838 					/* The following 16 bits may be */
839 					/* overwritten by PHWQ */
840 	uint32_t	WQES: 1;	/* WQE specify XBL */
841 	uint32_t	DBDE: 1;	/* Data type for BDE 0 */
842 	uint32_t	IOd: 1;		/* IO direction */
843 	uint32_t	Rsvd4: 1;
844 	uint32_t	XBL: 1;		/* Explicit Buffer List */
845 	uint32_t	Rsvd3: 1;
846 	uint32_t	QOSd: 1;	/* QOS disable */
847 	uint32_t	LenLoc: 2;	/* Length Location */
848 	uint32_t	Rsvd2: 3;
849 	uint32_t	EBDEcnt: 4;	/* Extended BDE cnt */
850 	/* Word 11 */
851 	uint32_t	CQId: 16;	/* CompletionQueueID */
852 	uint32_t	Rsvd8: 8;
853 	uint32_t	WQEC: 1;	/* Request WQE consumed CQE */
854 	uint32_t	ELSId: 3;
855 	uint32_t	CmdType: 4;	/* Command Type */
856 #endif
857 #ifdef EMLXS_LITTLE_ENDIAN
858 	/* Word 6 */
859 	uint16_t	XRITag;		/* XRItag */
860 	uint16_t	ContextTag;	/* Context Tag */
861 	/* Word 7 */
862 	uint32_t	DIF: 2;
863 	uint32_t	ContextType: 2;	/* Context Type */
864 	uint32_t	BsType: 3;	/* DIF Block Size type */
865 	uint32_t	Rsvd0: 1;
866 	uint32_t	Command: 8;	/* Command Code */
867 	uint32_t	Class: 3;	/* COS */
868 	uint32_t	AR: 1;		/* Auto Response */
869 	uint32_t	PU: 2;		/* PU */
870 	uint32_t	ERP: 1;		/* ERP */
871 	uint32_t	Rsvd1: 1;
872 	uint32_t	Timer: 8;	/* TOV */
873 	/* Word 8 */
874 	uint32_t	AbortTag;	/* Abort Tag */
875 	/* Word 9 */
876 	uint16_t	RequestTag;	/* Request Tag */
877 	uint16_t	OXId;		/* OXId on xmitted rsp */
878 	/* Word 10 */
879 					/* The following 16 bits may be */
880 					/* overwritten by PHWQ */
881 	uint32_t	EBDEcnt: 4;	/* Extended BDE cnt */
882 	uint32_t	Rsvd2: 3;
883 	uint32_t	LenLoc: 2;	/* Length Location */
884 	uint32_t	QOSd: 1;	/* QOS disable */
885 	uint32_t	Rsvd3: 1;
886 	uint32_t	XBL: 1;		/* Explicit Buffer List */
887 	uint32_t	Rsvd4: 1;
888 	uint32_t	IOd: 1;		/* IO direction */
889 	uint32_t	DBDE: 1;	/* Data type for BDE 0 */
890 	uint32_t	WQES: 1;	/* WQE specify XBL */
891 	uint32_t	PRI: 3;		/* PRI */
892 	uint32_t	PV: 1;		/* PRIValid */
893 	uint32_t	Rsvd5: 1;
894 	uint32_t	XC: 1;		/* Exchange Create */
895 	uint32_t	CMD: 1;
896 	uint32_t	CCPE: 1;	/* CCPEnabled */
897 	uint32_t	CCP: 8;		/* CCP */
898 	/* Word 11 */
899 	uint32_t	CmdType: 4;	/* Command Type */
900 	uint32_t	ELSId: 3;
901 	uint32_t	WQEC: 1;	/* Request WQE consumed CQE */
902 	uint32_t	Rsvd8: 8;
903 	uint32_t	CQId: 16;	/* CompletionQueueID */
904 #endif
905 
906 	/* Words 12 */
907 	uint32_t	CmdSpecific;	/* Command specific information */
908 
909 	/* Words 13-15 */
910 	ULP_BDE64	FirstData;
911 } emlxs_wqe_t;
912 
913 /* Used if PHWQ is enabled */
914 #ifdef EMLXS_BIG_ENDIAN
915 #define	WQE_PHWQ_WQID(wqe, qid)  *(((uint16_t *)(wqe)) + 21) = \
916 				    ((qid << 1) & 0xfffe);
917 #endif
918 #ifdef EMLXS_LITTLE_ENDIAN
919 #define	WQE_PHWQ_WQID(wqe, qid)  *(((uint16_t *)(wqe)) + 20) = \
920 				    ((qid << 1) & 0xfffe);
921 #endif
922 
923 /* Defines for ContextType */
924 #define	WQE_RPI_CONTEXT		0
925 #define	WQE_VPI_CONTEXT		1
926 #define	WQE_VFI_CONTEXT		2
927 #define	WQE_FCFI_CONTEXT	3
928 
929 /* Defines for CmdType */
930 #define	WQE_TYPE_FCP_DATA_IN	0x00
931 #define	WQE_TYPE_FCP_DATA_OUT	0x01
932 #define	WQE_TYPE_TRECEIVE	0x02
933 #define	WQE_TYPE_TRSP		0x03
934 #define	WQE_TYPE_SRR_RSP	0x06
935 #define	WQE_TYPE_TSEND		0x07
936 #define	WQE_TYPE_GEN		0x08
937 #define	WQE_TYPE_ABORT		0x08
938 #define	WQE_TYPE_ELS		0x0C
939 #define	WQE_TYPE_MASK_FIP	0x01
940 
941 /* Defines for ELSId */
942 #define	WQE_ELSID_PLOGI		0x04
943 #define	WQE_ELSID_FLOGI		0x03
944 #define	WQE_ELSID_FDISC		0x02
945 #define	WQE_ELSID_LOGO		0x01
946 #define	WQE_ELSID_CMD		0x00
947 
948 /* RQB */
949 #define	RQB_HEADER_SIZE		32
950 #define	RQB_DATA_SIZE		2048
951 #define	RQB_COUNT		256
952 
953 #define	EMLXS_NUM_WQ_PAGES	4
954 #define	WQE_SIZE		64
955 
956 #define	EMLXS_NUM_CQ_PAGES_V2	4
957 #define	CQE_SIZE		16
958 
959 #define	EQ_DEPTH		1024
960 #define	CQ_DEPTH		256
961 #define	CQ_DEPTH_V2	((4096/CQE_SIZE) * EMLXS_NUM_CQ_PAGES_V2) /* 1024 */
962 #define	WQ_DEPTH	((4096/WQE_SIZE) * EMLXS_NUM_WQ_PAGES) /* 256 */
963 #define	MQ_DEPTH		16
964 #define	RQ_DEPTH		512 /* Multiple of RQB_COUNT */
965 #define	RQ_DEPTH_EXPONENT	9
966 
967 #define	EMLXS_MAX_WQS_PER_EQ	4
968 
969 
970 /* Principal doorbell register layouts */
971 typedef struct emlxs_rqdb
972 {
973 #ifdef EMLXS_BIG_ENDIAN
974 	uint32_t	Rsvd2:2;
975 	uint32_t	NumPosted:14;	/* Number of entries posted */
976 	uint32_t	Rsvd1:6;
977 	uint32_t	Qid:10;		/* RQ id for posted RQE */
978 #endif /* EMLXS_BIG_ENDIAN */
979 
980 #ifdef EMLXS_LITTLE_ENDIAN
981 	uint32_t	Qid:10;		/* RQ id for posted RQE */
982 	uint32_t	Rsvd1:6;
983 	uint32_t	NumPosted:14;	/* Number of entries posted */
984 	uint32_t	Rsvd2:2;
985 #endif /* EMLXS_LITTLE_ENDIAN */
986 
987 } emlxs_rqdb_t;
988 
989 
990 typedef union emlxs_rqdbu
991 {
992 	uint32_t	word;
993 	emlxs_rqdb_t	db;
994 
995 } emlxs_rqdbu_t;
996 
997 
998 typedef struct emlxs_wqdb
999 {
1000 #ifdef EMLXS_BIG_ENDIAN
1001 	uint32_t	NumPosted:8;	/* Number of entries posted */
1002 	uint32_t	Index:8;	/* Queue index for posted command */
1003 	uint32_t	Rsvd1:6;
1004 	uint32_t	Qid:10;		/* WQ id for posted WQE */
1005 #endif /* EMLXS_BIG_ENDIAN */
1006 
1007 #ifdef EMLXS_LITTLE_ENDIAN
1008 	uint32_t	Qid:10;		/* WQ id for posted WQE */
1009 	uint32_t	Rsvd1:6;
1010 	uint32_t	Index:8;	/* Queue index for posted command */
1011 	uint32_t	NumPosted:8;	/* Number of entries posted */
1012 #endif /* EMLXS_LITTLE_ENDIAN */
1013 
1014 } emlxs_wqdb_t;
1015 
1016 
1017 typedef union emlxs_wqdbu
1018 {
1019 	uint32_t	word;
1020 	emlxs_wqdb_t	db;
1021 
1022 } emlxs_wqdbu_t;
1023 
1024 
1025 typedef struct emlxs_cqdb
1026 {
1027 #ifdef EMLXS_BIG_ENDIAN
1028 	uint32_t	NumPosted:2;	/* Number of entries posted */
1029 	uint32_t	Rearm:1;	/* Rearm CQ */
1030 	uint32_t	NumPopped:13;	/* Number of CQ entries processed */
1031 	uint32_t	Rsvd1:5;
1032 	uint32_t	Event:1;	/* 1 if processed entry is EQE */
1033 				/* 0 if processed entry is CQE */
1034 	uint32_t	Qid:10;		/* CQ id for posted CQE */
1035 #endif /* EMLXS_BIG_ENDIAN */
1036 
1037 #ifdef EMLXS_LITTLE_ENDIAN
1038 	uint32_t	Qid:10;		/* CQ id for posted CQE */
1039 	uint32_t	Event:1;	/* 1 if processed entry is EQE */
1040 				/* 0 if processed entry is CQE */
1041 	uint32_t	Rsvd1:5;
1042 	uint32_t	NumPopped:13;	/* Number of CQ entries processed */
1043 	uint32_t	Rearm:1;	/* Rearm CQ */
1044 	uint32_t	NumPosted:2;	/* Number of entries posted */
1045 #endif /* EMLXS_LITTLE_ENDIAN */
1046 
1047 } emlxs_cqdb_t;
1048 
1049 
1050 typedef union emlxs_cqdbu
1051 {
1052 	uint32_t	word;
1053 	emlxs_cqdb_t	db;
1054 
1055 } emlxs_cqdbu_t;
1056 
1057 typedef struct emlxs_eqdb
1058 {
1059 #ifdef EMLXS_BIG_ENDIAN
1060 	uint32_t	Rsvd2:2;
1061 	uint32_t	Rearm:1;	/* Rearm EQ */
1062 	uint32_t	NumPopped:13;	/* Number of CQ entries processed */
1063 	uint32_t	Rsvd1:5;
1064 	uint32_t	Event:1;	/* True iff processed entry is EQE */
1065 	uint32_t	Clear:1;	/* clears EQ interrupt when set */
1066 	uint32_t	Qid:9;		/* EQ id for posted EQE */
1067 #endif /* EMLXS_BIG_ENDIAN */
1068 
1069 #ifdef EMLXS_LITTLE_ENDIAN
1070 	uint32_t	Qid:9;		/* EQ id for posted EQE */
1071 	uint32_t	Clear:1;	/* clears EQ interrupt when set */
1072 	uint32_t	Event:1;	/* True iff processed entry is EQE */
1073 	uint32_t	Rsvd1:5;
1074 	uint32_t	NumPopped:13;	/* Number of CQ entries processed */
1075 	uint32_t	Rearm:1;	/* Rearm EQ */
1076 	uint32_t	Rsvd2:2;
1077 #endif /* EMLXS_LITTLE_ENDIAN */
1078 
1079 } emlxs_eqdb_t;
1080 
1081 
1082 typedef union emlxs_eqdbu
1083 {
1084 	uint32_t	word;
1085 	emlxs_eqdb_t	db;
1086 
1087 } emlxs_eqdbu_t;
1088 
1089 
1090 typedef struct emlxs_mqdb
1091 {
1092 #ifdef EMLXS_BIG_ENDIAN
1093 	uint32_t	Rsvd2:2;
1094 	uint32_t	NumPosted:14;	/* Number of entries posted */
1095 	uint32_t	Rsvd1:5;
1096 	uint32_t	Qid:11;		/* MQ id for posted MQE */
1097 #endif /* EMLXS_BIG_ENDIAN */
1098 
1099 #ifdef EMLXS_LITTLE_ENDIAN
1100 	uint32_t	Qid:11;		/* MQ id for posted MQE */
1101 	uint32_t	Rsvd1:5;
1102 	uint32_t	NumPosted:14;	/* Number of entries posted */
1103 	uint32_t	Rsvd2:2;
1104 #endif /* EMLXS_LITTLE_ENDIAN */
1105 
1106 } emlxs_mqdb_t;
1107 
1108 
1109 typedef union emlxs_mqdbu
1110 {
1111 	uint32_t	word;
1112 	emlxs_mqdb_t	db;
1113 
1114 } emlxs_mqdbu_t;
1115 
1116 
1117 #ifdef	__cplusplus
1118 }
1119 #endif
1120 
1121 #endif	/* _EMLXS_QUEUE_H */
1122