1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_1394_ADAPTERS_HCI1394_RIO_REGS_H 28 #define _SYS_1394_ADAPTERS_HCI1394_RIO_REGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * hci1394_rio_regs.h 34 * Sun Microsystems RIO chipset 35 * See the RIO specification (r1.0), section 5.9, for a description 36 * of the vendor specific registers. 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /* 45 * RIO's vendor specific register mapping information. What register set it 46 * uses and the offset/size of the register set. 47 */ 48 #define RIOREG_REG_BASE 0x2 49 #define RIOREG_OFFSET 0x0 50 #define RIOREG_LENGTH 0x800 51 52 /* 53 * For RIO pass 1, we will setup the GUID in as part of the vendor specific 54 * init. This is to support the RIO PPX card (since it does not have firmware 55 * to setup the GUID. 56 */ 57 #define RIOREG_GUID_MASK 0x000000FFFFFFFFFF 58 #define RIOREG_GUID_SUN_MICROSYSTEMS 0x0800200000000000 59 #define RIOREG_SUNW_RIO_PASS1 0x01080020 60 61 /* 62 * RIO vendor specific registers. These are the offsets of the registers. They 63 * should be used as paramteres to hci1394_vendor_reg_write() and 64 * hci1394_vendor_reg_read(). 65 */ 66 #define RIOREG_INTR_EVENT 0x00 67 #define RIOREG_INTR_MASK 0x04 68 #define RIOREG_DMA_BURST_SIZE 0x08 69 #define RIOREG_XMIT_CONTROL 0x0C 70 #define RIOREG_HOST_CONTROL 0x10 71 #define RIOREG_STATS_RETRIES 0x14 72 #define RIOREG_STATS_ERRORS 0x18 73 #define RIOREG_STATS_PHYSICAL 0x1C 74 75 /* RIO interrupt event & mask bit offsets */ 76 #define RIOREG_INTR_STATS1 0x001 77 #define RIOREG_INTR_STATS2 0x002 78 #define RIOREG_INTR_STATS3 0x004 79 #define RIOREG_INTR_STATS4 0x008 80 #define RIOREG_INTR_STATS5 0x010 81 #define RIOREG_INTR_STATS6 0x020 82 #define RIOREG_INTR_STATS7 0x040 83 #define RIOREG_INTR_STATS8 0x080 84 #define RIOREG_INTR_LINKON 0x100 85 86 /* dma_burst_size (field defs) */ 87 #define RIOREG_INF_BURST_SHIFT 0 88 #define RIOREG_DBURST_SHIFT 1 89 #define RIOREG_RXBURST_SHIFT 26 90 #define RIOREG_TXBURST_SHIFT 28 91 #define RIOREG_PFBURST_SHIFT 30 92 #define RIOREG_INF_BURST_MASK (1 << RIOREG_INF_BURST_SHIFT) 93 #define RIOREG_DBURST_MASK (1 << RIOREG_DBURST_SHIFT) 94 #define RIOREG_RXBURST_MASK (3 << RIOREG_RXBURST_SHIFT) 95 #define RIOREG_TXBURST_MASK (3 << RIOREG_TXBURST_SHIFT) 96 #define RIOREG_PFBURST_MASK (3 << RIOREG_PFBURST_SHIFT) 97 98 /* dma_burst_size (values) */ 99 #define RIOREG_BURST_32 0 /* 32 bytes or less */ 100 #define RIOREG_BURST_64 1 /* 64 bytes or less */ 101 #define RIOREG_BURST_128 2 /* 128 bytes or less */ 102 #define RIOREG_BURST_256 3 /* 256 bytes or less */ 103 104 /* xmit ctrl (field defs) */ 105 #define RIOREG_XMIT_BND1_SHIFT 0 106 #define RIOREG_XMIT_BND2_SHIFT 8 107 #define RIOREG_XMIT_BND1_MASK (0xFF << RIOREG_XMIT_BND1_SHIFT) 108 #define RIOREG_XMIT_BND2_MASK (0xFF << RIOREG_XMIT_BND2_SHIFT) 109 110 /* host control (field defs) */ 111 #define RIOREG_HOST_ATREQ 0x00000001 112 #define RIOREG_HOST_ATRESP 0x00000002 113 #define RIOREG_HOST_IT1 0x00000004 114 #define RIOREG_HOST_IT2 0x00000008 115 #define RIOREG_HOST_IT3 0x00000010 116 #define RIOREG_HOST_IT4 0x00000020 117 #define RIOREG_HOST_ARREQ 0x00000040 118 #define RIOREG_HOST_ARRESP 0x00000080 119 #define RIOREG_HOST_IR1 0x00000100 120 #define RIOREG_HOST_IR2 0x00000200 121 #define RIOREG_HOST_IR3 0x00000400 122 #define RIOREG_HOST_IR4 0x00000800 123 #define RIOREG_HOST_BWCAT 0x02000000 124 #define RIOREG_HOST_BRCAT 0x04000000 125 #define RIOREG_HOST_ISOCTL 0xC0000000 126 127 /* Allow Descriptor pre-fetching */ 128 #define RIOREG_HOST_CONTROL_SETTING \ 129 (RIOREG_HOST_ATREQ | RIOREG_HOST_ATRESP | RIOREG_HOST_IT1 | \ 130 RIOREG_HOST_IT2 | RIOREG_HOST_IT3 | RIOREG_HOST_IT4 | \ 131 RIOREG_HOST_ARREQ | RIOREG_HOST_ARRESP | RIOREG_HOST_IR1 | \ 132 RIOREG_HOST_IR2 | RIOREG_HOST_IR3 | RIOREG_HOST_IR4) 133 134 /* stats_retries (field defs) */ 135 #define RIOREG_RET_PHYS 0xFF000000 136 #define RIOREG_RET_ATS 0x0000FF00 137 #define RIOREG_RET_ATQ 0x000000FF 138 139 /* stats_errors (field defs) */ 140 #define RIOREG_ERR_EACKR 0x000000FF 141 #define RIOREG_ERR_EACKX 0x0000FF00 142 #define RIOREG_ERR_BUS 0x0FFF0000 143 144 /* stats_phys (field defs) */ 145 #define RIOREG_PHYS_WRQ 0x000000FF 146 #define RIOREG_PHYS_RDQ 0x00FF0000 147 148 149 #ifdef __cplusplus 150 } 151 #endif 152 153 #endif /* _SYS_1394_ADAPTERS_HCI1394_RIO_REGS_H */ 154