1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010-2013, by Broadcom, Inc. 24 * All Rights Reserved. 25 */ 26 27 /* 28 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. 29 * All rights reserved. 30 */ 31 32 #ifndef _BGE_HW_H 33 #define _BGE_HW_H 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <sys/types.h> 40 41 42 /* 43 * First section: 44 * Identification of the various Broadcom chips 45 * 46 * Note: the various ID values are *not* all unique ;-( 47 * 48 * Note: the presence of an ID here does *not* imply that the chip is 49 * supported. At this time, only the 5703C, 5704C, and 5704S devices 50 * used on the motherboards of certain Sun products are supported. 51 * 52 * Note: the revision-id values in the PCI revision ID register are 53 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 54 */ 55 56 #define VENDOR_ID_BROADCOM 0x14e4 57 #define VENDOR_ID_SUN 0x108e 58 59 #define DEVICE_ID_5700 0x1644 60 #define DEVICE_ID_5700x 0x0003 61 #define DEVICE_ID_5701 0x1645 62 #define DEVICE_ID_5702 0x16a6 63 #define DEVICE_ID_5702fe 0x164d 64 #define DEVICE_ID_5703C 0x16a7 65 #define DEVICE_ID_5703S 0x1647 66 #define DEVICE_ID_5703 0x16c7 67 #define DEVICE_ID_5704C 0x1648 68 #define DEVICE_ID_5704S 0x16a8 69 #define DEVICE_ID_5704 0x1649 70 #define DEVICE_ID_5705C 0x1653 71 #define DEVICE_ID_5705_2 0x1654 72 #define DEVICE_ID_5717 0x1655 73 #define DEVICE_ID_5717_C0 0x1665 74 #define DEVICE_ID_5718 0x1656 75 #define DEVICE_ID_5719 0x1657 76 #define DEVICE_ID_5720 0x165f 77 #define DEVICE_ID_5724 0x165c 78 #define DEVICE_ID_5725 0x1643 79 #define DEVICE_ID_5727 0x16f3 80 #define DEVICE_ID_5705M 0x165d 81 #define DEVICE_ID_5705MA3 0x165e 82 #define DEVICE_ID_5705F 0x166e 83 #define DEVICE_ID_5780 0x166a 84 #define DEVICE_ID_5782 0x1696 85 #define DEVICE_ID_5785 0x1699 86 #define DEVICE_ID_5787 0x169b 87 #define DEVICE_ID_5787M 0x1693 88 #define DEVICE_ID_5788 0x169c 89 #define DEVICE_ID_5789 0x169d 90 #define DEVICE_ID_5751 0x1677 91 #define DEVICE_ID_5751M 0x167d 92 #define DEVICE_ID_5752 0x1600 93 #define DEVICE_ID_5752M 0x1601 94 #define DEVICE_ID_5753 0x16fd 95 #define DEVICE_ID_5754 0x167a 96 #define DEVICE_ID_5755 0x167b 97 #define DEVICE_ID_5755M 0x1673 98 #define DEVICE_ID_5756M 0x1674 99 #define DEVICE_ID_5721 0x1659 100 #define DEVICE_ID_5722 0x165a 101 #define DEVICE_ID_5723 0x165b 102 #define DEVICE_ID_5714C 0x1668 103 #define DEVICE_ID_5714S 0x1669 104 #define DEVICE_ID_5715C 0x1678 105 #define DEVICE_ID_5715S 0x1679 106 #define DEVICE_ID_5761E 0x1680 107 #define DEVICE_ID_5761 0x1681 108 #define DEVICE_ID_5764 0x1684 109 #define DEVICE_ID_5906 0x1712 110 #define DEVICE_ID_5906M 0x1713 111 #define DEVICE_ID_57780 0x1692 112 113 #define REVISION_ID_5700_B0 0x10 114 #define REVISION_ID_5700_B2 0x12 115 #define REVISION_ID_5700_B3 0x13 116 #define REVISION_ID_5700_C0 0x20 117 #define REVISION_ID_5700_C1 0x21 118 #define REVISION_ID_5700_C2 0x22 119 120 #define REVISION_ID_5701_A0 0x08 121 #define REVISION_ID_5701_A2 0x12 122 #define REVISION_ID_5701_A3 0x15 123 124 #define REVISION_ID_5702_A0 0x00 125 126 #define REVISION_ID_5703_A0 0x00 127 #define REVISION_ID_5703_A1 0x01 128 #define REVISION_ID_5703_A2 0x02 129 130 #define REVISION_ID_5704_A0 0x00 131 #define REVISION_ID_5704_A1 0x01 132 #define REVISION_ID_5704_A2 0x02 133 #define REVISION_ID_5704_A3 0x03 134 #define REVISION_ID_5704_B0 0x10 135 136 #define REVISION_ID_5705_A0 0x00 137 #define REVISION_ID_5705_A1 0x01 138 #define REVISION_ID_5705_A2 0x02 139 #define REVISION_ID_5705_A3 0x03 140 141 #define REVISION_ID_5721_A0 0x00 142 #define REVISION_ID_5721_A1 0x01 143 144 #define REVISION_ID_5751_A0 0x00 145 #define REVISION_ID_5751_A1 0x01 146 147 #define REVISION_ID_5714_A0 0x00 148 #define REVISION_ID_5714_A1 0x01 149 #define REVISION_ID_5714_A2 0xA2 150 #define REVISION_ID_5714_A3 0xA3 151 152 #define REVISION_ID_5715_A0 0x00 153 #define REVISION_ID_5715_A1 0x01 154 #define REVISION_ID_5715_A2 0xA2 155 156 #define REVISION_ID_5715S_A0 0x00 157 #define REVISION_ID_5715S_A1 0x01 158 159 #define REVISION_ID_5754_A0 0x00 160 #define REVISION_ID_5754_A1 0x01 161 162 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 163 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 164 (bgep->chipid.device == DEVICE_ID_5701) ||\ 165 (bgep->chipid.device == DEVICE_ID_5702) ||\ 166 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 167 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 168 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 169 (bgep->chipid.device == DEVICE_ID_5703) ||\ 170 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 171 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 172 (bgep->chipid.device == DEVICE_ID_5704)) 173 174 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 175 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 176 (bgep->chipid.device == DEVICE_ID_5702fe)) 177 178 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 179 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 180 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 181 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 182 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 183 (bgep->chipid.device == DEVICE_ID_5780) ||\ 184 (bgep->chipid.device == DEVICE_ID_5782) ||\ 185 (bgep->chipid.device == DEVICE_ID_5788) ||\ 186 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 187 (bgep->chipid.device == DEVICE_ID_5754) ||\ 188 (bgep->chipid.device == DEVICE_ID_5755) ||\ 189 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 190 (bgep->chipid.device == DEVICE_ID_5753)) 191 192 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 193 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 194 (bgep->chipid.device == DEVICE_ID_5751) ||\ 195 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 196 (bgep->chipid.device == DEVICE_ID_5752) ||\ 197 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 198 (bgep->chipid.device == DEVICE_ID_5789)) 199 200 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \ 201 ((bgep->chipid.device == DEVICE_ID_5717) ||\ 202 (bgep->chipid.device == DEVICE_ID_5718) ||\ 203 (bgep->chipid.device == DEVICE_ID_5719) ||\ 204 (bgep->chipid.device == DEVICE_ID_5720) ||\ 205 (bgep->chipid.device == DEVICE_ID_5724)) 206 207 #define DEVICE_5725_SERIES_CHIPSETS(bgep) \ 208 ((bgep->chipid.device == DEVICE_ID_5725) ||\ 209 (bgep->chipid.device == DEVICE_ID_5727)) 210 211 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 212 ((bgep->chipid.device == DEVICE_ID_5723) ||\ 213 (bgep->chipid.device == DEVICE_ID_5761) ||\ 214 (bgep->chipid.device == DEVICE_ID_5761E) ||\ 215 (bgep->chipid.device == DEVICE_ID_5764) ||\ 216 (bgep->chipid.device == DEVICE_ID_5785) ||\ 217 (bgep->chipid.device == DEVICE_ID_57780)) 218 219 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 220 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 221 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 222 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 223 (bgep->chipid.device == DEVICE_ID_5715S)) 224 225 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 226 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 227 (bgep->chipid.device == DEVICE_ID_5906M)) 228 229 /* 230 * Second section: 231 * Offsets of important registers & definitions for bits therein 232 */ 233 234 /* 235 * PCI-X registers & bits 236 */ 237 #define PCIX_CONF_COMM 0x42 238 #define PCIX_COMM_RELAXED 0x0002 239 240 /* 241 * Miscellaneous Host Control Register, in PCI config space 242 */ 243 #define PCI_CONF_BGE_MHCR 0x68 244 #define MHCR_CHIP_REV_MASK 0xffff0000 245 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 246 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 247 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 248 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 249 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 250 #define MHCR_ENABLE_PCI_STATE_RW 0x00000010 251 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 252 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 253 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 254 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 255 #define MHCR_BOUNDARY_CHECK 0x00002000 256 #define MHCR_TLP_MINOR_ERR_TOLERANCE 0x00008000 257 258 #define MHCR_CHIP_REV_5700_B0 0x71000000 259 #define MHCR_CHIP_REV_5700_B2 0x71020000 260 #define MHCR_CHIP_REV_5700_B3 0x71030000 261 #define MHCR_CHIP_REV_5700_C0 0x72000000 262 #define MHCR_CHIP_REV_5700_C1 0x72010000 263 #define MHCR_CHIP_REV_5700_C2 0x72020000 264 265 #define MHCR_CHIP_REV_5701_A0 0x00000000 266 #define MHCR_CHIP_REV_5701_A2 0x00020000 267 #define MHCR_CHIP_REV_5701_A3 0x00030000 268 #define MHCR_CHIP_REV_5701_A5 0x01050000 269 270 #define MHCR_CHIP_REV_5702_A0 0x10000000 271 #define MHCR_CHIP_REV_5702_A1 0x10010000 272 #define MHCR_CHIP_REV_5702_A2 0x10020000 273 274 #define MHCR_CHIP_REV_5703_A0 0x10000000 275 #define MHCR_CHIP_REV_5703_A1 0x10010000 276 #define MHCR_CHIP_REV_5703_A2 0x10020000 277 #define MHCR_CHIP_REV_5703_B0 0x11000000 278 #define MHCR_CHIP_REV_5703_B1 0x11010000 279 280 #define MHCR_CHIP_REV_5704_A0 0x20000000 281 #define MHCR_CHIP_REV_5704_A1 0x20010000 282 #define MHCR_CHIP_REV_5704_A2 0x20020000 283 #define MHCR_CHIP_REV_5704_A3 0x20030000 284 #define MHCR_CHIP_REV_5704_B0 0x21000000 285 286 #define MHCR_CHIP_REV_5705_A0 0x30000000 287 #define MHCR_CHIP_REV_5705_A1 0x30010000 288 #define MHCR_CHIP_REV_5705_A2 0x30020000 289 #define MHCR_CHIP_REV_5705_A3 0x30030000 290 #define MHCR_CHIP_REV_5705_A5 0x30050000 291 292 #define MHCR_CHIP_REV_5782_A0 0x30030000 293 #define MHCR_CHIP_REV_5782_A1 0x30030088 294 295 #define MHCR_CHIP_REV_5788_A1 0x30050000 296 297 #define MHCR_CHIP_REV_5751_A0 0x40000000 298 #define MHCR_CHIP_REV_5751_A1 0x40010000 299 300 #define MHCR_CHIP_REV_5721_A0 0x41000000 301 #define MHCR_CHIP_REV_5721_A1 0x41010000 302 303 #define MHCR_CHIP_REV_5714_A0 0x50000000 304 #define MHCR_CHIP_REV_5714_A1 0x90010000 305 306 #define MHCR_CHIP_REV_5715_A0 0x50000000 307 #define MHCR_CHIP_REV_5715_A1 0x90010000 308 309 #define MHCR_CHIP_REV_5715S_A0 0x50000000 310 #define MHCR_CHIP_REV_5715S_A1 0x90010000 311 312 #define MHCR_CHIP_REV_5754_A0 0xb0000000 313 #define MHCR_CHIP_REV_5754_A1 0xb0010000 314 315 #define MHCR_CHIP_REV_5787_A0 0xb0000000 316 #define MHCR_CHIP_REV_5787_A1 0xb0010000 317 #define MHCR_CHIP_REV_5787_A2 0xb0020000 318 319 #define MHCR_CHIP_REV_5755_A0 0xa0000000 320 #define MHCR_CHIP_REV_5755_A1 0xa0010000 321 322 #define MHCR_CHIP_REV_5906_A0 0xc0000000 323 #define MHCR_CHIP_REV_5906_A1 0xc0010000 324 #define MHCR_CHIP_REV_5906_A2 0xc0020000 325 326 #define CHIP_ASIC_REV_USE_PROD_ID_REG 0xf0000000 327 #define MHCR_CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev & 0xf0000000) 328 #define CHIP_ASIC_REV_PROD_ID(bgep) ((bgep)->chipid.asic_rev_prod_id) 329 #define CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev_prod_id >> 12) 330 331 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 332 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 333 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 334 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 335 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 336 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 337 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 338 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 339 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 340 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 341 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 342 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 343 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 344 /* (0xf << 28) touches all 5717 and 5725 series as well (OK) */ 345 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 346 347 #define CHIP_ASIC_REV_5723 0x5784 348 #define CHIP_ASIC_REV_5761 0x5761 349 #define CHIP_ASIC_REV_5785 0x5785 350 #define CHIP_ASIC_REV_57780 0x57780 351 352 #define CHIP_ASIC_REV_5717 0x5717 353 #define CHIP_ASIC_REV_5719 0x5719 354 #define CHIP_ASIC_REV_5720 0x5720 355 #define CHIP_ASIC_REV_5762 0x5762 /* 5725/5727 */ 356 357 #define CHIP_ASIC_REV_PROD_ID_REG 0x000000bc 358 #define CHIP_ASIC_REV_PROD_ID_GEN2_REG 0x000000f4 359 360 #define CHIP_ASIC_REV_5717_B0 0x05717100 361 #define CHIP_ASIC_REV_5717_C0 0x05717200 362 #define CHIP_ASIC_REV_5718_B0 0x05717100 363 #define CHIP_ASIC_REV_5719_A0 0x05719000 364 #define CHIP_ASIC_REV_5719_A1 0x05719001 365 #define CHIP_ASIC_REV_5720_A0 0x05720000 366 #define CHIP_ASIC_REV_5725_A0 0x05762000 367 #define CHIP_ASIC_REV_5727_B0 0x05762100 368 369 /* 370 * PCI DMA read/write Control Register, in PCI config space 371 * 372 * Note that several fields previously defined here have been deleted 373 * as they are not implemented in the 5703/4. 374 * 375 * Note: the value of this register is critical. It is possible to 376 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 377 * by programming the wrong value. The value #defined below has been 378 * tested and shown to avoid all known problems. If it is to be changed, 379 * correct operation must be reverified on all supported platforms. 380 * 381 * In particular, we set both watermark fields to 2xCacheLineSize (128) 382 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 383 * with Tomatillo's internal pipelines, that otherwise result in stalls, 384 * repeated retries, and DTOs. 385 */ 386 #define PCI_CONF_BGE_PDRWCR 0x6c 387 #define PDRWCR_RWCMD_MASK 0xFF000000 388 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 389 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 390 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 391 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 392 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 393 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 394 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 395 396 /* 397 * These are the actual values to be put into the fields shown above 398 */ 399 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 400 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 401 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 402 #define PDRWCR_MIN_BEATS 0x00000000 403 404 #define PDRWCR_VAR_DEFAULT 0x761b0000 405 #define PDRWCR_VAR_5721 0x76180000 406 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 407 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 408 #define PDRWCR_VAR_5717 0x00380000 409 410 /* 411 * PCI State Register, in PCI config space 412 * 413 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 414 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 415 */ 416 #define PCI_CONF_BGE_PCISTATE 0x70 417 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 418 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 419 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 420 #define PCISTATE_RETRY_SAME_DMA 0x00002000 421 #define PCISTATE_FLAT_VIEW 0x00000100 422 #define PCISTATE_EXT_ROM_RETRY 0x00000040 423 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 424 #define PCISTATE_BUS_IS_32_BIT 0x00000010 425 #define PCISTATE_BUS_IS_FAST 0x00000008 426 #define PCISTATE_BUS_IS_PCI 0x00000004 427 #define PCISTATE_INTA_STATE 0x00000002 428 #define PCISTATE_FORCE_RESET 0x00000001 429 430 /* 431 * PCI Clock Control Register, in PCI config space 432 */ 433 #define PCI_CONF_BGE_CLKCTL 0x74 434 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 435 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 436 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 437 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 438 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 439 #define CLKCTL_PCIE_A0_FIX 0x00101000 440 441 /* 442 * Dual MAC Control Register, in PCI config space 443 */ 444 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 445 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 446 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 447 448 /* 449 * Register Indirect Access Address Register, 0x78 in PCI config 450 * space. Once this is set, accesses to the Register Indirect 451 * Access Data Register (0x80) refer to the register whose address 452 * is given by *this* register. This allows access to all the 453 * operating registers, while using only config space accesses. 454 * 455 * Note that the address written to the RIIAR should lie in one 456 * of the following ranges: 457 * 0x00000000 <= address < 0x00008000 (regular registers) 458 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 459 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 460 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 461 */ 462 #define PCI_CONF_BGE_RIAAR 0x78 463 #define PCI_CONF_BGE_RIADR 0x80 464 465 #define RIAAR_REGISTER_MIN 0x00000000 466 #define RIAAR_REGISTER_MAX 0x00008000 467 #define RIAAR_RX_SCRATCH_MIN 0x00030000 468 #define RIAAR_RX_SCRATCH_MAX 0x00034000 469 #define RIAAR_TX_SCRATCH_MIN 0x00034000 470 #define RIAAR_TX_SCRATCH_MAX 0x00038000 471 #define RIAAR_RXROM_MIN 0x00038000 472 #define RIAAR_RXROM_MAX 0x00038800 473 474 /* 475 * Memory Window Base Address Register, 0x7c in PCI config space 476 * Once this is set, accesses to the Memory Window Data Access Register 477 * (0x84) refer to the word of NIC-local memory whose address is given 478 * by this register. When used in this way, the whole of the address 479 * written to this register is significant. 480 * 481 * This register also provides the 32K-aligned base address for a 32K 482 * region of NIC-local memory that the host can directly address in 483 * the upper 32K of the 64K of PCI memory space allocated to the chip. 484 * In this case, the bottom 15 bits of the register are ignored. 485 * 486 * Note that the address written to the MWBAR should lie in the range 487 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 488 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 489 * memory were present, but it's only supported on the 5700, not the 490 * 5701/5703/5704. 491 */ 492 #define PCI_CONF_BGE_MWBAR 0x7c 493 #define PCI_CONF_BGE_MWDAR 0x84 494 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 495 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 496 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 497 498 /* 499 * The PCI express device control register and device status register 500 * which are only applicable on BCM5751 and BCM5721. 501 */ 502 #define PCI_CONF_DEV_CTRL 0xd8 503 #define PCI_CONF_DEV_CTRL_5723 0xd4 504 #define PCI_CONF_DEV_CTRL_5717 0xb4 505 #define READ_REQ_SIZE_MASK 0x7000 506 #define READ_REQ_SIZE_MAX 0x5000 507 #define READ_REQ_SIZE_2K 0x4000 508 #define DEV_CTRL_NO_SNOOP 0x0800 509 #define DEV_CTRL_RELAXED 0x0010 510 511 #define PCI_CONF_DEV_STUS 0xda 512 #define PCI_CONF_DEV_STUS_5723 0xd6 513 #define DEVICE_ERROR_STUS 0xf 514 515 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 516 517 /* 518 * Where to find things in NIC-local (on-chip) memory 519 */ 520 #define NIC_MEM_SEND_RINGS 0x0100 521 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 522 #define NIC_MEM_RECV_RINGS 0x0200 523 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 524 #define NIC_MEM_STATISTICS 0x0300 525 #define NIC_MEM_STATISTICS_SIZE 0x0800 526 #define NIC_MEM_STATUS_BLOCK 0x0b00 527 #define NIC_MEM_STATUS_SIZE 0x0050 528 #define NIC_MEM_GENCOMM 0x0b50 529 530 531 /* 532 * Note: the (non-bogus) values below are appropriate for systems 533 * without external memory. They would be different on a 5700 with 534 * external memory. 535 * 536 * Note: The higher send ring addresses and the mini ring shadow 537 * buffer address are dummies - systems without external memory 538 * are limited to 4 send rings and no mini receive ring. 539 */ 540 #define NIC_MEM_SHADOW_DMA 0x2000 541 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 542 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 543 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 544 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 545 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 546 #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000 547 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 548 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 549 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 550 551 /* 552 * Put this in the GENCOMM port to tell the firmware not to run PXE 553 */ 554 #define T3_MAGIC_NUMBER 0x4b657654u 555 556 /* 557 * The remaining registers appear in the low 32K of regular 558 * PCI Memory Address Space 559 */ 560 561 /* 562 * All the state machine control registers below have at least a 563 * <RESET> bit and an <ENABLE> bit as defined below. Some also 564 * have an <ATTN_ENABLE> bit. 565 */ 566 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 567 #define STATE_MACHINE_ENABLE_BIT 0x00000002 568 #define STATE_MACHINE_RESET_BIT 0x00000001 569 570 #define TRANSMIT_MAC_MODE_REG 0x045c 571 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 572 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 573 #define SEND_BD_SELECTOR_MODE_REG 0x1400 574 #define SEND_BD_INITIATOR_MODE_REG 0x1800 575 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 576 577 #define RECEIVE_MAC_MODE_REG 0x0468 578 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 579 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 580 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 581 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 582 #define RCV_BD_COMPLETION_MODE_REG 0x3000 583 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 584 585 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 586 #define HOST_COALESCE_MODE_REG 0x3c00 587 #define MEMORY_ARBITER_MODE_REG 0x4000 588 #define BUFFER_MANAGER_MODE_REG 0x4400 589 #define BUFFER_MANAGER_MODE_NO_TX_UNDERRUN 0x80000000 590 #define BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE 0x00000010 591 #define READ_DMA_MODE_REG 0x4800 592 #define WRITE_DMA_MODE_REG 0x4c00 593 #define DMA_COMPLETION_MODE_REG 0x6400 594 #define FAST_BOOT_PC 0x6894 595 596 #define RDMA_RSRV_CTRL_REG 0x4900 597 #define RDMA_RSRV_CTRL_REG2 0x4890 598 #define RDMA_RSRV_CTRL_FIFO_OFLW_FIX 0x00000004 599 #define RDMA_RSRV_CTRL_FIFO_LWM_1_5K 0x00000c00 600 #define RDMA_RSRV_CTRL_FIFO_LWM_MASK 0x00000ff0 601 #define RDMA_RSRV_CTRL_FIFO_HWM_1_5K 0x000c0000 602 #define RDMA_RSRV_CTRL_FIFO_HWM_MASK 0x000ff000 603 #define RDMA_RSRV_CTRL_TXMRGN_320B 0x28000000 604 #define RDMA_RSRV_CTRL_TXMRGN_MASK 0xffe00000 605 606 #define RDMA_CORR_CTRL_REG 0x4910 607 #define RDMA_CORR_CTRL_REG2 0x48a0 608 #define RDMA_CORR_CTRL_BLEN_BD_4K 0x00030000 609 #define RDMA_CORR_CTRL_BLEN_LSO_4K 0x000c0000 610 #define RDMA_CORR_CTRL_TX_LENGTH_WA 0x02000000 611 612 #define BGE_NUM_RDMA_CHANNELS 4 613 #define BGE_RDMA_LENGTH 0x4be0 614 615 /* 616 * Other bits in some of the above state machine control registers 617 */ 618 619 /* 620 * Transmit MAC Mode Register 621 * (TRANSMIT_MAC_MODE_REG, 0x045c) 622 */ 623 #define TRANSMIT_MODE_MBUF_LOCKUP_FIX 0x00000100 624 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 625 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 626 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 627 628 /* 629 * Receive MAC Mode Register 630 * (RECEIVE_MAC_MODE_REG, 0x0468) 631 */ 632 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 633 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 634 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 635 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 636 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 637 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 638 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 639 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 640 641 /* 642 * Receive BD Initiator Mode Register 643 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 644 * 645 * Each of these bits controls whether ATTN is asserted 646 * on a particular condition 647 */ 648 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 649 650 /* 651 * Receive Data & Receive BD Initiator Mode Register 652 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 653 * 654 * Each of these bits controls whether ATTN is asserted 655 * on a particular condition 656 */ 657 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 658 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 659 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 660 661 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 662 663 /* 664 * Host Coalescing Mode Control Register 665 * (HOST_COALESCE_MODE_REG, 0x3c00) 666 */ 667 #define COALESCE_64_BYTE_RINGS 12 668 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 669 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 670 #define COALESCE_CLR_TICKS_TX 0x00000400 671 #define COALESCE_CLR_TICKS_RX 0x00000200 672 #define COALESCE_32_BYTE_STATUS 0x00000100 673 #define COALESCE_64_BYTE_STATUS 0x00000080 674 #define COALESCE_NOW 0x00000008 675 676 /* 677 * Memory Arbiter Mode Register 678 * (MEMORY_ARBITER_MODE_REG, 0x4000) 679 */ 680 #define MEMORY_ARBITER_ENABLE 0x00000002 681 682 /* 683 * Buffer Manager Mode Register 684 * (BUFFER_MANAGER_MODE_REG, 0x4400) 685 * 686 * In addition to the usual error-attn common to most state machines 687 * this register has a separate bit for attn on running-low-on-mbufs 688 */ 689 #define BUFF_MGR_TEST_MODE 0x00000008 690 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 691 692 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 693 694 /* 695 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 696 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 697 * 698 * These registers each contain a 2-bit priority field, which controls 699 * the relative priority of that type of DMA (read vs. write vs. MSI), 700 * and a set of bits that control whether ATTN is asserted on each 701 * particular condition 702 */ 703 #define DMA_PRIORITY_MASK 0xc0000000 704 #define DMA_PRIORITY_SHIFT 30 705 #define ALL_DMA_ATTN_BITS 0x000003fc 706 707 /* 708 * BCM5755, 5755M, 5906, 5906M only 709 * 1 - Enable Fix. Device will send out the status block before 710 * the interrupt message 711 * 0 - Disable fix. Device will send out the interrupt message 712 * before the status block 713 */ 714 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 715 716 /* 717 * End of state machine control register definitions 718 */ 719 720 721 /* 722 * High priority mailbox registers. 723 * Mailbox Registers (8 bytes each, but high half unused) 724 */ 725 #define INTERRUPT_MBOX_0_REG 0x0200 726 #define INTERRUPT_MBOX_1_REG 0x0208 727 #define INTERRUPT_MBOX_2_REG 0x0210 728 #define INTERRUPT_MBOX_3_REG 0x0218 729 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 730 731 /* 732 * Low priority mailbox registers, for BCM5906, BCM5906M. 733 */ 734 #define INTERRUPT_LP_MBOX_0_REG 0x5800 735 736 /* 737 * Ring Producer/Consumer Index (Mailbox) Registers 738 */ 739 #define RECV_STD_PROD_INDEX_REG 0x0268 740 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 741 #define RECV_MINI_PROD_INDEX_REG 0x0278 742 #define RECV_RING_CONS_INDEX_REGS 0x0280 743 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 744 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 745 746 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 747 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 748 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 749 750 /* 751 * Ethernet MAC Mode Register 752 */ 753 #define ETHERNET_MAC_MODE_REG 0x0400 754 #define ETHERNET_MODE_APE_TX_EN 0x10000000 755 #define ETHERNET_MODE_APE_RX_EN 0x08000000 756 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 757 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 758 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 759 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 760 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 761 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 762 #define ETHERNET_MODE_SEND_CFGS 0x00020000 763 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 764 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 765 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 766 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 767 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 768 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 769 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 770 #define ETHERNET_MODE_MAX_DEFER 0x00000200 771 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 772 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 773 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 774 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 775 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 776 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 777 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 778 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 779 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 780 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 781 782 /* 783 * Ethernet MAC Status & Event Registers 784 */ 785 #define ETHERNET_MAC_STATUS_REG 0x0404 786 #define ETHERNET_STATUS_MI_INT 0x00800000 787 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 788 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 789 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 790 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 791 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 792 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 793 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 794 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 795 796 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 797 #define ETHERNET_EVENT_MI_INT 0x00800000 798 #define ETHERNET_EVENT_LINK_INT 0x00001000 799 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 800 801 /* 802 * Ethernet MAC LED Control Register 803 * 804 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 805 * the external LED driver circuitry is wired up to assume that this mode 806 * will always be selected. Software must not change it! 807 */ 808 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 809 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 810 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 811 #define LED_CONTROL_LED_MODE_MASK 0x00001800 812 #define LED_CONTROL_LED_MODE_5700 0x00000000 813 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 814 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 815 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 816 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 817 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 818 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 819 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 820 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 821 #define LED_CONTROL_TRAFFIC_LED 0x00000020 822 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 823 #define LED_CONTROL_10MBPS_LED 0x00000008 824 #define LED_CONTROL_100MBPS_LED 0x00000004 825 #define LED_CONTROL_1000MBPS_LED 0x00000002 826 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 827 #define LED_CONTROL_DEFAULT 0x02000800 828 829 /* 830 * MAC Address registers 831 * 832 * These four eight-byte registers each hold one unicast address 833 * (six bytes), right justified & zero-filled on the left. 834 * They will normally all be set to the same value, as a station 835 * usually only has one h/w address. The value in register 0 is 836 * used for pause packets; any of the four can be specified for 837 * substitution into other transmitted packets if required. 838 */ 839 #define MAC_ADDRESS_0_REG 0x0410 840 #define MAC_ADDRESS_1_REG 0x0418 841 #define MAC_ADDRESS_2_REG 0x0420 842 #define MAC_ADDRESS_3_REG 0x0428 843 844 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 845 #define MAC_ADDRESS_REGS_MAX 4 846 847 /* 848 * More MAC Registers ... 849 */ 850 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 851 #define MAC_RX_MTU_SIZE_REG 0x043c 852 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 853 #define MAC_TX_LENGTHS_REG 0x0464 854 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 855 856 /* 857 * MII access registers 858 */ 859 #define MI_COMMS_REG 0x044c 860 #define MI_COMMS_START 0x20000000 861 #define MI_COMMS_READ_FAILED 0x10000000 862 #define MI_COMMS_COMMAND_MASK 0x0c000000 863 #define MI_COMMS_COMMAND_READ 0x08000000 864 #define MI_COMMS_COMMAND_WRITE 0x04000000 865 #define MI_COMMS_ADDRESS_MASK 0x03e00000 866 #define MI_COMMS_ADDRESS_SHIFT 21 867 #define MI_COMMS_REGISTER_MASK 0x001f0000 868 #define MI_COMMS_REGISTER_SHIFT 16 869 #define MI_COMMS_DATA_MASK 0x0000ffff 870 #define MI_COMMS_DATA_SHIFT 0 871 872 #define MI_STATUS_REG 0x0450 873 #define MI_STATUS_10MBPS 0x00000002 874 #define MI_STATUS_LINK 0x00000001 875 876 #define MI_MODE_REG 0x0454 877 #define MI_MODE_CLOCK_MASK 0x001f0000 878 #define MI_MODE_AUTOPOLL 0x00000010 879 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 880 #define MI_MODE_DEFAULT 0x000c0000 881 882 #define MI_AUTOPOLL_STATUS_REG 0x0458 883 #define MI_AUTOPOLL_ERROR 0x00000001 884 885 #define TRANSMIT_MAC_STATUS_REG 0x0460 886 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 887 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 888 #define TRANSMIT_STATUS_LINK_UP 0x00000008 889 #define TRANSMIT_STATUS_SENT_XON 0x00000004 890 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 891 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 892 893 #define RECEIVE_MAC_STATUS_REG 0x046c 894 #define RECEIVE_STATUS_RCVD_XON 0x00000004 895 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 896 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 897 898 /* 899 * These four-byte registers constitute a hash table for deciding 900 * whether to accept incoming multicast packets. The bits are 901 * numbered in big-endian fashion, from hash 0 => the MSB of 902 * register 0 to hash 127 => the LSB of the highest-numbered 903 * register. 904 * 905 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 906 * enabled by setting the appropriate bit in the Rx MAC mode 907 * register. Otherwise, and on all earlier chips, the table 908 * is only 128 bits (registers 0-3). 909 */ 910 #define MAC_HASH_0_REG 0x0470 911 #define MAC_HASH_1_REG 0x0474 912 #define MAC_HASH_2_REG 0x0478 913 #define MAC_HASH_3_REG 0x047c 914 #define MAC_HASH_4_REG 0x???? 915 #define MAC_HASH_5_REG 0x???? 916 #define MAC_HASH_6_REG 0x???? 917 #define MAC_HASH_7_REG 0x???? 918 #define MAC_HASH_REG(n) (0x470+4*(n)) 919 920 /* 921 * Receive Rules Registers: 16 pairs of control+mask/value pairs 922 */ 923 #define RCV_RULES_CONTROL_0_REG 0x0480 924 #define RCV_RULES_MASK_0_REG 0x0484 925 #define RCV_RULES_CONTROL_15_REG 0x04f8 926 #define RCV_RULES_MASK_15_REG 0x04fc 927 #define RCV_RULES_CONFIG_REG 0x0500 928 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 929 930 #define RECV_RULES_NUM_MAX 16 931 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 932 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 933 934 #define RECV_RULE_CTL_ENABLE 0x80000000 935 #define RECV_RULE_CTL_AND 0x40000000 936 #define RECV_RULE_CTL_P1 0x20000000 937 #define RECV_RULE_CTL_P2 0x10000000 938 #define RECV_RULE_CTL_P3 0x08000000 939 #define RECV_RULE_CTL_MASK 0x04000000 940 #define RECV_RULE_CTL_DISCARD 0x02000000 941 #define RECV_RULE_CTL_MAP 0x01000000 942 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 943 #define RECV_RULE_CTL_OP 0x00030000 944 #define RECV_RULE_CTL_OP_EQ 0x00000000 945 #define RECV_RULE_CTL_OP_NEQ 0x00010000 946 #define RECV_RULE_CTL_OP_GREAT 0x00020000 947 #define RECV_RULE_CTL_OP_LESS 0x00030000 948 #define RECV_RULE_CTL_HEADER 0x0000e000 949 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 950 #define RECV_RULE_CTL_HEADER_IP 0x00002000 951 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 952 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 953 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 954 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 955 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 956 RECV_RULE_CTL_CLASS_BITS) 957 #define RECV_RULE_CTL_OFFSET 0x000000ff 958 959 /* 960 * Receive Rules definition 961 */ 962 #define ETHERHEADER_DEST_OFFSET 0x00 963 #define IPHEADER_PROTO_OFFSET 0x08 964 #define IPHEADER_SIP_OFFSET 0x0c 965 #define IPHEADER_DIP_OFFSET 0x10 966 #define TCPHEADER_SPORT_OFFSET 0x00 967 #define TCPHEADER_DPORT_OFFSET 0x02 968 #define UDPHEADER_SPORT_OFFSET 0x00 969 #define UDPHEADER_DPORT_OFFSET 0x02 970 971 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 972 RECV_RULE_CTL_CLASS((ring))) 973 974 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 975 976 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 977 RECV_RULE_CTL_HEADER_FRAME | \ 978 ETHERHEADER_DEST_OFFSET) 979 980 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 981 RECV_RULE_CTL_HEADER_FRAME | \ 982 ETHERHEADER_DEST_OFFSET + 4) 983 984 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 985 IPHEADER_DIP_OFFSET) 986 987 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 988 IPHEADER_SIP_OFFSET) 989 990 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 991 RECV_RULE_CTL_HEADER_IP | \ 992 IPHEADER_PROTO_OFFSET) 993 994 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 995 RECV_RULE_CTL_HEADER_TCP | \ 996 TCPHEADER_SPORT_OFFSET) 997 998 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 999 RECV_RULE_CTL_HEADER_TCP | \ 1000 TCPHEADER_DPORT_OFFSET) 1001 1002 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 1003 RECV_RULE_CTL_HEADER_UDP | \ 1004 UDPHEADER_SPORT_OFFSET) 1005 1006 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 1007 RECV_RULE_CTL_HEADER_UDP | \ 1008 UDPHEADER_DPORT_OFFSET) 1009 1010 /* 1011 * 1000BaseX low-level access registers 1012 */ 1013 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 1014 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 1015 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 1016 #define TX_1000BASEX_AUTONEG_REG 0x0444 1017 #define RX_1000BASEX_AUTONEG_REG 0x0448 1018 1019 /* 1020 * Autoneg code bits for the 1000BASE-X AUTONEG registers 1021 */ 1022 #define AUTONEG_CODE_PAUSE 0x00008000 1023 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 1024 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 1025 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 1026 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 1027 #define AUTONEG_CODE_FAULT_MASK 0x00000030 1028 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 1029 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 1030 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 1031 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 1032 1033 /* 1034 * SerDes Registers (5703S/5704S only) 1035 */ 1036 #define SERDES_CONTROL_REG 0x0590 1037 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 1038 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 1039 #define SERDES_CONTROL_TX_DISABLE 0x00004000 1040 #define SERDES_STATUS_REG 0x0594 1041 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 1042 #define SERDES_STATUS_RXSTAT 0x000000ff 1043 1044 /* 5780/5714 only */ 1045 #define SERDES_RX_CONTROL 0x000005b0 1046 #define SERDES_RX_CONTROL_SIG_DETECT 0x00000400 1047 1048 /* 1049 * SGMII Status Register (5717/18/19/20 only) 1050 */ 1051 #define SGMII_STATUS_REG 0x5B4 1052 #define MEDIA_SELECTION_MODE 0x00000100 1053 1054 /* 1055 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 1056 */ 1057 #define STAT_IFHCOUT_OCTETS_REG 0x0800 1058 #define STAT_ETHER_COLLIS_REG 0x0808 1059 #define STAT_OUTXON_SENT_REG 0x080c 1060 #define STAT_OUTXOFF_SENT_REG 0x0810 1061 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 1062 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 1063 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 1064 #define STAT_DOT3_DEFERED_TX_REG 0x0824 1065 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 1066 #define STAT_DOT3_LATE_COLLI_REG 0x0830 1067 #define STAT_IFHCOUT_UPKGS_REG 0x086c 1068 #define STAT_IFHCOUT_MPKGS_REG 0x0870 1069 #define STAT_IFHCOUT_BPKGS_REG 0x0874 1070 1071 #define STAT_IFHCIN_OCTETS_REG 0x0880 1072 #define STAT_ETHER_FRAGMENT_REG 0x0888 1073 #define STAT_IFHCIN_UPKGS_REG 0x088c 1074 #define STAT_IFHCIN_MPKGS_REG 0x0890 1075 #define STAT_IFHCIN_BPKGS_REG 0x0894 1076 1077 #define STAT_DOT3_FCS_ERR_REG 0x0898 1078 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 1079 #define STAT_XON_PAUSE_RX_REG 0x08a0 1080 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 1081 #define STAT_MAC_CTRL_RX_REG 0x08a8 1082 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 1083 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 1084 #define STAT_ETHER_JABBERS_REG 0x08b4 1085 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 1086 #define SIZE_OF_STATISTIC_REG 0x1B 1087 /* 1088 * Send Data Initiator Registers 1089 */ 1090 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 1091 #define SEND_INIT_STATS_ZERO 0x00000010 1092 #define SEND_INIT_STATS_FLUSH 0x00000008 1093 #define SEND_INIT_STATS_CLEAR 0x00000004 1094 #define SEND_INIT_STATS_FASTER 0x00000002 1095 #define SEND_INIT_STATS_ENABLE 0x00000001 1096 1097 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 1098 1099 /* 1100 * Send Buffer Descriptor Selector Control Registers 1101 */ 1102 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 1103 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 1104 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 1105 1106 /* 1107 * Receive List Placement Registers 1108 */ 1109 #define RCV_LP_CONFIG_REG 0x2010 1110 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1111 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1112 1113 #define RCV_LP_STATS_CONTROL_REG 0x2014 1114 #define RCV_LP_STATS_ZERO 0x00000010 1115 #define RCV_LP_STATS_FLUSH 0x00000008 1116 #define RCV_LP_STATS_CLEAR 0x00000004 1117 #define RCV_LP_STATS_FASTER 0x00000002 1118 #define RCV_LP_STATS_ENABLE 0x00000001 1119 1120 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1121 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1122 1123 /* 1124 * Receive Data & BD Initiator Registers 1125 */ 1126 #define RCV_INITIATOR_STATUS_REG 0x2404 1127 1128 /* 1129 * Receive Buffer Descriptor Ring Control Block Registers 1130 * NB: sixteen bytes (128 bits) each 1131 */ 1132 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1133 #define STD_RCV_BD_RING_RCB_REG 0x2450 1134 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1135 1136 /* 1137 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1138 */ 1139 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1140 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1141 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1142 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1143 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1144 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1145 1146 /* 1147 * CPMU registers (5717/18/19/20 only) 1148 */ 1149 #define CPMU_CLCK_ORIDE_REG 0x3624 1150 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1151 #define CPMU_STATUS_REG 0x362c 1152 #define CPMU_STATUS_FUNC_NUM 0x20000000 1153 #define CPMU_STATUS_FUNC_NUM_SHIFT 29 1154 #define CPMU_STATUS_FUNC_NUM_5719 0xc0000000 1155 #define CPMU_STATUS_FUNC_NUM_5719_SHIFT 30 1156 1157 /* 1158 * EEE registers (5718/19/20 only) 1159 */ 1160 #define EEE_MODE_REG 0x36b0 1161 #define EEE_MODE_APE_TX_DET_EN 0x00000004 1162 #define EEE_MODE_ERLY_L1_XIT_DET 0x00000008 1163 #define EEE_MODE_SND_IDX_DET_EN 0x00000040 1164 #define EEE_MODE_LPI_ENABLE 0x00000080 1165 #define EEE_MODE_LPI_IN_TX 0x00000100 1166 #define EEE_MODE_LPI_IN_RX 0x00000200 1167 #define EEE_MODE_EEE_ENABLE 0x00100000 1168 1169 #define EEE_DEBOUNCE_T1_CONTROL_REG 0x36b4 1170 #define EEE_DEBOUNCE_T1_PCIEXIT_2047US 0x07ff0000 1171 #define EEE_DEBOUNCE_T1_LNKIDLE_2047US 0x000007ff 1172 1173 #define EEE_DEBOUNCE_T2_CONTROL_REG 0x36b8 1174 #define EEE_DEBOUNCE_T2_APE_TX_2047US 0x07ff0000 1175 #define EEE_DEBOUNCE_T2_TXIDXEQ_2047US 0x000007ff 1176 1177 #define EEE_LINK_IDLE_CONTROL_REG 0x36bc 1178 #define EEE_LINK_IDLE_PCIE_NL0 0x01000000 1179 #define EEE_LINK_IDLE_UART_IDL 0x00000004 1180 #define EEE_LINK_IDLE_APE_TX_MT 0x00000002 1181 1182 #define EEE_CONTROL_REG 0x36d0 1183 #define EEE_CONTROL_EXIT_16_5_US 0x0000019d 1184 #define EEE_CONTROL_EXIT_36_US 0x00000384 1185 #define EEE_CONTROL_EXIT_20_1_US 0x000001f8 1186 1187 /* Clause 45 expansion registers */ 1188 #define EEE_CL45_D7_RESULT_STAT 0x803e 1189 #define EEE_CL45_D7_RESULT_STAT_LP_100TX 0x0002 1190 #define EEE_CL45_D7_RESULT_STAT_LP_1000T 0x0004 1191 1192 #define MDIO_MMD_AN 0x0007 1193 #define MDIO_AN_EEE_ADV 0x003c 1194 1195 /* 1196 * Host Coalescing Engine Control Registers 1197 */ 1198 #define RCV_COALESCE_TICKS_REG 0x3c08 1199 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1200 #define SEND_COALESCE_TICKS_REG 0x3c0c 1201 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1202 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1203 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1204 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1205 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1206 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1207 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1208 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1209 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1210 #define RCV_COALESCE_INT_BD_REG 0x3c20 1211 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1212 #define SEND_COALESCE_INT_BD_REG 0x3c24 1213 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1214 #define STATISTICS_TICKS_REG 0x3c28 1215 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1216 #define STATISTICS_HOST_ADDR_REG 0x3c30 1217 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1218 #define STATISTICS_BASE_ADDR_REG 0x3c40 1219 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1220 #define FLOW_ATTN_REG 0x3c48 1221 1222 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1223 #define NIC_STD_RECV_INDEX_REG 0x3c54 1224 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1225 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1226 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1227 1228 /* 1229 * Mbuf Pool Initialisation & Watermark Registers 1230 * 1231 * There are some conflicts in the PRM; compare the recommendations 1232 * on pp. 115, 236, and 339. The values here were recommended by 1233 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1234 */ 1235 #define BUFFER_MANAGER_STATUS_REG 0x4404 1236 #define MBUF_POOL_BASE_REG 0x4408 1237 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1238 #define MBUF_POOL_BASE_5721 0x00010000 1239 #define MBUF_POOL_BASE_5704 0x00010000 1240 #define MBUF_POOL_BASE_5705 0x00010000 1241 #define MBUF_POOL_LENGTH_REG 0x440c 1242 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1243 #define MBUF_POOL_LENGTH_5704 0x00010000 1244 #define MBUF_POOL_LENGTH_5705 0x00008000 1245 #define MBUF_POOL_LENGTH_5721 0x00008000 1246 #define RDMA_MBUF_LOWAT_REG 0x4410 1247 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1248 #define RDMA_MBUF_LOWAT_5705 0x00000000 1249 #define RDMA_MBUF_LOWAT_5906 0x00000000 1250 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1251 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1252 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1253 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1254 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1255 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1256 #define MAC_RX_MBUF_LOWAT_5717 0x0000002a 1257 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1258 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1259 #define MBUF_HIWAT_REG 0x4418 1260 #define MBUF_HIWAT_DEFAULT 0x00000060 1261 #define MBUF_HIWAT_5705 0x00000060 1262 #define MBUF_HIWAT_5906 0x00000010 1263 #define MBUF_HIWAT_5717 0x000000a0 1264 #define MBUF_HIWAT_JUMBO 0x0000017c 1265 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1266 1267 /* 1268 * DMA Descriptor Pool Initialisation & Watermark Registers 1269 */ 1270 #define DMAD_POOL_BASE_REG 0x442c 1271 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1272 #define DMAD_POOL_LENGTH_REG 0x4430 1273 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1274 #define DMAD_POOL_LOWAT_REG 0x4434 1275 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1276 #define DMAD_POOL_HIWAT_REG 0x4438 1277 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1278 1279 /* 1280 * More threshold/watermark registers ... 1281 */ 1282 #define RECV_FLOW_THRESHOLD_REG 0x4458 1283 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1284 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1285 1286 /* 1287 * Read/Write DMA Status Registers 1288 */ 1289 #define READ_DMA_STATUS_REG 0x4804 1290 #define WRITE_DMA_STATUS_REG 0x4c04 1291 1292 /* 1293 * RX/TX RISC Registers 1294 */ 1295 #define RX_RISC_MODE_REG 0x5000 1296 #define RX_RISC_STATE_REG 0x5004 1297 #define RX_RISC_PC_REG 0x501c 1298 #define TX_RISC_MODE_REG 0x5400 1299 #define TX_RISC_STATE_REG 0x5404 1300 #define TX_RISC_PC_REG 0x541c 1301 1302 /* 1303 * V? RISC Registerss 1304 */ 1305 #define VCPU_STATUS_REG 0x5100 1306 #define VCPU_INIT_DONE 0x04000000 1307 #define VCPU_DRV_RESET 0x08000000 1308 1309 #define VCPU_EXT_CTL 0x6890 1310 #define VCPU_EXT_CTL_HALF 0x00400000 1311 1312 #define FTQ_RESET_REG 0x5c00 1313 1314 #define MSI_MODE_REG 0x6000 1315 #define MSI_PRI_HIGHEST 0xc0000000 1316 #define MSI_MSI_ENABLE 0x00000002 1317 #define MSI_ERROR_ATTENTION 0x0000001c 1318 1319 #define MSI_STATUS_REG 0x6004 1320 1321 #define MODE_CONTROL_REG 0x6800 1322 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1323 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1324 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1325 #define MODE_INT_ON_DMA_ATTN 0x08000000 1326 #define MODE_INT_ON_MAC_ATTN 0x04000000 1327 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1328 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1329 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1330 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1331 #define MODE_HOST_SEND_BDS 0x00020000 1332 #define MODE_HOST_STACK_UP 0x00010000 1333 #define MODE_FORCE_32_BIT_PCI 0x00008000 1334 #define MODE_NO_INT_ON_RECV 0x00004000 1335 #define MODE_NO_INT_ON_SEND 0x00002000 1336 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1337 #define MODE_NO_CRC 0x00000400 1338 #define MODE_NO_FRAME_CRACKING 0x00000200 1339 #define MODE_WORD_SWAP_FRAME 0x00000020 1340 #define MODE_BYTE_SWAP_FRAME 0x00000010 1341 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1342 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1343 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1344 1345 /* 1346 * Miscellaneous Configuration Register 1347 * 1348 * This contains various bits relating to power control (which differ 1349 * among different members of the chip family), but the important bits 1350 * for our purposes are the RESET bit and the Timer Prescaler field. 1351 * 1352 * The RESET bit in this register serves to reset the whole chip, even 1353 * including the PCI interface(!) Once it's set, the chip will not 1354 * respond to ANY accesses -- not even CONFIG space -- until the reset 1355 * completes internally. According to the PRM, this should take less 1356 * than 100us. Any access during this period will get a bus error. 1357 * 1358 * The Timer Prescaler field must be programmed so that the timer period 1359 * is as near as possible to 1us. The value in this field should be 1360 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1361 * the Core Clock should always be 66MHz (independently of the bus speed, 1362 * at least for PCI rather than PCI-X), so this register must be set to 1363 * the value 0x82 ((66-1) << 1). 1364 */ 1365 #define CORE_CLOCK_MHZ 66 1366 #define MISC_CONFIG_REG 0x6804 1367 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1368 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1369 #define MISC_CONFIG_POWERDOWN 0x00100000 1370 #define MISC_CONFIG_POWER_STATE 0x00060000 1371 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1372 #define MISC_CONFIG_RESET_BIT 0x00000001 1373 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1374 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1375 1376 /* 1377 * Miscellaneous Local Control Register (MLCR) 1378 */ 1379 #define MISC_LOCAL_CONTROL_REG 0x6808 1380 1381 #define MLCR_PCI_CTRL_SELECT 0x10000000 1382 #define MLCR_LEGACY_PCI_MODE 0x08000000 1383 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1384 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1385 #define MLCR_SSRAM_TYPE 0x00400000 1386 #define MLCR_BANK_SELECT 0x00200000 1387 1388 #define MLCR_SRAM_SIZE_16M 0x00180000 1389 #define MLCR_SRAM_SIZE_8M 0x00140000 1390 #define MLCR_SRAM_SIZE_4M 0x00100000 1391 #define MLCR_SRAM_SIZE_2M 0x000c0000 1392 #define MLCR_SRAM_SIZE_1M 0x00080000 1393 #define MLCR_SRAM_SIZE_512K 0x00040000 1394 #define MLCR_SRAM_SIZE_256K 0x00000000 1395 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1396 1397 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1398 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1399 1400 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1401 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1402 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1403 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1404 1405 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1406 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1407 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1408 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1409 1410 #define MLCR_GPIO_OUTPUT3 0x00000080 1411 #define MLCR_GPIO_OE3 0x00000040 1412 #define MLCR_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1413 #define MLCR_GPIO_INPUT3 0x00000020 1414 #define MLCR_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1415 #define MLCR_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1416 1417 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1418 #define MLCR_SET_INT 0x00000004 /* W/O */ 1419 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1420 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1421 1422 /* 1423 * This value defines all GPIO bits as INPUTS, but sets their default 1424 * values as outputs to HIGH, on the assumption that external circuits 1425 * (if any) will probably be active-LOW with passive pullups. 1426 * 1427 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1428 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1429 * enable writing. Otherwise, the SEEPROM is protected. 1430 */ 1431 #define MLCR_DEFAULT (MLCR_AUTO_SEEPROM_ACCESS | \ 1432 MLCR_MISC_PINS_OUTPUT_2 | \ 1433 MLCR_MISC_PINS_OUTPUT_1 | \ 1434 MLCR_MISC_PINS_OUTPUT_0) 1435 1436 #define MLCR_DEFAULT_5714 (MLCR_PCI_CTRL_SELECT | \ 1437 MLCR_LEGACY_PCI_MODE | \ 1438 MLCR_AUTO_SEEPROM_ACCESS | \ 1439 MLCR_MISC_PINS_OUTPUT_2 | \ 1440 MLCR_MISC_PINS_OUTPUT_1 | \ 1441 MLCR_MISC_PINS_OUTPUT_0 | \ 1442 MLCR_USE_SIG_DETECT) 1443 1444 #define MLCR_DEFAULT_5717 (MLCR_AUTO_SEEPROM_ACCESS) 1445 1446 /* 1447 * Serial EEPROM Data/Address Registers (auto-access mode) 1448 */ 1449 #define SERIAL_EEPROM_DATA_REG 0x683c 1450 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1451 #define SEEPROM_ACCESS_READ 0x80000000 1452 #define SEEPROM_ACCESS_WRITE 0x00000000 1453 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1454 #define SEEPROM_ACCESS_RESET 0x20000000 1455 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1456 #define SEEPROM_ACCESS_START 0x02000000 1457 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1458 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1459 1460 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1461 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1462 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1463 1464 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1465 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1466 1467 /* 1468 * "Linearised" address mask, treating multiple devices as consecutive 1469 */ 1470 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1471 1472 /* 1473 * Non-Volatile Memory Interface Registers 1474 * Note: on chips that support the flash interface (5702+), flash is the 1475 * default and the legacy seeprom interface must be explicitly enabled 1476 * if required. On older chips (5700/01), SEEPROM is the default (and 1477 * only) non-volatile memory available, and these registers don't exist! 1478 */ 1479 #define NVM_FLASH_CMD_REG 0x7000 1480 #define NVM_FLASH_CMD_LAST 0x00000100 1481 #define NVM_FLASH_CMD_FIRST 0x00000080 1482 #define NVM_FLASH_CMD_RD 0x00000000 1483 #define NVM_FLASH_CMD_WR 0x00000020 1484 #define NVM_FLASH_CMD_DOIT 0x00000010 1485 #define NVM_FLASH_CMD_DONE 0x00000008 1486 1487 #define NVM_FLASH_WRITE_REG 0x7008 1488 #define NVM_FLASH_READ_REG 0x7010 1489 1490 #define NVM_FLASH_ADDR_REG 0x700c 1491 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1492 1493 #define NVM_CONFIG1_REG 0x7014 1494 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1495 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1496 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1497 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1498 #define NVM_CFG1_FLASH_MODE 0x00000001 1499 1500 #define NVM_SW_ARBITRATION_REG 0x7020 1501 #define NVM_READ_REQ3 0x00008000 1502 #define NVM_READ_REQ2 0x00004000 1503 #define NVM_READ_REQ1 0x00002000 1504 #define NVM_READ_REQ0 0x00001000 1505 #define NVM_WON_REQ3 0x00000800 1506 #define NVM_WON_REQ2 0x00000400 1507 #define NVM_WON_REQ1 0x00000200 1508 #define NVM_WON_REQ0 0x00000100 1509 #define NVM_RESET_REQ3 0x00000080 1510 #define NVM_RESET_REQ2 0x00000040 1511 #define NVM_RESET_REQ1 0x00000020 1512 #define NVM_RESET_REQ0 0x00000010 1513 #define NVM_SET_REQ3 0x00000008 1514 #define NVM_SET_REQ2 0x00000004 1515 #define NVM_SET_REQ1 0x00000002 1516 #define NVM_SET_REQ0 0x00000001 1517 1518 #define EEPROM_MAGIC 0x669955aa 1519 #define EEPROM_MAGIC_FW 0xa5000000 1520 #define EEPROM_MAGIC_FW_MSK 0xff000000 1521 #define EEPROM_SB_FORMAT_MASK 0x00e00000 1522 #define EEPROM_SB_FORMAT_1 0x00200000 1523 #define EEPROM_SB_REVISION_MASK 0x001f0000 1524 #define EEPROM_SB_REVISION_0 0x00000000 1525 #define EEPROM_SB_REVISION_2 0x00020000 1526 #define EEPROM_SB_REVISION_3 0x00030000 1527 #define EEPROM_SB_REVISION_4 0x00040000 1528 #define EEPROM_SB_REVISION_5 0x00050000 1529 #define EEPROM_SB_REVISION_6 0x00060000 1530 #define EEPROM_MAGIC_HW 0xabcd 1531 #define EEPROM_MAGIC_HW_MSK 0xffff 1532 1533 #define NVM_DIR_START 0x18 1534 #define NVM_DIR_END 0x78 1535 #define NVM_DIRENT_SIZE 0xc 1536 #define NVM_DIRTYPE_SHIFT 24 1537 #define NVM_DIRTYPE_LENMSK 0x003fffff 1538 #define NVM_DIRTYPE_ASFINI 1 1539 #define NVM_DIRTYPE_EXTVPD 20 1540 #define NVM_PTREV_BCVER 0x94 1541 #define NVM_BCVER_MAJMSK 0x0000ff00 1542 #define NVM_BCVER_MAJSFT 8 1543 #define NVM_BCVER_MINMSK 0x000000ff 1544 1545 /* 1546 * NVM access register 1547 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1548 * and BCM5715 only. 1549 */ 1550 #define NVM_ACCESS_REG 0x7024 1551 #define NVM_WRITE_ENABLE 0x00000002 1552 #define NVM_ACCESS_ENABLE 0x00000001 1553 1554 /* 1555 * TLP Control Register 1556 * Applicable to BCM5721 and BCM5751 only 1557 */ 1558 #define TLP_CONTROL_REG 0x7c00 1559 #define TLP_DATA_FIFO_PROTECT 0x02000000 1560 1561 /* 1562 * PHY Test Control Register 1563 * Applicable to BCM5721 and BCM5751 only 1564 */ 1565 #define PHY_TEST_CTRL_REG 0x7e2c 1566 #define PHY_PCIE_SCRAM_MODE 0x20 1567 #define PHY_PCIE_LTASS_MODE 0x40 1568 1569 /* 1570 * The internal firmware expects a certain layout of the non-volatile 1571 * memory (if fitted), and will check for it during startup, and use the 1572 * contents to initialise various internal parameters if it looks good. 1573 * 1574 * The offsets and field definitions below refer to where to find some 1575 * important values, and how to interpret them ... 1576 */ 1577 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1578 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1579 1580 /* 1581 * Vendor-specific MII registers 1582 */ 1583 1584 #define MII_MMD_CTRL 0x0d /* MMD Access Control register */ 1585 #define MII_MMD_CTRL_DATA_NOINC 0x4000 1586 #define MII_MMD_ADDRESS_DATA 0x0e /* MMD Address Data register */ 1587 1588 #define MII_RXR_COUNTERS 0x14 /* Local/Remote Rx Counts */ 1589 #define MII_DSP_RW_PORT 0x15 /* DSP read/write port */ 1590 #define MII_DSP_CONTROL 0x16 /* DSP control register */ 1591 #define MII_DSP_ADDRESS 0x17 /* DSP address register */ 1592 1593 #define MII_DSP_TAP26 0x001a 1594 #define MII_DSP_TAP26_ALNOKO 0x0001 1595 #define MII_DSP_TAP26_RMRXSTO 0x0002 1596 #define MII_DSP_TAP26_OPCSINPT 0x0004 1597 1598 #define MII_DSP_CH34TP2 0x4022 1599 #define MII_DSP_CH34TP2_HIBW01 0x017b 1600 1601 #define MII_EXT_CONTROL MII_VENDOR(0) 1602 #define MII_EXT_STATUS MII_VENDOR(1) 1603 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1604 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1605 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1606 #define MII_AUX_CONTROL MII_VENDOR(8) 1607 #define MII_AUX_STATUS MII_VENDOR(9) 1608 #define MII_INTR_STATUS MII_VENDOR(10) 1609 #define MII_INTR_MASK MII_VENDOR(11) 1610 #define MII_HCD_STATUS MII_VENDOR(13) 1611 1612 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1613 1614 /* 1615 * Bits in the MII_EXT_CONTROL register 1616 */ 1617 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1618 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1619 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1620 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1621 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1622 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1623 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1624 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1625 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1626 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1627 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1628 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1629 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1630 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1631 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1632 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1633 1634 /* 1635 * Bits in the MII_EXT_STATUS register 1636 */ 1637 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1638 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1639 #define MII_EXT_STAT_MDIX_STATE 0x2000 1640 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1641 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1642 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1643 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1644 #define MII_EXT_STAT_LINK_STATUS 0x0100 1645 #define MII_EXT_STAT_CRC_ERROR 0x0080 1646 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1647 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1648 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1649 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1650 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1651 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1652 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1653 1654 /* 1655 * The AUX CONTROL register is seriously weird! 1656 * 1657 * It hides (up to) eight 'shadow' registers. When writing, which one 1658 * of them is written is determined by the low-order bits of the data 1659 * written(!), but when reading, which one is read is determined by the 1660 * value previously written to (part of) one of the shadow registers!!! 1661 */ 1662 1663 /* 1664 * Shadow register numbers 1665 */ 1666 #define MII_AUX_CTRL_NORMAL 0 1667 #define MII_AUX_CTRL_10BASE_T 1 1668 #define MII_AUX_CTRL_POWER 2 1669 #define MII_AUX_CTRL_TEST_1 4 1670 #define MII_AUX_CTRL_MISC 7 1671 1672 /* 1673 * Selected bits in some of the shadow registers ... 1674 */ 1675 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1676 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1677 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1678 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1679 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1680 1681 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1682 1683 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1684 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1685 1686 #define MII_AUX_CTRL_TX_6DB 0x0400 1687 #define MII_AUX_CTRL_SMDSP_ENA 0x0800 1688 1689 /* 1690 * Write this value to the AUX control register 1691 * to select which shadow register will be read 1692 */ 1693 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1694 1695 /* 1696 * Bits in the MII_AUX_STATUS register 1697 */ 1698 #define MII_AUX_STATUS_MODE_MASK 0x0700 1699 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1700 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1701 #define MII_AUX_STATUS_MODE_100_F 0x0500 1702 #define MII_AUX_STATUS_MODE_100_4 0x0400 1703 #define MII_AUX_STATUS_MODE_100_H 0x0300 1704 #define MII_AUX_STATUS_MODE_10_F 0x0200 1705 #define MII_AUX_STATUS_MODE_10_H 0x0100 1706 #define MII_AUX_STATUS_MODE_NONE 0x0000 1707 #define MII_AUX_STATUS_MODE_SHIFT 8 1708 1709 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1710 #define MII_AUX_STATUS_REM_FAULT 0x0040 1711 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1712 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1713 1714 #define MII_AUX_STATUS_LINKUP 0x0004 1715 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1716 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1717 1718 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1719 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1720 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1721 1722 /* 1723 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1724 */ 1725 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1726 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1727 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1728 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1729 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1730 1731 1732 /* 1733 * Third section: 1734 * Hardware-defined data structures 1735 * 1736 * Note that the chip is naturally BIG-endian, so, for a big-endian 1737 * host, the structures defined below match those described in the PRM. 1738 * For little-endian hosts, some structures have to be swapped around. 1739 */ 1740 1741 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1742 #error Host endianness not defined 1743 #endif 1744 1745 /* 1746 * Architectural constants: absolute maximum numbers of each type of ring 1747 */ 1748 #ifdef BGE_EXT_MEM 1749 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1750 #else 1751 #define BGE_SEND_RINGS_MAX 4 1752 #endif 1753 #define BGE_SEND_RINGS_MAX_5705 1 1754 #define BGE_RECV_RINGS_MAX 16 1755 #define BGE_RECV_RINGS_MAX_5705 1 1756 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1757 /* only with ext mem) */ 1758 1759 #define BGE_SEND_SLOTS_MAX 512 1760 #define BGE_STD_SLOTS_MAX 512 1761 #define BGE_JUMBO_SLOTS_MAX 256 1762 #define BGE_MINI_SLOTS_MAX 1024 1763 #define BGE_RECV_SLOTS_MAX 2048 1764 #define BGE_RECV_SLOTS_5705 512 1765 #define BGE_RECV_SLOTS_5782 512 1766 #define BGE_RECV_SLOTS_5721 512 1767 1768 /* 1769 * Hardware-defined Ring Control Block 1770 */ 1771 typedef struct { 1772 uint64_t host_ring_addr; 1773 #ifdef _BIG_ENDIAN 1774 uint16_t max_len; 1775 uint16_t flags; 1776 uint32_t nic_ring_addr; 1777 #else 1778 uint32_t nic_ring_addr; 1779 uint16_t flags; 1780 uint16_t max_len; 1781 #endif /* _BIG_ENDIAN */ 1782 } bge_rcb_t; 1783 1784 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1785 #define RCB_FLAG_RING_DISABLED 0x0002 1786 1787 /* 1788 * Hardware-defined Send Buffer Descriptor 1789 */ 1790 typedef struct { 1791 uint64_t host_buf_addr; 1792 #ifdef _BIG_ENDIAN 1793 uint16_t len; 1794 uint16_t flags; 1795 uint16_t reserved; 1796 uint16_t vlan_tci; 1797 #else 1798 uint16_t vlan_tci; 1799 uint16_t reserved; 1800 uint16_t flags; 1801 uint16_t len; 1802 #endif /* _BIG_ENDIAN */ 1803 } bge_sbd_t; 1804 1805 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1806 #define SBD_FLAG_IP_CKSUM 0x0002 1807 #define SBD_FLAG_PACKET_END 0x0004 1808 #define SBD_FLAG_IP_FRAG 0x0008 1809 #define SBD_FLAG_JMB_PKT 0x0008 1810 #define SBD_FLAG_IP_FRAG_END 0x0010 1811 1812 #define SBD_FLAG_VLAN_TAG 0x0040 1813 #define SBD_FLAG_COAL_NOW 0x0080 1814 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1815 #define SBD_FLAG_CPU_POST_DMA 0x0200 1816 1817 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1818 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1819 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1820 1821 /* 1822 * Hardware-defined Receive Buffer Descriptor 1823 */ 1824 typedef struct { 1825 uint64_t host_buf_addr; 1826 #ifdef _BIG_ENDIAN 1827 uint16_t index; 1828 uint16_t len; 1829 uint16_t type; 1830 uint16_t flags; 1831 uint16_t ip_cksum; 1832 uint16_t tcp_udp_cksum; 1833 uint16_t error_flag; 1834 uint16_t vlan_tci; 1835 uint32_t reserved; 1836 uint32_t opaque; 1837 #else 1838 uint16_t flags; 1839 uint16_t type; 1840 uint16_t len; 1841 uint16_t index; 1842 uint16_t vlan_tci; 1843 uint16_t error_flag; 1844 uint16_t tcp_udp_cksum; 1845 uint16_t ip_cksum; 1846 uint32_t opaque; 1847 uint32_t reserved; 1848 #endif /* _BIG_ENDIAN */ 1849 } bge_rbd_t; 1850 1851 #define RBD_FLAG_STD_RING 0x0000 1852 #define RBD_FLAG_PACKET_END 0x0004 1853 1854 #define RBD_FLAG_JUMBO_RING 0x0020 1855 #define RBD_FLAG_VLAN_TAG 0x0040 1856 1857 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1858 #define RBD_FLAG_MINI_RING 0x0800 1859 #define RBD_FLAG_IP_CHECKSUM 0x1000 1860 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1861 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1862 1863 #define RBD_FLAG_DEFAULT 0x0000 1864 1865 #define RBD_ERROR_BAD_CRC 0x00010000 1866 #define RBD_ERROR_COLL_DETECT 0x00020000 1867 #define RBD_ERROR_LINK_LOST 0x00040000 1868 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1869 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1870 #define RBD_ERROR_MAC_ABORT 0x00200000 1871 #define RBD_ERROR_LEN_LESS_64 0x00400000 1872 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1873 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1874 1875 /* 1876 * Hardware-defined Status Block,Size of status block 1877 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1878 * alignment.For BCM5705/5788/5721/5751/5752/5714 1879 * and 5715,there is only 1 recv and send ring index,but 1880 * driver defined 16 indexs here,please pay attention only 1881 * one ring is enabled in these chipsets. 1882 */ 1883 typedef struct { 1884 uint64_t flags_n_tag; 1885 uint16_t buff_cons_index[4]; 1886 struct { 1887 #ifdef _BIG_ENDIAN 1888 uint16_t send_cons_index; 1889 uint16_t recv_prod_index; 1890 #else 1891 uint16_t recv_prod_index; 1892 uint16_t send_cons_index; 1893 #endif /* _BIG_ENDIAN */ 1894 } index[16]; 1895 } bge_status_t; 1896 1897 /* 1898 * Hardware-defined Receive BD Rule 1899 */ 1900 typedef struct { 1901 uint32_t control; 1902 uint32_t mask_value; 1903 } bge_recv_rule_t; 1904 1905 /* 1906 * This describes which sub-rule slots are used by a particular rule. 1907 */ 1908 typedef struct { 1909 int start; 1910 int count; 1911 } bge_rule_info_t; 1912 1913 /* 1914 * Indexes into the <buff_cons_index> array 1915 */ 1916 #ifdef _BIG_ENDIAN 1917 #define STATUS_STD_BUFF_CONS_INDEX 0 1918 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1919 #define STATUS_MINI_BUFF_CONS_INDEX 3 1920 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1921 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1922 #else 1923 #define STATUS_STD_BUFF_CONS_INDEX 3 1924 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1925 #define STATUS_MINI_BUFF_CONS_INDEX 0 1926 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1927 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1928 #endif /* _BIG_ENDIAN */ 1929 1930 /* 1931 * Bits in the <flags_n_tag> word 1932 */ 1933 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1934 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1935 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1936 #define STATUS_TAG_MASK 0x00000000000000FFull 1937 1938 /* 1939 * The tag from the status block is fed back to Interrupt Mailbox 0 1940 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1941 * lets the chip know what updates have been processed, so it can 1942 * reassert its interrupt if more updates have occurred since. 1943 * 1944 * These macros extract the tag from the <flags_n_tag> word, shift 1945 * it to the proper position in the Mailbox register, and provide 1946 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1947 * or enable interrupts 1948 */ 1949 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1950 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1951 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1952 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1953 1954 /* 1955 * Hardware-defined Statistics Block Offsets 1956 * 1957 * These are given in the manual as addresses in NIC memory, starting 1958 * from the NIC statistics area base address of 0x300; but here we 1959 * convert them into indexes into an array of (uint64_t)s, so we can 1960 * use them directly for accessing the copy of the statistics block 1961 * that the chip DMAs into main memory ... 1962 */ 1963 1964 #define KS_BASE 0x300 1965 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1966 1967 typedef enum { 1968 KS_ifHCInOctets = KS_ADDR(0x400), 1969 KS_etherStatsFragments = KS_ADDR(0x410), 1970 KS_ifHCInUcastPkts, 1971 KS_ifHCInMulticastPkts, 1972 KS_ifHCInBroadcastPkts, 1973 KS_dot3StatsFCSErrors, 1974 KS_dot3StatsAlignmentErrors, 1975 KS_xonPauseFramesReceived, 1976 KS_xoffPauseFramesReceived, 1977 KS_macControlFramesReceived, 1978 KS_xoffStateEntered, 1979 KS_dot3StatsFrameTooLongs, 1980 KS_etherStatsJabbers, 1981 KS_etherStatsUndersizePkts, 1982 KS_inRangeLengthError, 1983 KS_outRangeLengthError, 1984 KS_etherStatsPkts64Octets, 1985 KS_etherStatsPkts65to127Octets, 1986 KS_etherStatsPkts128to255Octets, 1987 KS_etherStatsPkts256to511Octets, 1988 KS_etherStatsPkts512to1023Octets, 1989 KS_etherStatsPkts1024to1518Octets, 1990 KS_etherStatsPkts1519to2047Octets, 1991 KS_etherStatsPkts2048to4095Octets, 1992 KS_etherStatsPkts4096to8191Octets, 1993 KS_etherStatsPkts8192to9022Octets, 1994 1995 KS_ifHCOutOctets = KS_ADDR(0x600), 1996 KS_etherStatsCollisions = KS_ADDR(0x610), 1997 KS_outXonSent, 1998 KS_outXoffSent, 1999 KS_flowControlDone, 2000 KS_dot3StatsInternalMacTransmitErrors, 2001 KS_dot3StatsSingleCollisionFrames, 2002 KS_dot3StatsMultipleCollisionFrames, 2003 KS_dot3StatsDeferredTransmissions, 2004 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 2005 KS_dot3StatsLateCollisions, 2006 KS_dot3Collided2Times, 2007 KS_dot3Collided3Times, 2008 KS_dot3Collided4Times, 2009 KS_dot3Collided5Times, 2010 KS_dot3Collided6Times, 2011 KS_dot3Collided7Times, 2012 KS_dot3Collided8Times, 2013 KS_dot3Collided9Times, 2014 KS_dot3Collided10Times, 2015 KS_dot3Collided11Times, 2016 KS_dot3Collided12Times, 2017 KS_dot3Collided13Times, 2018 KS_dot3Collided14Times, 2019 KS_dot3Collided15Times, 2020 KS_ifHCOutUcastPkts, 2021 KS_ifHCOutMulticastPkts, 2022 KS_ifHCOutBroadcastPkts, 2023 KS_dot3StatsCarrierSenseErrors, 2024 KS_ifOutDiscards, 2025 KS_ifOutErrors, 2026 2027 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 2028 KS_COSIfHCInPkts_2, 2029 KS_COSIfHCInPkts_3, 2030 KS_COSIfHCInPkts_4, 2031 KS_COSIfHCInPkts_5, 2032 KS_COSIfHCInPkts_6, 2033 KS_COSIfHCInPkts_7, 2034 KS_COSIfHCInPkts_8, 2035 KS_COSIfHCInPkts_9, 2036 KS_COSIfHCInPkts_10, 2037 KS_COSIfHCInPkts_11, 2038 KS_COSIfHCInPkts_12, 2039 KS_COSIfHCInPkts_13, 2040 KS_COSIfHCInPkts_14, 2041 KS_COSIfHCInPkts_15, 2042 KS_COSIfHCInPkts_16, 2043 KS_COSFramesDroppedDueToFilters, 2044 KS_nicDmaWriteQueueFull, 2045 KS_nicDmaWriteHighPriQueueFull, 2046 KS_nicNoMoreRxBDs, 2047 KS_ifInDiscards, 2048 KS_ifInErrors, 2049 KS_nicRecvThresholdHit, 2050 2051 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 2052 KS_COSIfHCOutPkts_2, 2053 KS_COSIfHCOutPkts_3, 2054 KS_COSIfHCOutPkts_4, 2055 KS_COSIfHCOutPkts_5, 2056 KS_COSIfHCOutPkts_6, 2057 KS_COSIfHCOutPkts_7, 2058 KS_COSIfHCOutPkts_8, 2059 KS_COSIfHCOutPkts_9, 2060 KS_COSIfHCOutPkts_10, 2061 KS_COSIfHCOutPkts_11, 2062 KS_COSIfHCOutPkts_12, 2063 KS_COSIfHCOutPkts_13, 2064 KS_COSIfHCOutPkts_14, 2065 KS_COSIfHCOutPkts_15, 2066 KS_COSIfHCOutPkts_16, 2067 KS_nicDmaReadQueueFull, 2068 KS_nicDmaReadHighPriQueueFull, 2069 KS_nicSendDataCompQueueFull, 2070 KS_nicRingSetSendProdIndex, 2071 KS_nicRingStatusUpdate, 2072 KS_nicInterrupts, 2073 KS_nicAvoidedInterrupts, 2074 KS_nicSendThresholdHit, 2075 2076 KS_STATS_SIZE = KS_ADDR(0xb00) 2077 } bge_stats_offset_t; 2078 2079 /* 2080 * Hardware-defined Statistics Block 2081 * 2082 * Another view of the statistic block, as a array and a structure ... 2083 */ 2084 2085 typedef union { 2086 uint64_t a[KS_STATS_SIZE]; 2087 struct { 2088 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 2089 2090 uint64_t ifHCInOctets; /* 0x0400 */ 2091 uint64_t spare2[1]; 2092 uint64_t etherStatsFragments; 2093 uint64_t ifHCInUcastPkts; 2094 uint64_t ifHCInMulticastPkts; 2095 uint64_t ifHCInBroadcastPkts; 2096 uint64_t dot3StatsFCSErrors; 2097 uint64_t dot3StatsAlignmentErrors; 2098 uint64_t xonPauseFramesReceived; 2099 uint64_t xoffPauseFramesReceived; 2100 uint64_t macControlFramesReceived; 2101 uint64_t xoffStateEntered; 2102 uint64_t dot3StatsFrameTooLongs; 2103 uint64_t etherStatsJabbers; 2104 uint64_t etherStatsUndersizePkts; 2105 uint64_t inRangeLengthError; 2106 uint64_t outRangeLengthError; 2107 uint64_t etherStatsPkts64Octets; 2108 uint64_t etherStatsPkts65to127Octets; 2109 uint64_t etherStatsPkts128to255Octets; 2110 uint64_t etherStatsPkts256to511Octets; 2111 uint64_t etherStatsPkts512to1023Octets; 2112 uint64_t etherStatsPkts1024to1518Octets; 2113 uint64_t etherStatsPkts1519to2047Octets; 2114 uint64_t etherStatsPkts2048to4095Octets; 2115 uint64_t etherStatsPkts4096to8191Octets; 2116 uint64_t etherStatsPkts8192to9022Octets; 2117 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 2118 2119 uint64_t ifHCOutOctets; /* 0x0600 */ 2120 uint64_t spare4[1]; 2121 uint64_t etherStatsCollisions; 2122 uint64_t outXonSent; 2123 uint64_t outXoffSent; 2124 uint64_t flowControlDone; 2125 uint64_t dot3StatsInternalMacTransmitErrors; 2126 uint64_t dot3StatsSingleCollisionFrames; 2127 uint64_t dot3StatsMultipleCollisionFrames; 2128 uint64_t dot3StatsDeferredTransmissions; 2129 uint64_t spare5[1]; 2130 uint64_t dot3StatsExcessiveCollisions; 2131 uint64_t dot3StatsLateCollisions; 2132 uint64_t dot3Collided2Times; 2133 uint64_t dot3Collided3Times; 2134 uint64_t dot3Collided4Times; 2135 uint64_t dot3Collided5Times; 2136 uint64_t dot3Collided6Times; 2137 uint64_t dot3Collided7Times; 2138 uint64_t dot3Collided8Times; 2139 uint64_t dot3Collided9Times; 2140 uint64_t dot3Collided10Times; 2141 uint64_t dot3Collided11Times; 2142 uint64_t dot3Collided12Times; 2143 uint64_t dot3Collided13Times; 2144 uint64_t dot3Collided14Times; 2145 uint64_t dot3Collided15Times; 2146 uint64_t ifHCOutUcastPkts; 2147 uint64_t ifHCOutMulticastPkts; 2148 uint64_t ifHCOutBroadcastPkts; 2149 uint64_t dot3StatsCarrierSenseErrors; 2150 uint64_t ifOutDiscards; 2151 uint64_t ifOutErrors; 2152 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 2153 2154 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 2155 uint64_t COSFramesDroppedDueToFilters; 2156 uint64_t nicDmaWriteQueueFull; 2157 uint64_t nicDmaWriteHighPriQueueFull; 2158 uint64_t nicNoMoreRxBDs; 2159 uint64_t ifInDiscards; 2160 uint64_t ifInErrors; 2161 uint64_t nicRecvThresholdHit; 2162 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 2163 2164 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 2165 uint64_t nicDmaReadQueueFull; 2166 uint64_t nicDmaReadHighPriQueueFull; 2167 uint64_t nicSendDataCompQueueFull; 2168 uint64_t nicRingSetSendProdIndex; 2169 uint64_t nicRingStatusUpdate; 2170 uint64_t nicInterrupts; 2171 uint64_t nicAvoidedInterrupts; 2172 uint64_t nicSendThresholdHit; 2173 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 2174 } s; 2175 } bge_statistics_t; 2176 2177 #define KS_STAT_REG_SIZE (0x1B) 2178 #define KS_STAT_REG_BASE (0x800) 2179 2180 typedef struct { 2181 uint32_t ifHCOutOctets; 2182 uint32_t etherStatsCollisions; 2183 uint32_t outXonSent; 2184 uint32_t outXoffSent; 2185 uint32_t dot3StatsInternalMacTransmitErrors; 2186 uint32_t dot3StatsSingleCollisionFrames; 2187 uint32_t dot3StatsMultipleCollisionFrames; 2188 uint32_t dot3StatsDeferredTransmissions; 2189 uint32_t dot3StatsExcessiveCollisions; 2190 uint32_t dot3StatsLateCollisions; 2191 uint32_t ifHCOutUcastPkts; 2192 uint32_t ifHCOutMulticastPkts; 2193 uint32_t ifHCOutBroadcastPkts; 2194 uint32_t ifHCInOctets; 2195 uint32_t etherStatsFragments; 2196 uint32_t ifHCInUcastPkts; 2197 uint32_t ifHCInMulticastPkts; 2198 uint32_t ifHCInBroadcastPkts; 2199 uint32_t dot3StatsFCSErrors; 2200 uint32_t dot3StatsAlignmentErrors; 2201 uint32_t xonPauseFramesReceived; 2202 uint32_t xoffPauseFramesReceived; 2203 uint32_t macControlFramesReceived; 2204 uint32_t xoffStateEntered; 2205 uint32_t dot3StatsFrameTooLongs; 2206 uint32_t etherStatsJabbers; 2207 uint32_t etherStatsUndersizePkts; 2208 } bge_statistics_reg_t; 2209 2210 2211 #ifdef BGE_IPMI_ASF 2212 2213 /* 2214 * Device internal memory entries 2215 */ 2216 2217 #define BGE_FIRMWARE_MAILBOX 0x0b50 2218 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 2219 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 2220 2221 2222 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 2223 #define BGE_NIC_DATA_SIG 0x4b657654 2224 2225 2226 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2227 2228 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2229 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2230 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2231 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2232 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2233 2234 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2235 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2236 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2237 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2238 2239 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2240 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2241 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2242 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2243 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2244 #define BGE_NIC_CFG_MINI_PCI 0x001000 2245 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2246 #define BGE_NIC_CFG_5753_12x12 0x100000 2247 2248 2249 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2250 2251 2252 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2253 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2254 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2255 2256 2257 #define BGE_CMD_MAILBOX 0x0b78 2258 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2259 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2260 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2261 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2262 2263 2264 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2265 #define BGE_CMD_DATA_MAILBOX 0x0b80 2266 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2267 2268 #define BGE_DRV_STATE_MAILBOX 0x0c04 2269 #define BGE_DRV_STATE_START 0x00000001 2270 #define BGE_DRV_STATE_START_DONE 0x80000001 2271 #define BGE_DRV_STATE_UNLOAD 0x00000002 2272 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2273 #define BGE_DRV_STATE_WOL 0x00000003 2274 #define BGE_DRV_STATE_SUSPEND 0x00000004 2275 2276 2277 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2278 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2279 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2280 2281 2282 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2283 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2284 2285 2286 /* 2287 * RX-RISC event register 2288 */ 2289 #define RX_RISC_EVENT_REG 0x6810 2290 #define RRER_ASF_EVENT 0x4000 2291 2292 #endif /* BGE_IPMI_ASF */ 2293 2294 /* APE registers. Accessible through BAR1 */ 2295 #define BGE_APE_GPIO_MSG 0x0008 2296 #define BGE_APE_GPIO_MSG_SHIFT 4 2297 #define BGE_APE_EVENT 0x000c 2298 #define APE_EVENT_1 0x00000001 2299 #define BGE_APE_LOCK_REQ 0x002c 2300 #define APE_LOCK_REQ_DRIVER 0x00001000 2301 #define BGE_APE_LOCK_GRANT 0x004c 2302 #define APE_LOCK_GRANT_DRIVER 0x00001000 2303 #define BGE_APE_STICKY_TMR 0x00b0 2304 2305 /* APE shared memory. Accessible through BAR1 */ 2306 #define BGE_APE_SHMEM_BASE 0x4000 2307 #define BGE_APE_SEG_SIG 0x4000 2308 #define APE_SEG_SIG_MAGIC 0x41504521 2309 #define BGE_APE_FW_STATUS 0x400c 2310 #define APE_FW_STATUS_READY 0x00000100 2311 #define BGE_APE_FW_FEATURES 0x4010 2312 #define BGE_APE_FW_FEATURE_NCSI 0x00000002 2313 #define BGE_APE_FW_VERSION 0x4018 2314 #define APE_FW_VERSION_MAJMSK 0xff000000 2315 #define APE_FW_VERSION_MAJSFT 24 2316 #define APE_FW_VERSION_MINMSK 0x00ff0000 2317 #define APE_FW_VERSION_MINSFT 16 2318 #define APE_FW_VERSION_REVMSK 0x0000ff00 2319 #define APE_FW_VERSION_REVSFT 8 2320 #define APE_FW_VERSION_BLDMSK 0x000000ff 2321 #define BGE_APE_SEG_MSG_BUF_OFF 0x401c 2322 #define BGE_APE_SEG_MSG_BUF_LEN 0x4020 2323 #define BGE_APE_HOST_SEG_SIG 0x4200 2324 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2325 #define BGE_APE_HOST_SEG_LEN 0x4204 2326 #define APE_HOST_SEG_LEN_MAGIC 0x00000020 2327 #define BGE_APE_HOST_INIT_COUNT 0x4208 2328 #define BGE_APE_HOST_DRIVER_ID 0x420c 2329 #define APE_HOST_DRIVER_ID_SOLARIS 0xf4000000 2330 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2331 (APE_HOST_DRIVER_ID_SOLARIS | (maj & 0xff) << 16 | (min & 0xff) << 8) 2332 #define BGE_APE_HOST_BEHAVIOR 0x4210 2333 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2334 #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2335 #define APE_HOST_HEARTBEAT_INT_DISABLE 0 2336 #define APE_HOST_HEARTBEAT_INT_5SEC 5000 2337 #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2338 #define BGE_APE_HOST_DRVR_STATE 0x421c 2339 #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2340 #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2341 #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2342 #define BGE_APE_HOST_WOL_SPEED 0x4224 2343 #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2344 2345 #define BGE_APE_EVENT_STATUS 0x4300 2346 2347 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2348 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2349 #define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600 2350 #define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700 2351 #define APE_EVENT_STATUS_STATE_START 0x00010000 2352 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2353 #define APE_EVENT_STATUS_STATE_WOL 0x00030000 2354 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2355 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2356 2357 #define BGE_APE_PER_LOCK_REQ 0x8400 2358 #define APE_LOCK_PER_REQ_DRIVER 0x00001000 2359 #define BGE_APE_PER_LOCK_GRANT 0x8420 2360 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2361 2362 /* APE convenience enumerations. */ 2363 #define BGE_APE_LOCK_PHY0 0 2364 #define BGE_APE_LOCK_GRC 1 2365 #define BGE_APE_LOCK_PHY1 2 2366 #define BGE_APE_LOCK_PHY2 3 2367 #define BGE_APE_LOCK_MEM 4 2368 #define BGE_APE_LOCK_PHY3 5 2369 #define BGE_APE_LOCK_GPIO 7 2370 2371 #ifdef __cplusplus 2372 } 2373 #endif 2374 2375 #endif /* _BGE_HW_H */ 2376