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Searched refs:REG_X2APIC_BASE_MSR (Results 1 – 3 of 3) sorted by relevance

/titanic_41/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_regops.c157 i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff); in local_x2apic_read()
167 tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)); in local_x2apic_write()
173 wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp); in local_x2apic_write()
179 return (rdmsr(REG_X2APIC_BASE_MSR + (APIC_TASK_REG >> 2))); in get_local_x2apic_pri()
191 wrmsr((REG_X2APIC_BASE_MSR + (APIC_INT_CMD1 >> 2)), in local_x2apic_write_int_cmd()
/titanic_41/usr/src/uts/intel/sys/
H A Dx86_archext.h249 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ macro
/titanic_41/usr/src/uts/i86pc/sys/
H A Dapic.h190 wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)