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Searched refs:REG_WR (Results 1 – 25 of 26) sorted by relevance

12

/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_init_reset.c53 …REG_WR(pdev,(PORT_ID(pdev) ? PXP2_REG_PSWRQ_##blk##1_L2P: PXP2_REG_PSWRQ_##blk##0_L2P),((last)<<10…
55 REG_WR(pdev,PXP2_REG_RQ_##blk##_FIRST_ILT,(first)); \
56 REG_WR(pdev,PXP2_REG_RQ_##blk##_LAST_ILT,(last)); \
286 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in lm_cleanup_after_flr()
367 REG_WR(PFDEV(pdev),XSDM_REG_OPERATION_GEN, final_cleanup.command); in lm_cleanup_after_flr()
555 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in lm_cleanup_after_flr()
632 … REG_WR(pdev,(GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET),MISC_REGISTERS_RESET_REG_1_RST_RBCP); in rbc_reset_workaround()
715 REG_WR( pdev, reg_arr_ptr[idx], 0 ); in lm_reset_path()
746 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_CLEAR, reg_1_clear ); in lm_reset_path()
756 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, reg_2_clear); in lm_reset_path()
[all …]
H A Dlm_hw_attn.c144 REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0); in enable_blocks_attention()
147 REG_WR(pdev,PXP_REG_PXP_INT_MASK_1, (PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS in enable_blocks_attention()
151 REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0); in enable_blocks_attention()
157 REG_WR(pdev,BRB1_REG_BRB1_INT_MASK ,0xFC00); in enable_blocks_attention()
159 REG_WR(pdev,QM_REG_QM_INT_MASK ,0); in enable_blocks_attention()
160 REG_WR(pdev,TM_REG_TM_INT_MASK ,0); in enable_blocks_attention()
161 REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_0 ,0); in enable_blocks_attention()
162 REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_1 ,0); in enable_blocks_attention()
163 REG_WR(pdev,XCM_REG_XCM_INT_MASK ,0); in enable_blocks_attention()
166 REG_WR(pdev,USDM_REG_USDM_INT_MASK_0 ,0); in enable_blocks_attention()
[all …]
H A Dlm_er.c94 REG_WR(pdev, MISC_REG_AEU_GENERAL_MASK, val); in lm_er_disable_close_the_gate()
106 REG_WR(pdev, PXP_REG_HST_DISCARD_DOORBELLS, enable_bit); in lm_er_set_234_gates()
109 REG_WR(pdev, PXP_REG_HST_DISCARD_INTERNAL_WRITES, enable_bit); in lm_er_set_234_gates()
116 REG_WR(pdev, IGU_REG_BLOCK_CONFIGURATION, val); in lm_er_set_234_gates()
129 REG_WR(pdev, PXP2_REG_RD_START_INIT, 0); in lm_er_pxp_prep()
130 REG_WR(pdev, PXP2_REG_RQ_RBC_DONE, 0); in lm_er_pxp_prep()
189 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in lm_er_process_kill_chip_reset()
192 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in lm_er_process_kill_chip_reset()
195 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2); in lm_er_process_kill_chip_reset()
197 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in lm_er_process_kill_chip_reset()
[all …]
H A Dlm_nvram.c69 REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port_num )); in acquire_nvram_lock()
117 REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port_num)); in release_nvram_lock()
155 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
158 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WREN);
198 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
201 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WRDI);
240 …REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_EN… in enable_nvram_access()
262 …REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val & ~(MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_… in disable_nvram_access()
294 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in nvram_read_dword()
297 REG_WR(pdev, MCP_REG_MCPR_NVM_ADDR, offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE); in nvram_read_dword()
[all …]
H A Dlm_hw_access.c394 REG_WR(pdev,MISC_REG_SPIO_INT, val ) ; in lm_setup_fan_failure_detection()
399 REG_WR(pdev,MISC_REG_SPIO_EVENT_EN, val ) ; in lm_setup_fan_failure_detection()
584 REG_WR(pdev, MISC_REG_GPIO, gpio_reg); in lm_gpio_write()
648 REG_WR(pdev, MISC_REG_GPIO, gpio_reg); in lm_gpio_mult_write()
715 REG_WR(pdev, MISC_REG_GPIO_INT, gpio_reg); in lm_gpio_int_write()
776 REG_WR(pdev, MISC_REG_SPIO, reg_val); in lm_spio_read()
842 REG_WR(pdev, MISC_REG_SPIO, reg_val); in lm_spio_write()
869 REG_WR(pdev, NIG_REG_LED_MODE_P0, mode_idx); in lm_set_led_mode()
872 REG_WR(pdev, NIG_REG_LED_MODE_P1, mode_idx); in lm_set_led_mode()
941 REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val); in lm_override_led_value()
[all …]
H A Dlm_power.c129 REG_WR( pdev, reg_len, val ) ; in init_nwuf_57710()
132 REG_WR( pdev, reg_crc, val ) ; in init_nwuf_57710()
255 REG_WR( pdev, offset, nwuf_reg_value ) ; in lm_set_d3_nwuf()
277 REG_WR( pdev, offset, nwuf_reg_value ) ; in lm_set_d3_nwuf()
321 REG_WR(pdev, emac_base+ offset , b_enable_mpkt ? val:0); in lm_set_d3_mpkt()
326 REG_WR(pdev, emac_base+ offset, b_enable_mpkt ? val:0); in lm_set_d3_mpkt()
379 REG_WR(pdev, emac.emac_mode, val); in set_d0_power_state()
383 REG_WR(pdev, rpm.rpm_config, val); in set_d0_power_state()
485 REG_WR(pdev, pcicfg_device_control_offset, pf0_pcie_status_control); in lm_pcie_state_restore_for_d0()
H A Dlm_sb.c102 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WOMASK(pdev)); in lm_get_interrupt_status_wo_mask()
118 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WMASK(pdev)); in lm_get_interrupt_status()
570 REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_L + 8*PORT_ID(pdev), host_sb_addr->as_u32.low); in init_hc_attn_status_block()
571 REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_H + 8*PORT_ID(pdev), host_sb_addr->as_u32.high); in init_hc_attn_status_block()
580 REG_WR(pdev, IGU_REG_ATTN_MSG_ADDR_L, host_sb_addr->as_u32.low); in init_igu_attn_status_block()
581 REG_WR(pdev, IGU_REG_ATTN_MSG_ADDR_H, host_sb_addr->as_u32.high); in init_igu_attn_status_block()
896 REG_WR(pdev, HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_INT_ACK, result); in lm_int_hc_ack_sb()
929 REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, cmd_data.sb_id_and_flags); in lm_int_igu_ack_sb()
946 REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags); in lm_int_igu_ack_sb()
947 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data); in lm_int_igu_ack_sb()
[all …]
H A Dlm_phy.c82 REG_WR(cb, reg_addr, val); in elink_cb_reg_write()
202 REG_WR(cb, MISC_REG_AEU_GENERAL_ATTN_12 + FUNC_ID((lm_device_t *)cb)*sizeof(u32), 1); in elink_cb_notify_link_changed()
249 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1); in lm_mwrite()
258 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); in lm_mwrite()
267 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,tmp); in lm_mwrite()
298 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); in lm_mwrite()
300 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + in lm_mwrite()
323 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1); in lm_mread()
332 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val); in lm_mread()
341 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,val); in lm_mread()
[all …]
H A Dlm_mcp.c151 REG_WR(pdev, shmem + validity_offset, 0); in lm_reset_mcp_prep()
240 REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15 + 4, 0xffffffff); in lm_reset_mcp()
246 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, in lm_reset_mcp()
253 REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15, 0xffffffff); in lm_reset_mcp()
284 REG_WR(pdev, GRCBASE_MCP + 0x9c, val_wr); in acquire_split_alr()
326 REG_WR(pdev, GRCBASE_MCP + 0x9c, val); in release_split_alr()
H A Dlm_pf.c381 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0);
382 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0);
383 REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0);
389 REG_WR(pf_dev, 0x24d8, 1<<29);
391 REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev)));
973 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0); in lm_pf_clear_vf_igu_blocks()
989 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0); in lm_pf_release_vf_igu_block()
1013 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, value); in lm_pf_acquire_vf_igu_block()
1181 …REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(LM_FW_VF_DHC_QZONE_ID(vf_inf… in lm_pf_update_vf_ndsb()
H A Dbnxe_hw_debug.c84 REG_WR(pdev,TM_REG_EN_LINEAR0_TIMER, 0); in lm_disable_timer()
104 REG_WR(pdev,TM_REG_EN_LINEAR1_TIMER, 0); in lm_disable_timer()
134 REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER,1); in lm_enable_timer()
137 REG_WR(pdev, TM_REG_EN_LINEAR1_TIMER,1); in lm_enable_timer()
208 REG_WR(pdev,PXP2_REG_RQ_HOQ_RAM_RD_REQ,vq); in _vq_hoq()
H A Dlm_niv.c373 REG_WR(pdev, output_offset + bytes_written, *field_ptr); in lm_niv_stats_get()
H A Dlm_dmae.c808 REG_WR( pdev, in lm_dmae_post_command()
813 REG_WR(pdev, lm_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE) ; in lm_dmae_post_command()
H A Dlm_dcbx.c4254 REG_WR(pdev, (admin_mib_offset + i) , *buff); in lm_dcbx_ie_admin_mib_updated_runtime()
4439 REG_WR(pdev, (offset + i) , *buff); in lm_dcbx_admin_mib_updated_init()
4487 REG_WR(pdev, (offest+ i) , *buff);//Change to write in lm_dcbx_init_lldp_updated_params()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_init_ops.h43 REG_WR(pdev, addr + i*4, data[i]); in ecore_init_str_wr()
275 REG_WR(pdev, addr, op->write.val); in ecore_init_block()
519 REG_WR(pdev, read_arb_addr[i].l, read_arb_data[i][r_order].l); in ecore_init_pxp_arb()
520 REG_WR(pdev, read_arb_addr[i].add, in ecore_init_pxp_arb()
522 REG_WR(pdev, read_arb_addr[i].ubound, in ecore_init_pxp_arb()
530 REG_WR(pdev, write_arb_addr[i].l, in ecore_init_pxp_arb()
533 REG_WR(pdev, write_arb_addr[i].add, in ecore_init_pxp_arb()
536 REG_WR(pdev, write_arb_addr[i].ubound, in ecore_init_pxp_arb()
541 REG_WR(pdev, write_arb_addr[i].l, in ecore_init_pxp_arb()
545 REG_WR(pdev, write_arb_addr[i].add, in ecore_init_pxp_arb()
[all …]
H A Decore_init.h210 REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
234 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr, in ecore_disable_blocks_parity()
259 REG_WR(pdev, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
260 REG_WR(pdev, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
261 REG_WR(pdev, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
262 REG_WR(pdev, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
292 REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); in ecore_clear_blocks_parity()
303 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr, in ecore_enable_blocks_parity()
H A Decore_common.h51 REG_WR(pdev, addr + (i * 4), data[i]); in __storm_memset_struct()
H A Decore_sp_verbs.c1118 REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : in ecore_set_mac_in_nig()
3675 REG_WR(pdev, MC_HASH_OFFSET(pdev, i), mc_filter[i]); in ecore_mcast_setup_e1h()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/
H A Dlm_vf.c182 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0); in lm_vf_dis()
183 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0); in lm_vf_dis()
184 REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0); in lm_vf_dis()
190 REG_WR(pf_dev, 0x24d8, 1<<29); in lm_vf_dis()
192 REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev))); in lm_vf_dis()
355 …REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + XSTORM_VF_SPQ_DATA_OFFSET(ABS_VFID(pdev)) + i*sizeof(u32… in lm_vf_chip_init()
358 …REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(ABS_VFID(pdev))),pdev->s… in lm_vf_chip_init()
359 …REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(ABS_VFID(pdev)) + 4),pde… in lm_vf_chip_init()
360 …REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PROD_OFFSET(ABS_VFID(pdev))),pdev->sq_inf… in lm_vf_chip_init()
459 REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,0); in lm_vf_enable_vf()
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c68 #define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val) macro
70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val)
350 REG_WR(cb, reg, val); in elink_bits_en()
359 REG_WR(cb, reg, val); in elink_bits_dis()
388 REG_WR(cb, params->lfa_base + in elink_check_lfa()
509 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in elink_get_epio()
531 REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in elink_set_epio()
535 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in elink_set_epio()
584 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in elink_ets_e2e3a0_disabled()
593 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in elink_ets_e2e3a0_disabled()
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A Dbnxe_fw_funcs.c66 REG_WR(pdev, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); in ecore_map_q_cos()
71 REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
76 REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
87 REG_WR(pdev, reg_addr, reg_bit_map); in ecore_map_q_cos()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c209 …REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + XSTORM_VF_SPQ_DATA_OFFSET(vf_info->abs_vf_id) + i*sizeof… in lm_pf_vf_fill_init_vf_response()
212 … REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vf_info->abs_vf_id)),0); in lm_pf_vf_fill_init_vf_response()
213 …REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vf_info->abs_vf_id)) + 4… in lm_pf_vf_fill_init_vf_response()
214 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PROD_OFFSET(vf_info->abs_vf_id)),0); in lm_pf_vf_fill_init_vf_response()
219 REG_WR(PFDEV(pdev), reg, val); in lm_pf_vf_fill_init_vf_response()
558 REG_WR(PFDEV(pdev), reg, val); in lm_pf_vf_fill_close_vf_response()
2939 REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in lm_pf_enable_vf_igu_int()
2940 REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in lm_pf_enable_vf_igu_int()
2941 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0); in lm_pf_enable_vf_igu_int()
2942 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_MSB, 0); in lm_pf_enable_vf_igu_int()
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h180 REG_WR((_pdev), 0x2000, kuku); \
184 #define LM_GENERAL_ATTN_INTERRUPT_SET(_pdev,_func) REG_WR((_pdev),MISC_REG_AEU_GENER…
4091 #define REG_WR(_pdev, _reg_offset, _val) \ macro
4097 #define VF_REG_WR(_pdev, _reg_offset, _val) REG_WR(_pdev, _reg_offset, _val)
4106 #define REG_WR(_pdev, _reg_offset, _val) \ macro
4153 #define REG_WR(_pdev, _reg_offset, _val) \ macro
4194 #define REG_WR(_pdev, _reg_offset, _val) \ macro
/titanic_41/usr/src/uts/common/io/bnxe/
H A Dbnxe.h1026 REG_WR((lmdev), 0x2000, (data)); \
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/
H A Dlm_l4sp.c993 REG_WR(pdev, max_reg, ack_frequency); in _lm_set_ofld_params_xstorm_common()
1002 REG_WR(pdev, tmr_reg, delayed_ack_ticks); in _lm_set_ofld_params_xstorm_common()

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