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Searched refs:REG_SPI4_ING_SETUP2 (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dvsc7321.c120 { REG_SPI4_ING_SETUP2, 0x04040004 },
H A Dvsc7321_reg.h131 #define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */ macro
H A Dvsc7326_reg.h137 #define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */ macro
H A Dvsc7326.c123 { REG_SPI4_ING_SETUP2, 0x08080004 },