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Searched refs:REG_READ (Results 1 – 7 of 7) sorted by relevance

/titanic_41/usr/src/uts/common/io/arn/
H A Darn_calib.c112 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ath9k_hw_do_getnf()
114 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ath9k_hw_do_getnf()
123 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), in ath9k_hw_do_getnf()
126 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), in ath9k_hw_do_getnf()
136 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), in ath9k_hw_do_getnf()
146 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), in ath9k_hw_do_getnf()
149 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), in ath9k_hw_do_getnf()
159 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), in ath9k_hw_do_getnf()
162 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), in ath9k_hw_do_getnf()
172 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), in ath9k_hw_do_getnf()
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H A Darn_ani.c237 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); in ath9k_hw_update_mibstats()
238 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); in ath9k_hw_update_mibstats()
239 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); in ath9k_hw_update_mibstats()
240 stats->rts_good += REG_READ(ah, AR_RTS_OK); in ath9k_hw_update_mibstats()
241 stats->beacons += REG_READ(ah, AR_BEACON_CNT); in ath9k_hw_update_mibstats()
470 txFrameCount = REG_READ(ah, AR_TFCNT); in ath9k_hw_ani_get_listen_time()
471 rxFrameCount = REG_READ(ah, AR_RFCNT); in ath9k_hw_ani_get_listen_time()
472 cycleCount = REG_READ(ah, AR_CCCNT); in ath9k_hw_ani_get_listen_time()
601 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); in ath9k_hw_ani_monitor()
602 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); in ath9k_hw_ani_monitor()
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H A Darn_mac.c71 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof (uint32_t))); in ath9k_hw_dmaRegDump()
120 REG_READ(ah, AR_OBS_BUS_1))); in ath9k_hw_dmaRegDump()
122 "AR_CR 0x%x \n", REG_READ(ah, AR_CR))); in ath9k_hw_dmaRegDump()
128 return (REG_READ(ah, AR_QTXDP(q))); in ath9k_hw_gettxbuf()
155 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
158 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
178 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
216 tsfLow = REG_READ(ah, AR_TSF_L32); in ath9k_hw_stoptxdma()
222 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) in ath9k_hw_stoptxdma()
842 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
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H A Darn_hw.c120 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
127 reg, REG_READ(ah, reg), mask, val)); in ath9k_hw_wait()
304 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
307 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
332 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; in ath9k_hw_get_radiorev()
372 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
376 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
390 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
767 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in ath9k_hw_do_attach()
1044 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ath9k_hw_init_bb()
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H A Darn_phy.c69 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ath9k_hw_set_channel()
123 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ath9k_hw_ar9280_set_channel()
134 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ath9k_hw_ar9280_set_channel()
448 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38) in ath9k_hw_decrease_chain_power()
449 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38)); in ath9k_hw_decrease_chain_power()
H A Darn_eeprom.c66 regVal = REG_READ(ah, reg) & ~mask; in ath9k_hw_analog_shift_rmw()
133 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); in ath9k_hw_eeprom_read()
141 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), in ath9k_hw_eeprom_read()
1054 (uint16_t)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_def_power_cal_table()
1179 pdGainOverlap_t2 = (uint16_t)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_4k_power_cal_table()
2231 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_eeprom_set_def_board_values()
2273 (REG_READ(ah, in ath9k_hw_eeprom_set_def_board_values()
2283 (REG_READ(ah, in ath9k_hw_eeprom_set_def_board_values()
2305 (REG_READ(ah, in ath9k_hw_eeprom_set_def_board_values()
2314 (REG_READ(ah, in ath9k_hw_eeprom_set_def_board_values()
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H A Darn_ath9k.h613 #define REG_READ(_ah, _reg) arn_ioread32((_ah), (_reg)) macro
621 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
624 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
626 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
628 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)