Searched refs:RADEON_READ (Results 1 – 4 of 4) sorted by relevance
830 return (RADEON_READ(RADEON_CLOCK_CNTL_DATA)); in RADEON_READ_PLL()836 return (RADEON_READ(RADEON_PCIE_DATA)); in RADEON_READ_PCIE()843 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); in radeon_status()845 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); in radeon_status()847 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); in radeon_status()849 (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); in radeon_status()851 (unsigned int)RADEON_READ(RADEON_AIC_STAT)); in radeon_status()853 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); in radeon_status()855 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); in radeon_status()857 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); in radeon_status()[all …]
46 uint32_t irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask; in radeon_acknowledge_irqs()143 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) in radeon_wait_irq()149 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); in radeon_wait_irq()350 flag = RADEON_READ(RADEON_GEN_INT_CNTL); in radeon_vblank_crtc_get()
163 RADEON_READ(RADEON_CP_RB_RPTR))499 RADEON_READ(RADEON_SCRATCH_REG0 + 4*(x)))1006 #define RADEON_READ(reg) \ macro1166 RADEON_READ(RADEON_CP_RB_RPTR); \
2266 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | in radeon_do_init_pageflip()2269 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | in radeon_do_init_pageflip()