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Searched refs:PX_ERR_PIL (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_pec.c184 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_add_intr()
200 PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
208 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_add_intr()
222 px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL, in px_pec_msg_add_intr()
275 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_rem_intr()
281 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, in px_pec_msg_rem_intr()
291 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_rem_intr()
297 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG); in px_pec_msg_rem_intr()
H A Dpx_fm.h32 #define PX_ERR_PIL 14 macro
/titanic_41/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c2105 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, in px_err_add_intr()
2123 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); in px_err_rem_intr()
2209 VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL, in px_cb_add_intr()
2301 VERIFY(rem_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL) == 0); in px_cb_rem_intr()
/titanic_41/usr/src/uts/sun4v/io/px/
H A Dpx_lib4v.c1943 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, in px_err_add_intr()
1964 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); in px_err_rem_intr()
1983 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, in px_cb_add_intr()