Searched refs:PXP2_REG_RQ_DRAM_ALIGN (Results 1 – 2 of 2) sorted by relevance
2748 REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN,1); /* for 128B cache line value should be 2 */ in init_pxp2_common()
13536 #define PXP2_REG_RQ_DRAM_ALIGN … macro