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Searched refs:PUTCSR (Results 1 – 8 of 8) sorted by relevance

/titanic_41/usr/src/uts/common/io/efe/
H A Defe.c486 PUTCSR(efep, CSR_GENCTL, GENCTL_RESET); in efe_quiesce()
489 PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN); in efe_quiesce()
502 PUTCSR(efep, CSR_MMCTL, MMCTL_READ | in efe_mii_read()
521 PUTCSR(efep, CSR_MMDATA, data); in efe_mii_write()
523 PUTCSR(efep, CSR_MMCTL, MMCTL_WRITE | in efe_mii_write()
832 PUTCSR(efep, CSR_COMMAND, COMMAND_TXQUEUED); in efe_m_tx()
890 PUTCSR(efep, CSR_INTSTAT, status); in efe_intr()
901 PUTCSR(efep, CSR_COMMAND, COMMAND_RXQUEUED); in efe_intr()
956 PUTCSR(efep, CSR_GENCTL, val); in efe_init()
957 PUTCSR(efep, CSR_PBLCNT, BURSTLEN); in efe_init()
[all …]
H A Defe.h316 #define PUTCSR(efep, reg, val) \ macro
321 PUTCSR(efep, reg, (GETCSR(efep, reg) & ~(bit)))
324 PUTCSR(efep, reg, (GETCSR(efep, reg) | (bit)))
/titanic_41/usr/src/uts/common/io/afe/
H A Dafe.c714 PUTCSR(afep, CSR_PAR0, pa0); in afe_setrxfilt()
715 PUTCSR(afep, CSR_PAR1, pa1); in afe_setrxfilt()
729 PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]); in afe_setrxfilt()
730 PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]); in afe_setrxfilt()
923 PUTCSR(afep, CSR_PAR, par); in afe_initialize()
937 PUTCSR(afep, CSR_NAR, nar); in afe_initialize()
957 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); in afe_sromwidth()
959 PUTCSR(afep, CSR_SPR, eeread); in afe_sromwidth()
965 PUTCSR(afep, CSR_SPR, eeread | val); in afe_sromwidth()
967 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); in afe_sromwidth()
[all …]
H A Dafeimpl.h295 #define PUTCSR(afep, reg, val) \ macro
301 #define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val))
303 #define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val))
/titanic_41/usr/src/uts/common/io/mxfe/
H A Dmxfe.c780 PUTCSR(mxfep, CSR_PAR, par); in mxfe_initialize()
799 PUTCSR(mxfep, CSR_NAR, nar); in mxfe_initialize()
819 PUTCSR(mxfep, CSR_SPR, eeread & ~SPR_SROM_CHIP); in mxfe_sromwidth()
821 PUTCSR(mxfep, CSR_SPR, eeread); in mxfe_sromwidth()
826 PUTCSR(mxfep, CSR_SPR, eeread | val); in mxfe_sromwidth()
828 PUTCSR(mxfep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); in mxfe_sromwidth()
832 PUTCSR(mxfep, CSR_SPR, eeread); in mxfe_sromwidth()
835 PUTCSR(mxfep, CSR_SPR, eeread | SPR_SROM_CLOCK); in mxfe_sromwidth()
838 PUTCSR(mxfep, CSR_SPR, eeread); in mxfe_sromwidth()
842 PUTCSR(mxfep, CSR_SPR, eeread); in mxfe_sromwidth()
[all …]
H A Dmxfeimpl.h337 #define PUTCSR(mxfep, reg, val) \ macro
341 PUTCSR(mxfep, reg, GETCSR(mxfep, reg) | (val))
344 PUTCSR(mxfep, reg, GETCSR(mxfep, reg) & ~(val))
/titanic_41/usr/src/uts/common/sys/crypto/
H A Ddca.h748 #define PUTCSR(dca, reg, val) \ macro
752 PUTCSR(dca, reg, GETCSR(dca, reg) | val)
755 PUTCSR(dca, reg, GETCSR(dca, reg) & ~val)
/titanic_41/usr/src/uts/common/crypto/io/
H A Ddca.c774 PUTCSR(dca, CSR_DMACTL, DMACTL_BE32 | DMACTL_BE64); in dca_attach()
1035 PUTCSR(dca, CSR_DMACTL, DMACTL_BE32 | DMACTL_BE64); in dca_resume()
1084 PUTCSR(dca, CSR_DMACTL, DMACTL_RESET); in dca_reset()
1390 PUTCSR(dca, CSR_DMASTAT, status & DMASTAT_INTERRUPTS); in dca_intr()
2311 PUTCSR(dca, csr, workp->dw_mcr_paddr); in dca_schedule()