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Searched refs:PRB0_CTL (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/intel/io/drm/
H A Di915_gem.c859 I915_WRITE(PRB0_CTL, 0); in i965_reset()
865 I915_WRITE(PRB0_CTL, in i965_reset()
2769 I915_WRITE(PRB0_CTL, 0); in i915_gem_init_ringbuffer()
2782 I915_READ(PRB0_CTL), in i915_gem_init_ringbuffer()
2790 I915_READ(PRB0_CTL), in i915_gem_init_ringbuffer()
2796 I915_WRITE(PRB0_CTL, in i915_gem_init_ringbuffer()
2807 I915_READ(PRB0_CTL), in i915_gem_init_ringbuffer()
H A Di915_drv.h821 #define PRB0_CTL 0x0203c macro