xref: /titanic_41/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h (revision d478d0a82b5f273f7eac89c8df47960d9d22820b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at
9  * http://www.opensource.org/licenses/cddl1.txt.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2004-2012 Emulex. All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_MBOX_H
28 #define	_EMLXS_MBOX_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /* SLI 2/3 Mailbox defines */
35 
36 #define	MBOX_SIZE			256
37 #define	MBOX_EXTENSION_OFFSET		MBOX_SIZE
38 
39 #ifdef MBOX_EXT_SUPPORT
40 #define	MBOX_EXTENSION_SIZE		1024
41 #else
42 #define	MBOX_EXTENSION_SIZE		0
43 #endif /* MBOX_EXT_SUPPORT */
44 
45 
46 
47 /* ==== Mailbox Commands ==== */
48 #define	MBX_SHUTDOWN			0x00	/* terminate testing */
49 #define	MBX_LOAD_SM			0x01
50 #define	MBX_READ_NV			0x02
51 #define	MBX_WRITE_NV			0x03
52 #define	MBX_RUN_BIU_DIAG		0x04
53 #define	MBX_INIT_LINK			0x05
54 #define	MBX_DOWN_LINK			0x06
55 #define	MBX_CONFIG_LINK			0x07
56 #define	MBX_PART_SLIM			0x08
57 #define	MBX_CONFIG_RING			0x09
58 #define	MBX_RESET_RING			0x0A
59 #define	MBX_READ_CONFIG			0x0B
60 #define	MBX_READ_RCONFIG		0x0C
61 #define	MBX_READ_SPARM			0x0D
62 #define	MBX_READ_STATUS			0x0E
63 #define	MBX_READ_RPI			0x0F
64 #define	MBX_READ_XRI			0x10
65 #define	MBX_READ_REV			0x11
66 #define	MBX_READ_LNK_STAT		0x12
67 #define	MBX_REG_LOGIN			0x13
68 #define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
69 #define	MBX_UNREG_RPI			0x14  /* SLI4 */
70 #define	MBX_READ_LA			0x15
71 #define	MBX_CLEAR_LA			0x16
72 #define	MBX_DUMP_MEMORY			0x17
73 #define	MBX_DUMP_CONTEXT		0x18
74 #define	MBX_RUN_DIAGS			0x19
75 #define	MBX_RESTART			0x1A
76 #define	MBX_UPDATE_CFG			0x1B
77 #define	MBX_DOWN_LOAD			0x1C
78 #define	MBX_DEL_LD_ENTRY		0x1D
79 #define	MBX_RUN_PROGRAM			0x1E
80 #define	MBX_SET_MASK			0x20
81 #define	MBX_SET_VARIABLE		0x21
82 #define	MBX_UNREG_D_ID			0x23
83 #define	MBX_KILL_BOARD			0x24
84 #define	MBX_CONFIG_FARP			0x25
85 #define	MBX_BEACON			0x2A
86 #define	MBX_READ_VPI			0x2B
87 #define	MBX_CONFIG_MSIX			0x30
88 #define	MBX_HEARTBEAT			0x31
89 #define	MBX_WRITE_VPARMS		0x32
90 #define	MBX_ASYNC_EVENT			0x33
91 
92 #define	MBX_READ_EVENT_LOG_STATUS	0x37
93 #define	MBX_READ_EVENT_LOG		0x38
94 #define	MBX_WRITE_EVENT_LOG		0x39
95 #define	MBX_NV_LOG			0x3A
96 #define	MBX_PORT_CAPABILITIES		0x3B
97 #define	MBX_IOV_CONTROL			0x3C
98 #define	MBX_IOV_MBX			0x3D
99 
100 
101 #define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
102 #define	MBX_LOAD_AREA			0x81
103 #define	MBX_RUN_BIU_DIAG64		0x84
104 #define	MBX_GET_DEBUG			0x86
105 #define	MBX_CONFIG_PORT			0x88
106 #define	MBX_READ_SPARM64		0x8D
107 #define	MBX_READ_RPI64			0x8F
108 #define	MBX_CONFIG_MSI			0x90
109 #define	MBX_REG_LOGIN64			0x93 /* SLI2/3 */
110 #define	MBX_REG_RPI			0x93 /* SLI4 */
111 #define	MBX_READ_LA64			0x95 /* SLI2/3 */
112 #define	MBX_READ_TOPOLOGY		0x95 /* SLI4 */
113 #define	MBX_REG_VPI			0x96 /* NPIV */
114 #define	MBX_UNREG_VPI			0x97 /* NPIV */
115 #define	MBX_FLASH_WR_ULA		0x98
116 #define	MBX_SET_DEBUG			0x99
117 #define	MBX_SLI_CONFIG			0x9B
118 #define	MBX_LOAD_EXP_ROM		0x9C
119 #define	MBX_REQUEST_FEATURES		0x9D
120 #define	MBX_RESUME_RPI			0x9E
121 #define	MBX_REG_VFI			0x9F
122 #define	MBX_REG_FCFI			0xA0
123 #define	MBX_UNREG_VFI			0xA1
124 #define	MBX_UNREG_FCFI			0xA2
125 #define	MBX_INIT_VFI			0xA3
126 #define	MBX_INIT_VPI			0xA4
127 #define	MBX_ACCESS_VDATA		0xA5
128 #define	MBX_MAX_CMDS			0xA6
129 
130 
131 /*
132  * Define Status
133  */
134 #define	MBX_SUCCESS			0x0
135 #define	MBX_FAILURE			0x1
136 #define	MBXERR_NUM_IOCBS		0x2
137 #define	MBXERR_IOCBS_EXCEEDED		0x3
138 #define	MBXERR_BAD_RING_NUMBER		0x4
139 #define	MBXERR_MASK_ENTRIES_RANGE	0x5
140 #define	MBXERR_MASKS_EXCEEDED		0x6
141 #define	MBXERR_BAD_PROFILE		0x7
142 #define	MBXERR_BAD_DEF_CLASS		0x8
143 #define	MBXERR_BAD_MAX_RESPONDER	0x9
144 #define	MBXERR_BAD_MAX_ORIGINATOR	0xA
145 #define	MBXERR_RPI_REGISTERED		0xB
146 #define	MBXERR_RPI_FULL			0xC
147 #define	MBXERR_NO_RESOURCES		0xD
148 #define	MBXERR_BAD_RCV_LENGTH		0xE
149 #define	MBXERR_DMA_ERROR		0xF
150 #define	MBXERR_NOT_SUPPORTED		0x10
151 #define	MBXERR_UNSUPPORTED_FEATURE	0x11
152 #define	MBXERR_UNKNOWN_COMMAND		0x12
153 #define	MBXERR_BAD_IP_BIT		0x13
154 #define	MBXERR_BAD_PCB_ALIGN		0x14
155 #define	MBXERR_BAD_HBQ_ID		0x15
156 #define	MBXERR_BAD_HBQ_STATE		0x16
157 #define	MBXERR_BAD_HBQ_MASK_NUM		0x17
158 #define	MBXERR_BAD_HBQ_MASK_SUBSET	0x18
159 #define	MBXERR_HBQ_CREATE_FAIL		0x19
160 #define	MBXERR_HBQ_EXISTING		0x1A
161 #define	MBXERR_HBQ_RSPRING_FULL		0x1B
162 #define	MBXERR_HBQ_DUP_MASK		0x1C
163 #define	MBXERR_HBQ_INVAL_GET_PTR	0x1D
164 #define	MBXERR_BAD_HBQ_SIZE		0x1E
165 #define	MBXERR_BAD_HBQ_ORDER		0x1F
166 #define	MBXERR_INVALID_ID		0x20
167 
168 #define	MBXERR_INVALID_VFI		0x30
169 
170 #define	MBXERR_FLASH_WRITE_FAILED	0x100
171 
172 #define	MBXERR_INVALID_LINKSPEED	0x500
173 
174 #define	MBXERR_BAD_REDIRECT		0x900
175 #define	MBXERR_RING_ALREADY_CONFIG	0x901
176 
177 #define	MBXERR_RING_INACTIVE		0xA00
178 
179 #define	MBXERR_RPI_INACTIVE		0xF00
180 
181 #define	MBXERR_NO_ACTIVE_XRI		0x1100
182 #define	MBXERR_XRI_NOT_ACTIVE		0x1101
183 
184 #define	MBXERR_RPI_INUSE		0x1400
185 
186 #define	MBXERR_NO_LINK_ATTENTION	0x1500
187 
188 #define	MBXERR_INVALID_SLI_MODE		0x8800
189 #define	MBXERR_INVALID_HOST_PTR		0x8801
190 #define	MBXERR_CANT_CFG_SLI_MODE	0x8802
191 #define	MBXERR_BAD_OVERLAY		0x8803
192 #define	MBXERR_INVALID_FEAT_REQ		0x8804
193 
194 #define	MBXERR_CONFIG_CANT_COMPLETE	0x88FF
195 
196 #define	MBXERR_DID_ALREADY_REGISTERED	0x9600
197 #define	MBXERR_DID_INCONSISTENT		0x9601
198 #define	MBXERR_VPI_TOO_LARGE		0x9603
199 
200 #define	MBXERR_STILL_ASSOCIATED		0x9700
201 
202 #define	MBXERR_INVALID_VF_STATE		0x9F00
203 #define	MBXERR_VFI_ALREADY_REGISTERED	0x9F02
204 #define	MBXERR_VFI_TOO_LARGE		0x9F03
205 
206 #define	MBXERR_LOAD_FW_FAILED		0xFFFE
207 #define	MBXERR_FIND_FW_FAILED		0xFFFF
208 
209 /* Driver special codes */
210 #define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
211 #define	MBX_NONEMBED_ERROR		0xF9
212 #define	MBX_OVERTEMP_ERROR		0xFA
213 #define	MBX_HARDWARE_ERROR		0xFB
214 #define	MBX_DRVR_ERROR			0xFC
215 #define	MBX_BUSY			0xFD
216 #define	MBX_TIMEOUT			0xFE
217 #define	MBX_NOT_FINISHED		0xFF
218 
219 /*
220  * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
221  */
222 #define	MBX_POLL	0x01	/* poll mailbox till command done, */
223 				/* then return */
224 #define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
225 				/* wakes thread up */
226 #define	MBX_WAIT	0x03	/* wait for comand done, then return */
227 #define	MBX_NOWAIT	0x04	/* issue command then return immediately */
228 #define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */
229 
230 
231 
232 /*
233  * Begin Structure Definitions for Mailbox Commands
234  */
235 
236 typedef struct revcompat
237 {
238 #ifdef EMLXS_BIG_ENDIAN
239 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
240 	uint32_t	ldcount:7;	/* For use by program load */
241 	uint32_t	kernel:4;	/* Kernel ID */
242 	uint32_t	kver:4;	/* Kernel compatibility version */
243 	uint32_t	SMver:4;	/* Sequence Manager version */
244 					/* 0 if none */
245 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
246 	uint32_t	BIUtype:4;	/* PCI = 0 */
247 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
248 #endif
249 #ifdef EMLXS_LITTLE_ENDIAN
250 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
251 	uint32_t	BIUtype:4;	/* PCI = 0 */
252 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
253 	uint32_t	SMver:4;	/* Sequence Manager version */
254 					/* 0 if none */
255 	uint32_t	kver:4;	/* Kernel compatibility version */
256 	uint32_t	kernel:4;	/* Kernel ID */
257 	uint32_t	ldcount:7;	/* For use by program load */
258 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
259 #endif
260 } REVCOMPAT;
261 
262 typedef struct id_word
263 {
264 #ifdef EMLXS_BIG_ENDIAN
265 	uint8_t		Type;
266 	uint8_t		Id;
267 	uint8_t		Ver;
268 	uint8_t		Rev;
269 #endif
270 #ifdef EMLXS_LITTLE_ENDIAN
271 	uint8_t		Rev;
272 	uint8_t		Ver;
273 	uint8_t		Id;
274 	uint8_t		Type;
275 #endif
276 	union
277 	{
278 		REVCOMPAT	cp;
279 		uint32_t	revcomp;
280 	} un;
281 } PROG_ID;
282 
283 typedef struct
284 {
285 #ifdef EMLXS_BIG_ENDIAN
286 	uint8_t		tval;
287 	uint8_t		tmask;
288 	uint8_t		rval;
289 	uint8_t		rmask;
290 #endif
291 #ifdef EMLXS_LITTLE_ENDIAN
292 	uint8_t		rmask;
293 	uint8_t		rval;
294 	uint8_t		tmask;
295 	uint8_t		tval;
296 #endif
297 } RR_REG;
298 
299 
300 /* Structure used for a HBQ entry */
301 typedef struct
302 {
303 	ULP_BDE64	bde;
304 	union UN_TAG
305 	{
306 		uint32_t	w;
307 		struct
308 		{
309 #ifdef EMLXS_BIG_ENDIAN
310 			uint32_t	HBQ_tag:4;
311 			uint32_t	HBQE_tag:28;
312 #endif
313 #ifdef EMLXS_LITTLE_ENDIAN
314 			uint32_t	HBQE_tag:28;
315 			uint32_t	HBQ_tag:4;
316 #endif
317 		} ext;
318 	} unt;
319 } HBQE_t;
320 
321 typedef struct
322 {
323 #ifdef EMLXS_BIG_ENDIAN
324 	uint8_t		tmatch;
325 	uint8_t		tmask;
326 	uint8_t		rctlmatch;
327 	uint8_t		rctlmask;
328 #endif
329 #ifdef EMLXS_LITTLE_ENDIAN
330 	uint8_t		rctlmask;
331 	uint8_t		rctlmatch;
332 	uint8_t		tmask;
333 	uint8_t		tmatch;
334 #endif
335 } HBQ_MASK;
336 
337 #define	EMLXS_MAX_HBQ_BUFFERS	4096
338 
339 typedef struct
340 {
341 	uint32_t	HBQ_num_mask;		/* number of mask entries in */
342 						/* port array */
343 	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
344 	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
345 	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
346 	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
347 						/* for LogEntry */
348 	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
349 						/* 7=logentry */
350 	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
351 						/* Ring0=b0001, ring2=b0100 */
352 	uint32_t	HBQ_id;			/* index of this hbq in ring */
353 						/* of HBQs[] */
354 	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
355 						/* use */
356 	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
357 	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
358 						/* from Port */
359 	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
360 						/* in list */
361 	MATCHMAP	*HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
362 	MATCHMAP	HBQ_host_buf;		/* HBQ host buffer for HBQEs */
363 	HBQ_MASK	HBQ_Masks[6];
364 
365 	union
366 	{
367 		uint32_t	allprofiles[12];
368 
369 		struct
370 		{
371 #ifdef EMLXS_BIG_ENDIAN
372 			uint32_t	seqlenoff:16;
373 			uint32_t	maxlen:16;
374 #endif
375 #ifdef EMLXS_LITTLE_ENDIAN
376 			uint32_t	maxlen:16;
377 			uint32_t	seqlenoff:16;
378 #endif
379 #ifdef EMLXS_BIG_ENDIAN
380 			uint32_t	rsvd1:28;
381 			uint32_t	seqlenbcnt:4;
382 #endif
383 #ifdef EMLXS_LITTLE_ENDIAN
384 			uint32_t	seqlenbcnt:4;
385 			uint32_t	rsvd1:28;
386 #endif
387 			uint32_t	rsvd[10];
388 		} profile2;
389 
390 		struct
391 		{
392 #ifdef EMLXS_BIG_ENDIAN
393 			uint32_t	seqlenoff:16;
394 			uint32_t	maxlen:16;
395 #endif
396 #ifdef EMLXS_LITTLE_ENDIAN
397 			uint32_t	maxlen:16;
398 			uint32_t	seqlenoff:16;
399 #endif
400 #ifdef EMLXS_BIG_ENDIAN
401 			uint32_t	cmdcodeoff:28;
402 			uint32_t	rsvd1:12;
403 			uint32_t	seqlenbcnt:4;
404 #endif
405 #ifdef EMLXS_LITTLE_ENDIAN
406 			uint32_t	seqlenbcnt:4;
407 			uint32_t	rsvd1:12;
408 			uint32_t	cmdcodeoff:28;
409 #endif
410 			uint32_t	cmdmatch[8];
411 
412 			uint32_t	rsvd[2];
413 		} profile3;
414 
415 		struct
416 		{
417 #ifdef EMLXS_BIG_ENDIAN
418 			uint32_t	seqlenoff:16;
419 			uint32_t	maxlen:16;
420 #endif
421 #ifdef EMLXS_LITTLE_ENDIAN
422 			uint32_t	maxlen:16;
423 			uint32_t	seqlenoff:16;
424 #endif
425 #ifdef EMLXS_BIG_ENDIAN
426 			uint32_t	cmdcodeoff:28;
427 			uint32_t	rsvd1:12;
428 			uint32_t	seqlenbcnt:4;
429 #endif
430 #ifdef EMLXS_LITTLE_ENDIAN
431 			uint32_t	seqlenbcnt:4;
432 			uint32_t	rsvd1:12;
433 			uint32_t	cmdcodeoff:28;
434 #endif
435 			uint32_t	cmdmatch[8];
436 
437 			uint32_t	rsvd[2];
438 		} profile5;
439 	} profiles;
440 } HBQ_INIT_t;
441 
442 
443 
444 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
445 
446 
447 typedef struct
448 {
449 #ifdef EMLXS_BIG_ENDIAN
450 	uint32_t	rsvd2:24;
451 	uint32_t	keep:1;
452 	uint32_t	acknowledgment:1;
453 	uint32_t	version:1;
454 	uint32_t	erase_or_prog:1;
455 	uint32_t	update_flash:1;
456 	uint32_t	update_ram:1;
457 	uint32_t	method:1;
458 	uint32_t	load_cmplt:1;
459 #endif
460 #ifdef EMLXS_LITTLE_ENDIAN
461 	uint32_t	load_cmplt:1;
462 	uint32_t	method:1;
463 	uint32_t	update_ram:1;
464 	uint32_t	update_flash:1;
465 	uint32_t	erase_or_prog:1;
466 	uint32_t	version:1;
467 	uint32_t	acknowledgment:1;
468 	uint32_t	keep:1;
469 	uint32_t	rsvd2:24;
470 #endif
471 
472 #define	DL_FROM_BDE	0	/* method */
473 #define	DL_FROM_SLIM	1
474 
475 #define	PROGRAM_FLASH	0	/* erase_or_prog */
476 #define	ERASE_FLASH	1
477 
478 	uint32_t	dl_to_adr;
479 	uint32_t	dl_len;
480 	union
481 	{
482 		uint32_t	dl_from_slim_offset;
483 		ULP_BDE		dl_from_bde;
484 		ULP_BDE64	dl_from_bde64;
485 		PROG_ID		prog_id;
486 	} un;
487 } LOAD_SM_VAR;
488 
489 
490 /* Structure for MB Command READ_NVPARM (02) */
491 /* Good for SLI2/3 and SLI4 */
492 
493 typedef struct
494 {
495 	uint32_t	rsvd1[3];	/* Read as all one's */
496 	uint32_t	rsvd2;		/* Read as all zero's */
497 	uint32_t	portname[2];	/* N_PORT name */
498 	uint32_t	nodename[2];	/* NODE name */
499 #ifdef EMLXS_BIG_ENDIAN
500 	uint32_t	pref_DID:24;
501 	uint32_t	hardAL_PA:8;
502 #endif
503 #ifdef EMLXS_LITTLE_ENDIAN
504 	uint32_t	hardAL_PA:8;
505 	uint32_t	pref_DID:24;
506 #endif
507 	uint32_t	rsvd3[21];	/* Read as all one's */
508 } READ_NV_VAR;
509 
510 
511 /* Structure for MB Command WRITE_NVPARMS (03) */
512 /* Good for SLI2/3 and SLI4 */
513 
514 typedef struct
515 {
516 	uint32_t	rsvd1[3];	/* Must be all one's */
517 	uint32_t	rsvd2;		/* Must be all zero's */
518 	uint32_t	portname[2];	/* N_PORT name */
519 	uint32_t	nodename[2];	/* NODE name */
520 #ifdef EMLXS_BIG_ENDIAN
521 	uint32_t	pref_DID:24;
522 	uint32_t	hardAL_PA:8;
523 #endif
524 #ifdef EMLXS_LITTLE_ENDIAN
525 	uint32_t	hardAL_PA:8;
526 	uint32_t	pref_DID:24;
527 #endif
528 	uint32_t	rsvd3[21];	/* Must be all one's */
529 } WRITE_NV_VAR;
530 
531 
532 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
533 /* Good for SLI2/3 and SLI4 */
534 
535 typedef struct
536 {
537 	uint32_t	rsvd1;
538 	union
539 	{
540 		struct
541 		{
542 			ULP_BDE64	xmit_bde64;
543 			ULP_BDE64	rcv_bde64;
544 		} s2;
545 	} un;
546 } BIU_DIAG_VAR;
547 
548 
549 /* Structure for MB Command INIT_LINK (05) */
550 /* Good for SLI2/3 and SLI4 */
551 
552 typedef struct
553 {
554 #ifdef EMLXS_BIG_ENDIAN
555 	uint32_t	rsvd1:24;
556 	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
557 					/* Reset to */
558 #endif
559 #ifdef EMLXS_LITTLE_ENDIAN
560 	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
561 					/* Reset to */
562 	uint32_t	rsvd1:24;
563 #endif
564 
565 #ifdef EMLXS_BIG_ENDIAN
566 	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
567 	uint8_t		rsvd2;
568 	uint16_t	link_flags;
569 #endif
570 #ifdef EMLXS_LITTLE_ENDIAN
571 	uint16_t	link_flags;
572 	uint8_t		rsvd2;
573 	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
574 #endif
575 #define	FLAGS_LOCAL_LB			0x01	/* link_flags (=1) */
576 						/* ENDEC loopback */
577 #define	FLAGS_TOPOLOGY_MODE_LOOP_PT	0x00	/* Attempt loop then pt-pt */
578 #define	FLAGS_TOPOLOGY_MODE_PT_PT	0x02	/* Attempt pt-pt only */
579 #define	FLAGS_TOPOLOGY_MODE_LOOP	0x04	/* Attempt loop only */
580 #define	FLAGS_TOPOLOGY_MODE_PT_LOOP	0x06	/* Attempt pt-pt then loop */
581 #define	FLAGS_LIRP_LILP			0x80	/* LIRP / LILP is disabled */
582 
583 #define	FLAGS_TOPOLOGY_FAILOVER		0x0400	/* Bit 10 */
584 #define	FLAGS_LINK_SPEED		0x0800	/* Bit 11 */
585 #define	FLAGS_PREABORT_RETURN		0x4000	/* Bit 14 */
586 
587 	uint32_t	link_speed;	/* NEW_FEATURE */
588 #define	LINK_SPEED_AUTO			0	/* Auto selection */
589 #define	LINK_SPEED_1G			1	/* 1 Gigabaud */
590 #define	LINK_SPEED_2G			2	/* 2 Gigabaud */
591 } INIT_LINK_VAR;
592 
593 
594 /* Structure for MB Command DOWN_LINK (06) */
595 /* Good for SLI2/3 and SLI4 */
596 
597 typedef struct
598 {
599 	uint32_t	rsvd1;
600 } DOWN_LINK_VAR;
601 
602 
603 /* Structure for MB Command CONFIG_LINK (07) */
604 
605 typedef struct
606 {
607 #ifdef EMLXS_BIG_ENDIAN
608 	uint32_t	cr:1;
609 	uint32_t	ci:1;
610 	uint32_t	cr_delay:6;
611 	uint32_t	cr_count:8;
612 	uint32_t	rsvd1:8;
613 	uint32_t	MaxBBC:8;
614 #endif
615 #ifdef EMLXS_LITTLE_ENDIAN
616 	uint32_t	MaxBBC:8;
617 	uint32_t	rsvd1:8;
618 	uint32_t	cr_count:8;
619 	uint32_t	cr_delay:6;
620 	uint32_t	ci:1;
621 	uint32_t	cr:1;
622 #endif
623 	uint32_t	myId;
624 	uint32_t	rsvd2;
625 	uint32_t	edtov;
626 	uint32_t	arbtov;
627 	uint32_t	ratov;
628 	uint32_t	rttov;
629 	uint32_t	altov;
630 	uint32_t	crtov;
631 	uint32_t	citov;
632 #ifdef EMLXS_BIG_ENDIAN
633 	uint32_t	rrq_enable:1;
634 	uint32_t	rrq_immed:1;
635 	uint32_t	rsvd4:29;
636 	uint32_t	ack0_enable:1;
637 #endif
638 #ifdef EMLXS_LITTLE_ENDIAN
639 	uint32_t	ack0_enable:1;
640 	uint32_t	rsvd4:29;
641 	uint32_t	rrq_immed:1;
642 	uint32_t	rrq_enable:1;
643 #endif
644 } CONFIG_LINK;
645 
646 
647 /* Structure for MB Command PART_SLIM (08) */
648 
649 typedef struct
650 {
651 #ifdef EMLXS_BIG_ENDIAN
652 	uint32_t		unused1:24;
653 	uint32_t		numRing:8;
654 #endif
655 #ifdef EMLXS_LITTLE_ENDIAN
656 	uint32_t		numRing:8;
657 	uint32_t		unused1:24;
658 #endif
659 	emlxs_ring_def_t	ringdef[4];
660 	uint32_t		hbainit;
661 } PART_SLIM_VAR;
662 
663 
664 /* Structure for MB Command CONFIG_RING (09) */
665 
666 typedef struct
667 {
668 #ifdef EMLXS_BIG_ENDIAN
669 	uint32_t	unused2:6;
670 	uint32_t	recvSeq:1;
671 	uint32_t	recvNotify:1;
672 	uint32_t	numMask:8;
673 	uint32_t	profile:8;
674 	uint32_t	unused1:4;
675 	uint32_t	ring:4;
676 #endif
677 #ifdef EMLXS_LITTLE_ENDIAN
678 	uint32_t	ring:4;
679 	uint32_t	unused1:4;
680 	uint32_t	profile:8;
681 	uint32_t	numMask:8;
682 	uint32_t	recvNotify:1;
683 	uint32_t	recvSeq:1;
684 	uint32_t	unused2:6;
685 #endif
686 #ifdef EMLXS_BIG_ENDIAN
687 	uint16_t	maxRespXchg;
688 	uint16_t	maxOrigXchg;
689 #endif
690 #ifdef EMLXS_LITTLE_ENDIAN
691 	uint16_t	maxOrigXchg;
692 	uint16_t	maxRespXchg;
693 #endif
694 	RR_REG		rrRegs[6];
695 } CONFIG_RING_VAR;
696 
697 
698 /* Structure for MB Command RESET_RING (10) */
699 
700 typedef struct
701 {
702 	uint32_t	ring_no;
703 } RESET_RING_VAR;
704 
705 
706 /* Structure for MB Command READ_CONFIG (11) */
707 /* Good for SLI2/3 only */
708 
709 typedef struct
710 {
711 #ifdef EMLXS_BIG_ENDIAN
712 	uint32_t	cr:1;
713 	uint32_t	ci:1;
714 	uint32_t	cr_delay:6;
715 	uint32_t	cr_count:8;
716 	uint32_t	InitBBC:8;
717 	uint32_t	MaxBBC:8;
718 #endif
719 #ifdef EMLXS_LITTLE_ENDIAN
720 	uint32_t	MaxBBC:8;
721 	uint32_t	InitBBC:8;
722 	uint32_t	cr_count:8;
723 	uint32_t	cr_delay:6;
724 	uint32_t	ci:1;
725 	uint32_t	cr:1;
726 #endif
727 #ifdef EMLXS_BIG_ENDIAN
728 	uint32_t	topology:8;
729 	uint32_t	myDid:24;
730 #endif
731 #ifdef EMLXS_LITTLE_ENDIAN
732 	uint32_t	myDid:24;
733 	uint32_t	topology:8;
734 #endif
735 	/* Defines for topology (defined previously) */
736 #ifdef EMLXS_BIG_ENDIAN
737 	uint32_t	AR:1;
738 	uint32_t	IR:1;
739 	uint32_t	rsvd1:29;
740 	uint32_t	ack0:1;
741 #endif
742 #ifdef EMLXS_LITTLE_ENDIAN
743 	uint32_t	ack0:1;
744 	uint32_t	rsvd1:29;
745 	uint32_t	IR:1;
746 	uint32_t	AR:1;
747 #endif
748 	uint32_t	edtov;
749 	uint32_t	arbtov;
750 	uint32_t	ratov;
751 	uint32_t	rttov;
752 	uint32_t	altov;
753 	uint32_t	lmt;
754 
755 #define	LMT_1GB_CAPABLE		0x0004
756 #define	LMT_2GB_CAPABLE		0x0008
757 #define	LMT_4GB_CAPABLE		0x0040
758 #define	LMT_8GB_CAPABLE		0x0080
759 #define	LMT_10GB_CAPABLE	0x0100
760 #define	LMT_16GB_CAPABLE	0x0200
761 /* E2E supported on adapters >= 8GB */
762 #define	LMT_E2E_CAPABLE		(LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
763 
764 	uint32_t	rsvd2;
765 	uint32_t	rsvd3;
766 	uint32_t	max_xri;
767 	uint32_t	max_iocb;
768 	uint32_t	max_rpi;
769 	uint32_t	avail_xri;
770 	uint32_t	avail_iocb;
771 	uint32_t	avail_rpi;
772 	uint32_t	max_vpi;
773 	uint32_t	max_alpa;
774 	uint32_t	rsvd4;
775 	uint32_t	avail_vpi;
776 
777 } READ_CONFIG_VAR;
778 
779 
780 /* Structure for MB Command READ_CONFIG(0x11) */
781 /* Good for SLI4 only */
782 
783 typedef struct
784 {
785 #ifdef EMLXS_BIG_ENDIAN
786 	uint32_t	extents:1;	/* Word 1 */
787 	uint32_t	rsvd1:31;
788 
789 	uint32_t	topology:8;	/* Word 2 */
790 	uint32_t	rsvd2:15;
791 	uint32_t	ldv:1;
792 	uint32_t	link_type:2;
793 	uint32_t	link_number:6;
794 #endif
795 #ifdef EMLXS_LITTLE_ENDIAN
796 	uint32_t	rsvd1:31;	/* Word 1 */
797 	uint32_t	extents:1;
798 
799 	uint32_t	link_number:6;	/* Word 2 */
800 	uint32_t	link_type:2;
801 	uint32_t	ldv:1;
802 	uint32_t	rsvd2:15;
803 	uint32_t	topology:8;
804 #endif
805 	uint32_t	rsvd3;		/* Word 3 */
806 	uint32_t	edtov;		/* Word 4 */
807 	uint32_t	rsvd4;		/* Word 5 */
808 	uint32_t	ratov;		/* Word 6 */
809 	uint32_t	rsvd5;		/* Word 7 */
810 	uint32_t	rsvd6;		/* Word 8 */
811 	uint32_t	lmt;		/* Word 9 */
812 	uint32_t	rsvd8;		/* Word 10 */
813 	uint32_t	rsvd9;		/* Word 11 */
814 
815 #ifdef EMLXS_BIG_ENDIAN
816 	uint16_t	XRICount;	/* Word 12 */
817 	uint16_t	XRIBase;	/* Word 12 */
818 
819 	uint16_t	RPICount;	/* Word 13 */
820 	uint16_t	RPIBase;	/* Word 13 */
821 
822 	uint16_t	VPICount;	/* Word 14 */
823 	uint16_t	VPIBase;	/* Word 14 */
824 
825 	uint16_t	VFICount;	/* Word 15 */
826 	uint16_t	VFIBase;	/* Word 15 */
827 
828 	uint16_t	FCFICount;	/* Word 16 */
829 	uint16_t	rsvd10;		/* Word 16 */
830 
831 	uint16_t	EQCount;	/* Word 17 */
832 	uint16_t	RQCount;	/* Word 17 */
833 
834 	uint16_t	CQCount;	/* Word 18 */
835 	uint16_t	WQCount;	/* Word 18 */
836 #endif
837 #ifdef EMLXS_LITTLE_ENDIAN
838 	uint16_t	XRIBase;	/* Word 12 */
839 	uint16_t	XRICount;	/* Word 12 */
840 
841 	uint16_t	RPIBase;	/* Word 13 */
842 	uint16_t	RPICount;	/* Word 13 */
843 
844 	uint16_t	VPIBase;	/* Word 14 */
845 	uint16_t	VPICount;	/* Word 14 */
846 
847 	uint16_t	VFIBase;	/* Word 15 */
848 	uint16_t	VFICount;	/* Word 15 */
849 
850 	uint16_t	rsvd10;		/* Word 16 */
851 	uint16_t	FCFICount;	/* Word 16 */
852 
853 	uint16_t	RQCount;	/* Word 17 */
854 	uint16_t	EQCount;	/* Word 17 */
855 
856 	uint16_t	WQCount;	/* Word 18 */
857 	uint16_t	CQCount;	/* Word 18 */
858 #endif
859 
860 } READ_CONFIG4_VAR;
861 
862 /* Structure for MB Command READ_RCONFIG (12) */
863 
864 typedef struct
865 {
866 #ifdef EMLXS_BIG_ENDIAN
867 	uint32_t	rsvd2:7;
868 	uint32_t	recvNotify:1;
869 	uint32_t	numMask:8;
870 	uint32_t	profile:8;
871 	uint32_t	rsvd1:4;
872 	uint32_t	ring:4;
873 #endif
874 #ifdef EMLXS_LITTLE_ENDIAN
875 	uint32_t	ring:4;
876 	uint32_t	rsvd1:4;
877 	uint32_t	profile:8;
878 	uint32_t	numMask:8;
879 	uint32_t	recvNotify:1;
880 	uint32_t	rsvd2:7;
881 #endif
882 #ifdef EMLXS_BIG_ENDIAN
883 	uint16_t	maxResp;
884 	uint16_t	maxOrig;
885 #endif
886 #ifdef EMLXS_LITTLE_ENDIAN
887 	uint16_t	maxOrig;
888 	uint16_t	maxResp;
889 #endif
890 	RR_REG		rrRegs[6];
891 #ifdef EMLXS_BIG_ENDIAN
892 	uint16_t	cmdRingOffset;
893 	uint16_t	cmdEntryCnt;
894 	uint16_t	rspRingOffset;
895 	uint16_t	rspEntryCnt;
896 	uint16_t	nextCmdOffset;
897 	uint16_t	rsvd3;
898 	uint16_t	nextRspOffset;
899 	uint16_t	rsvd4;
900 #endif
901 #ifdef EMLXS_LITTLE_ENDIAN
902 	uint16_t	cmdEntryCnt;
903 	uint16_t	cmdRingOffset;
904 	uint16_t	rspEntryCnt;
905 	uint16_t	rspRingOffset;
906 	uint16_t	rsvd3;
907 	uint16_t	nextCmdOffset;
908 	uint16_t	rsvd4;
909 	uint16_t	nextRspOffset;
910 #endif
911 } READ_RCONF_VAR;
912 
913 
914 /* Structure for MB Command READ_SPARM (13) */
915 /* Structure for MB Command READ_SPARM64 (0x8D) */
916 /* Good for SLI2/3 and SLI4 */
917 
918 typedef struct
919 {
920 	uint32_t	rsvd1;
921 	uint32_t	rsvd2;
922 	union
923 	{
924 		ULP_BDE		sp;	/* This BDE points to SERV_PARM */
925 					/* structure */
926 		ULP_BDE64	sp64;
927 	} un;
928 	uint32_t	rsvd3;
929 
930 #ifdef EMLXS_BIG_ENDIAN
931 	uint16_t	portNameCnt;
932 	uint16_t	portNameOffset;
933 
934 	uint16_t	fabricNameCnt;
935 	uint16_t	fabricNameOffset;
936 
937 	uint16_t	lportNameCnt;
938 	uint16_t	lportNameOffset;
939 
940 	uint16_t	lfabricNameCnt;
941 	uint16_t	lfabricNameOffset;
942 
943 #endif
944 #ifdef EMLXS_LITTLE_ENDIAN
945 	uint16_t	portNameOffset;
946 	uint16_t	portNameCnt;
947 
948 	uint16_t	fabricNameOffset;
949 	uint16_t	fabricNameCnt;
950 
951 	uint16_t	lportNameOffset;
952 	uint16_t	lportNameCnt;
953 
954 	uint16_t	lfabricNameOffset;
955 	uint16_t	lfabricNameCnt;
956 
957 #endif
958 
959 } READ_SPARM_VAR;
960 
961 
962 /* Structure for MB Command READ_STATUS (14) */
963 /* Good for SLI2/3 and SLI4 */
964 
965 typedef struct
966 {
967 #ifdef EMLXS_BIG_ENDIAN
968 	uint32_t	rsvd1:31;
969 	uint32_t	clrCounters:1;
970 
971 	uint16_t	activeXriCnt;
972 	uint16_t	activeRpiCnt;
973 #endif
974 #ifdef EMLXS_LITTLE_ENDIAN
975 	uint32_t	clrCounters:1;
976 	uint32_t	rsvd1:31;
977 
978 	uint16_t	activeRpiCnt;
979 	uint16_t	activeXriCnt;
980 #endif
981 	uint32_t	xmitByteCnt;
982 	uint32_t	rcvByteCnt;
983 	uint32_t	xmitFrameCnt;
984 	uint32_t	rcvFrameCnt;
985 	uint32_t	xmitSeqCnt;
986 	uint32_t	rcvSeqCnt;
987 	uint32_t	totalOrigExchanges;
988 	uint32_t	totalRespExchanges;
989 	uint32_t	rcvPbsyCnt;
990 	uint32_t	rcvFbsyCnt;
991 } READ_STATUS_VAR;
992 
993 
994 /* Structure for MB Command READ_RPI (15) */
995 /* Structure for MB Command READ_RPI64 (0x8F) */
996 
997 typedef struct
998 {
999 #ifdef EMLXS_BIG_ENDIAN
1000 	uint16_t	nextRpi;
1001 	uint16_t	reqRpi;
1002 	uint32_t	rsvd2:8;
1003 	uint32_t	DID:24;
1004 #endif
1005 #ifdef EMLXS_LITTLE_ENDIAN
1006 	uint16_t	reqRpi;
1007 	uint16_t	nextRpi;
1008 	uint32_t	DID:24;
1009 	uint32_t	rsvd2:8;
1010 #endif
1011 	union
1012 	{
1013 		ULP_BDE		sp;
1014 		ULP_BDE64	sp64;
1015 	} un;
1016 } READ_RPI_VAR;
1017 
1018 
1019 /* Structure for MB Command READ_XRI (16) */
1020 
1021 typedef struct
1022 {
1023 #ifdef EMLXS_BIG_ENDIAN
1024 	uint16_t	nextXri;
1025 	uint16_t	reqXri;
1026 	uint16_t	rsvd1;
1027 	uint16_t	rpi;
1028 	uint32_t	rsvd2:8;
1029 	uint32_t	DID:24;
1030 	uint32_t	rsvd3:8;
1031 	uint32_t	SID:24;
1032 	uint32_t	rsvd4;
1033 	uint8_t		seqId;
1034 	uint8_t		rsvd5;
1035 	uint16_t	seqCount;
1036 	uint16_t	oxId;
1037 	uint16_t	rxId;
1038 	uint32_t	rsvd6:30;
1039 	uint32_t	si:1;
1040 	uint32_t	exchOrig:1;
1041 #endif
1042 #ifdef EMLXS_LITTLE_ENDIAN
1043 	uint16_t	reqXri;
1044 	uint16_t	nextXri;
1045 	uint16_t	rpi;
1046 	uint16_t	rsvd1;
1047 	uint32_t	DID:24;
1048 	uint32_t	rsvd2:8;
1049 	uint32_t	SID:24;
1050 	uint32_t	rsvd3:8;
1051 	uint32_t	rsvd4;
1052 	uint16_t	seqCount;
1053 	uint8_t		rsvd5;
1054 	uint8_t		seqId;
1055 	uint16_t	rxId;
1056 	uint16_t	oxId;
1057 	uint32_t	exchOrig:1;
1058 	uint32_t	si:1;
1059 	uint32_t	rsvd6:30;
1060 #endif
1061 } READ_XRI_VAR;
1062 
1063 
1064 /* Structure for MB Command READ_REV (17) */
1065 /* Good for SLI2/3 only */
1066 
1067 typedef struct
1068 {
1069 #ifdef EMLXS_BIG_ENDIAN
1070 	uint32_t	cv:1;
1071 	uint32_t	rr:1;
1072 	uint32_t	co:1;
1073 	uint32_t	rp:1;
1074 	uint32_t	cv3:1;
1075 	uint32_t	rf3:1;
1076 	uint32_t	rsvd1:10;
1077 	uint32_t	offset:14;
1078 	uint32_t	rv:2;
1079 #endif
1080 #ifdef EMLXS_LITTLE_ENDIAN
1081 	uint32_t	rv:2;
1082 	uint32_t	offset:14;
1083 	uint32_t	rsvd1:10;
1084 	uint32_t	rf3:1;
1085 	uint32_t	cv3:1;
1086 	uint32_t	rp:1;
1087 	uint32_t	co:1;
1088 	uint32_t	rr:1;
1089 	uint32_t	cv:1;
1090 #endif
1091 	uint32_t	biuRev;
1092 	uint32_t	smRev;
1093 	union
1094 	{
1095 		uint32_t	smFwRev;
1096 		struct
1097 		{
1098 #ifdef EMLXS_BIG_ENDIAN
1099 			uint8_t		ProgType;
1100 			uint8_t		ProgId;
1101 			uint16_t	ProgVer:4;
1102 			uint16_t	ProgRev:4;
1103 			uint16_t	ProgFixLvl:2;
1104 			uint16_t	ProgDistType:2;
1105 			uint16_t	DistCnt:4;
1106 #endif
1107 #ifdef EMLXS_LITTLE_ENDIAN
1108 			uint16_t	DistCnt:4;
1109 			uint16_t	ProgDistType:2;
1110 			uint16_t	ProgFixLvl:2;
1111 			uint16_t	ProgRev:4;
1112 			uint16_t	ProgVer:4;
1113 			uint8_t		ProgId;
1114 			uint8_t		ProgType;
1115 #endif
1116 		} b;
1117 	} un;
1118 	uint32_t	endecRev;
1119 #ifdef EMLXS_BIG_ENDIAN
1120 	uint8_t		feaLevelHigh;
1121 	uint8_t		feaLevelLow;
1122 	uint8_t		fcphHigh;
1123 	uint8_t		fcphLow;
1124 #endif
1125 #ifdef EMLXS_LITTLE_ENDIAN
1126 	uint8_t		fcphLow;
1127 	uint8_t		fcphHigh;
1128 	uint8_t		feaLevelLow;
1129 	uint8_t		feaLevelHigh;
1130 #endif
1131 	uint32_t	postKernRev;
1132 	uint32_t	opFwRev;
1133 	uint8_t		opFwName[16];
1134 
1135 	uint32_t	sliFwRev1;
1136 	uint8_t		sliFwName1[16];
1137 	uint32_t	sliFwRev2;
1138 	uint8_t		sliFwName2[16];
1139 } READ_REV_VAR;
1140 
1141 /* Structure for MB Command READ_REV (17) */
1142 /* Good for SLI4 only */
1143 
1144 typedef struct
1145 {
1146 #ifdef EMLXS_BIG_ENDIAN
1147 	uint32_t	Rsvd3:2;
1148 	uint32_t	VPD:1;
1149 	uint32_t	rsvd2:6;
1150 	uint32_t	dcbxMode:2;
1151 	uint32_t	FCoE:1;
1152 	uint32_t	sliLevel:4;
1153 	uint32_t	rsvd1:16;
1154 #endif
1155 #ifdef EMLXS_LITTLE_ENDIAN
1156 	uint32_t	rsvd1:16;
1157 	uint32_t	sliLevel:4;
1158 	uint32_t	FCoE:1;
1159 	uint32_t	dcbxMode:2;
1160 	uint32_t	rsvd2:6;
1161 	uint32_t	VPD:1;
1162 	uint32_t	Rsvd3:2;
1163 #endif
1164 
1165 	uint32_t	HwRev1;
1166 	uint32_t	HwRev2;
1167 	uint32_t	Rsvd4;
1168 	uint32_t	HwRev3;
1169 
1170 #ifdef EMLXS_BIG_ENDIAN
1171 	uint8_t		feaLevelHigh;
1172 	uint8_t		feaLevelLow;
1173 	uint8_t		fcphHigh;
1174 	uint8_t		fcphLow;
1175 #endif
1176 #ifdef EMLXS_LITTLE_ENDIAN
1177 	uint8_t		fcphLow;
1178 	uint8_t		fcphHigh;
1179 	uint8_t		feaLevelLow;
1180 	uint8_t		feaLevelHigh;
1181 #endif
1182 
1183 	uint32_t	Redboot;
1184 
1185 	uint32_t	ARMFwId;
1186 	uint8_t		ARMFwName[16];
1187 
1188 	uint32_t	ULPFwId;
1189 	uint8_t		ULPFwName[16];
1190 
1191 	uint32_t	Rsvd6[30];
1192 
1193 	ULP_BDE64	VPDBde;
1194 
1195 	uint32_t	ReturnedVPDLength;
1196 
1197 } READ_REV4_VAR;
1198 
1199 #define	EMLXS_DCBX_MODE_CIN	0	/* Mapped to nonFIP mode */
1200 #define	EMLXS_DCBX_MODE_CEE	1	/* Mapped to FIP mode */
1201 
1202 /* Structure for MB Command READ_LINK_STAT (18) */
1203 /* Good for SLI2/3 and SLI4 */
1204 
1205 typedef struct
1206 {
1207 	uint32_t	rsvd1;
1208 	uint32_t	linkFailureCnt;
1209 	uint32_t	lossSyncCnt;
1210 
1211 	uint32_t	lossSignalCnt;
1212 	uint32_t	primSeqErrCnt;
1213 	uint32_t	invalidXmitWord;
1214 	uint32_t	crcCnt;
1215 	uint32_t	primSeqTimeout;
1216 	uint32_t	elasticOverrun;
1217 	uint32_t	arbTimeout;
1218 
1219 	uint32_t	rxBufCredit;
1220 	uint32_t	rxBufCreditCur;
1221 
1222 	uint32_t	txBufCredit;
1223 	uint32_t	txBufCreditCur;
1224 
1225 	uint32_t	EOFaCnt;
1226 	uint32_t	EOFdtiCnt;
1227 	uint32_t	EOFniCnt;
1228 	uint32_t	SOFfCnt;
1229 	uint32_t	DropAERCnt;
1230 	uint32_t	DropRcv;
1231 } READ_LNK_VAR;
1232 
1233 
1234 /* Structure for MB Command REG_LOGIN (19) */
1235 /* Structure for MB Command REG_LOGIN64 (0x93) */
1236 /* Structure for MB Command REG_RPI (0x93) */
1237 /* Good for SLI2/3 and SLI4 */
1238 
1239 typedef struct
1240 {
1241 #ifdef EMLXS_BIG_ENDIAN
1242 	uint16_t	rsvd1;
1243 	uint16_t	rpi;
1244 	uint32_t	CI:1;
1245 	uint32_t	rsvd2:1;
1246 	uint32_t	TERP:1;
1247 	uint32_t	rsvd3:4;
1248 	uint32_t	update:1;
1249 	uint32_t	did:24;
1250 #endif
1251 #ifdef EMLXS_LITTLE_ENDIAN
1252 	uint16_t	rpi;
1253 	uint16_t	rsvd1;
1254 	uint32_t	did:24;
1255 	uint32_t	update:1;
1256 	uint32_t	rsvd3:4;
1257 	uint32_t	TERP:1;
1258 	uint32_t	rsvd2:1;
1259 	uint32_t	CI:1;
1260 #endif
1261 	union
1262 	{
1263 		ULP_BDE		sp;
1264 		ULP_BDE64	sp64;
1265 	} un;
1266 
1267 #ifdef EMLXS_BIG_ENDIAN
1268 	uint16_t	rsvd6;
1269 	uint16_t	vpi;
1270 #endif
1271 #ifdef EMLXS_LITTLE_ENDIAN
1272 	uint16_t	vpi;
1273 	uint16_t	rsvd6;
1274 #endif
1275 } REG_LOGIN_VAR;
1276 
1277 /* Word 30 contents for REG_LOGIN */
1278 typedef union
1279 {
1280 	struct
1281 	{
1282 #ifdef EMLXS_BIG_ENDIAN
1283 		uint16_t	rsvd1:12;
1284 		uint16_t	class:4;
1285 		uint16_t	xri;
1286 #endif
1287 #ifdef EMLXS_LITTLE_ENDIAN
1288 		uint16_t	xri;
1289 		uint16_t	class:4;
1290 		uint16_t	rsvd1:12;
1291 #endif
1292 	} f;
1293 	uint32_t	word;
1294 } REG_WD30;
1295 
1296 
1297 /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
1298 /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
1299 
1300 typedef struct
1301 {
1302 #ifdef EMLXS_BIG_ENDIAN
1303 	uint16_t	ll:2;		/* SLI4 only */
1304 	uint16_t	rsvd1:14;
1305 	uint16_t	rpi;
1306 #endif
1307 #ifdef EMLXS_LITTLE_ENDIAN
1308 	uint16_t	rpi;
1309 	uint16_t	rsvd1:14;
1310 	uint16_t	ll:2;		/* SLI4 only */
1311 #endif
1312 
1313 	uint32_t	rsvd2;
1314 	uint32_t	rsvd3;
1315 	uint32_t	rsvd4;
1316 	uint32_t	rsvd5;
1317 #ifdef EMLXS_BIG_ENDIAN
1318 	uint16_t	rsvd6;
1319 	uint16_t	vpi;
1320 #endif
1321 #ifdef EMLXS_LITTLE_ENDIAN
1322 	uint16_t	vpi;
1323 	uint16_t	rsvd6;
1324 #endif
1325 } UNREG_LOGIN_VAR;
1326 
1327 /* Structure for MB Command REG_FCFI (0xA0) */
1328 /* Good for SLI4 only */
1329 
1330 typedef struct
1331 {
1332 #ifdef EMLXS_BIG_ENDIAN
1333 	uint16_t	FCFI;
1334 	uint16_t	InfoIndex;
1335 
1336 	uint16_t	RQId0;
1337 	uint16_t	RQId1;
1338 	uint16_t	RQId2;
1339 	uint16_t	RQId3;
1340 
1341 	uint8_t		Id0_type;
1342 	uint8_t		Id0_type_mask;
1343 	uint8_t		Id0_rctl;
1344 	uint8_t		Id0_rctl_mask;
1345 
1346 	uint8_t		Id1_type;
1347 	uint8_t		Id1_type_mask;
1348 	uint8_t		Id1_rctl;
1349 	uint8_t		Id1_rctl_mask;
1350 
1351 	uint8_t		Id2_type;
1352 	uint8_t		Id2_type_mask;
1353 	uint8_t		Id2_rctl;
1354 	uint8_t		Id2_rctl_mask;
1355 
1356 	uint8_t		Id3_type;
1357 	uint8_t		Id3_type_mask;
1358 	uint8_t		Id3_rctl;
1359 	uint8_t		Id3_rctl_mask;
1360 
1361 	uint32_t	Rsvd1: 17;
1362 	uint32_t	mam: 2;
1363 	uint32_t	vv: 1;
1364 	uint32_t	vlanTag: 12;
1365 #endif
1366 #ifdef EMLXS_LITTLE_ENDIAN
1367 	uint16_t	InfoIndex;
1368 	uint16_t	FCFI;
1369 
1370 	uint16_t	RQId1;
1371 	uint16_t	RQId0;
1372 	uint16_t	RQId3;
1373 	uint16_t	RQId2;
1374 
1375 	uint8_t		Id0_rctl_mask;
1376 	uint8_t		Id0_rctl;
1377 	uint8_t		Id0_type_mask;
1378 	uint8_t		Id0_type;
1379 
1380 	uint8_t		Id1_rctl_mask;
1381 	uint8_t		Id1_rctl;
1382 	uint8_t		Id1_type_mask;
1383 	uint8_t		Id1_type;
1384 
1385 	uint8_t		Id2_rctl_mask;
1386 	uint8_t		Id2_rctl;
1387 	uint8_t		Id2_type_mask;
1388 	uint8_t		Id2_type;
1389 
1390 	uint8_t		Id3_rctl_mask;
1391 	uint8_t		Id3_rctl;
1392 	uint8_t		Id3_type_mask;
1393 	uint8_t		Id3_type;
1394 
1395 	uint32_t	vlanTag: 12;
1396 	uint32_t	vv: 1;
1397 	uint32_t	mam: 2;
1398 	uint32_t	Rsvd1: 17;
1399 #endif
1400 
1401 }  REG_FCFI_VAR;
1402 
1403 /* Defines for mam */
1404 #define	EMLXS_REG_FCFI_MAM_SPMA	1	/* Server Provided MAC Address */
1405 #define	EMLXS_REG_FCFI_MAM_FPMA	2	/* Fabric Provided MAC Address */
1406 
1407 /* Structure for MB Command UNREG_FCFI (0xA2) */
1408 /* Good for SLI4 only */
1409 
1410 typedef struct
1411 {
1412 	uint32_t	Rsvd1;
1413 #ifdef EMLXS_BIG_ENDIAN
1414 	uint16_t	Rsvd2;
1415 	uint16_t	FCFI;
1416 #endif
1417 #ifdef EMLXS_LITTLE_ENDIAN
1418 	uint16_t	FCFI;
1419 	uint16_t	Rsvd2;
1420 #endif
1421 }  UNREG_FCFI_VAR;
1422 
1423 /* Structure for MB Command RESUME_RPI (0x9E) */
1424 /* Good for SLI4 only */
1425 
1426 typedef struct
1427 {
1428 #ifdef EMLXS_BIG_ENDIAN
1429 	uint16_t	Rsvd1;
1430 	uint16_t	RPI;
1431 
1432 	uint32_t	EventTag;
1433 	uint32_t	rsvd2[3];
1434 
1435 	uint16_t	VFI;
1436 	uint16_t	VPI;
1437 #endif
1438 #ifdef EMLXS_LITTLE_ENDIAN
1439 	uint16_t	RPI;
1440 	uint16_t	Rsvd1;
1441 
1442 	uint32_t	EventTag;
1443 	uint32_t	rsvd2[3];
1444 
1445 	uint16_t	VPI;
1446 	uint16_t	VFI;
1447 #endif
1448 
1449 }  RESUME_RPI_VAR;
1450 
1451 
1452 /* Structure for MB Command UNREG_D_ID (0x23) */
1453 
1454 typedef struct
1455 {
1456 	uint32_t	did;
1457 
1458 	uint32_t	rsvd2;
1459 	uint32_t	rsvd3;
1460 	uint32_t	rsvd4;
1461 	uint32_t	rsvd5;
1462 #ifdef EMLXS_BIG_ENDIAN
1463 	uint16_t	rsvd6;
1464 	uint16_t	vpi;
1465 #endif
1466 #ifdef EMLXS_LITTLE_ENDIAN
1467 	uint16_t	vpi;
1468 	uint16_t	rsvd6;
1469 #endif
1470 } UNREG_D_ID_VAR;
1471 
1472 
1473 /* Structure for MB Command READ_LA (21) */
1474 /* Structure for MB Command READ_LA64 (0x95) */
1475 
1476 typedef struct
1477 {
1478 	uint32_t	eventTag;	/* Event tag */
1479 #ifdef EMLXS_BIG_ENDIAN
1480 	uint32_t	rsvd2:19;
1481 	uint32_t	fa:1;
1482 	uint32_t	mm:1;
1483 	uint32_t	tc:1;
1484 	uint32_t	pb:1;
1485 	uint32_t	il:1;
1486 	uint32_t	attType:8;
1487 #endif
1488 #ifdef EMLXS_LITTLE_ENDIAN
1489 	uint32_t	attType:8;
1490 	uint32_t	il:1;
1491 	uint32_t	pb:1;
1492 	uint32_t	tc:1;
1493 	uint32_t	mm:1;
1494 	uint32_t	fa:1;
1495 	uint32_t	rsvd2:19;
1496 #endif
1497 #define	AT_RESERVED	0x00	/* Reserved - attType */
1498 #define	AT_LINK_UP	0x01	/* Link is up */
1499 #define	AT_LINK_DOWN	0x02	/* Link is down */
1500 #define	AT_NO_HARD_ALPA	0x03	/* SLI4 */
1501 
1502 #ifdef EMLXS_BIG_ENDIAN
1503 	uint8_t		granted_AL_PA;
1504 	uint8_t		lipAlPs;
1505 	uint8_t		lipType;
1506 	uint8_t		topology;
1507 #endif
1508 #ifdef EMLXS_LITTLE_ENDIAN
1509 	uint8_t		topology;
1510 	uint8_t		lipType;
1511 	uint8_t		lipAlPs;
1512 	uint8_t		granted_AL_PA;
1513 #endif
1514 
1515 	/* lipType */
1516 #define	LT_PORT_INIT	0x00	/* An L_PORT initing (F7, AL_PS) - lipType */
1517 #define	LT_PORT_ERR	0x01	/* Err @L_PORT rcv'er (F8, AL_PS) */
1518 #define	LT_RESET_APORT	0x02	/* Lip Reset of some other port */
1519 #define	LT_RESET_MYPORT	0x03	/* Lip Reset of my port */
1520 
1521 	/* topology */
1522 #define	TOPOLOGY_PT_PT	0x01	/* Topology is pt-pt / pt-fabric */
1523 #define	TOPOLOGY_LOOP	0x02	/* Topology is FC-AL (private) */
1524 
1525 	union
1526 	{
1527 		ULP_BDE		lilpBde;	/* This BDE points to a */
1528 						/* 128 byte buffer to store */
1529 						/* the LILP AL_PA position */
1530 						/* map into */
1531 		ULP_BDE64	lilpBde64;
1532 	} un;
1533 #ifdef EMLXS_BIG_ENDIAN
1534 	uint32_t	Dlu:1;
1535 	uint32_t	Dtf:1;
1536 	uint32_t	Drsvd2:14;
1537 	uint32_t	DlnkSpeed:8;
1538 	uint32_t	DnlPort:4;
1539 	uint32_t	Dtx:2;
1540 	uint32_t	Drx:2;
1541 #endif
1542 #ifdef EMLXS_LITTLE_ENDIAN
1543 	uint32_t	Drx:2;
1544 	uint32_t	Dtx:2;
1545 	uint32_t	DnlPort:4;
1546 	uint32_t	DlnkSpeed:8;
1547 	uint32_t	Drsvd2:14;
1548 	uint32_t	Dtf:1;
1549 	uint32_t	Dlu:1;
1550 #endif
1551 #ifdef EMLXS_BIG_ENDIAN
1552 	uint32_t	Ulu:1;
1553 	uint32_t	Utf:1;
1554 	uint32_t	Ursvd2:14;
1555 	uint32_t	UlnkSpeed:8;
1556 	uint32_t	UnlPort:4;
1557 	uint32_t	Utx:2;
1558 	uint32_t	Urx:2;
1559 #endif
1560 #ifdef EMLXS_LITTLE_ENDIAN
1561 	uint32_t	Urx:2;
1562 	uint32_t	Utx:2;
1563 	uint32_t	UnlPort:4;
1564 	uint32_t	UlnkSpeed:8;
1565 	uint32_t	Ursvd2:14;
1566 	uint32_t	Utf:1;
1567 	uint32_t	Ulu:1;
1568 #endif
1569 #define	LA_1GHZ_LINK   0x04	/* lnkSpeed */
1570 #define	LA_2GHZ_LINK   0x08	/* lnkSpeed */
1571 #define	LA_4GHZ_LINK   0x10	/* lnkSpeed */
1572 #define	LA_8GHZ_LINK   0x20	/* lnkSpeed */
1573 #define	LA_10GHZ_LINK  0x40	/* lnkSpeed */
1574 #define	LA_16GHZ_LINK  0x80	/* lnkSpeed */
1575 } READ_LA_VAR;
1576 
1577 
1578 /* Structure for MB Command CLEAR_LA (22) */
1579 
1580 typedef struct
1581 {
1582 	uint32_t	eventTag;	/* Event tag */
1583 	uint32_t	rsvd1;
1584 } CLEAR_LA_VAR;
1585 
1586 /* Structure for MB Command DUMP */
1587 /* Good for SLI2/3 only */
1588 
1589 typedef struct
1590 {
1591 #ifdef EMLXS_BIG_ENDIAN
1592 	uint32_t	rsvd:25;
1593 	uint32_t	ra:1;
1594 	uint32_t	co:1;
1595 	uint32_t	cv:1;
1596 	uint32_t	type:4;
1597 
1598 	uint32_t	entry_index:16;
1599 	uint32_t	region_id:16;
1600 #endif
1601 #ifdef EMLXS_LITTLE_ENDIAN
1602 	uint32_t	type:4;
1603 	uint32_t	cv:1;
1604 	uint32_t	co:1;
1605 	uint32_t	ra:1;
1606 	uint32_t	rsvd:25;
1607 
1608 	uint32_t	region_id:16;
1609 	uint32_t	entry_index:16;
1610 #endif
1611 	uint32_t	base_adr;
1612 	uint32_t	word_cnt;
1613 	uint32_t	resp_offset;
1614 } DUMP_VAR;
1615 
1616 /* Structure for MB Command DUMP */
1617 /* Good for SLI4 only */
1618 
1619 typedef struct
1620 {
1621 #ifdef EMLXS_BIG_ENDIAN
1622 	uint32_t	ppi:4;
1623 	uint32_t	phy_index:4;
1624 	uint32_t	rsvd:20;
1625 	uint32_t	type:4;
1626 
1627 	uint32_t	entry_index:16;
1628 	uint32_t	region_id:16;
1629 #endif
1630 #ifdef EMLXS_LITTLE_ENDIAN
1631 	uint32_t	type:4;
1632 	uint32_t	rsvd:20;
1633 	uint32_t	phy_index:4;
1634 	uint32_t	ppi:4;
1635 
1636 	uint32_t	region_id:16;
1637 	uint32_t	entry_index:16;
1638 #endif
1639 	uint32_t	available_cnt;
1640 	uint32_t	addrLow;
1641 	uint32_t	addrHigh;
1642 	uint32_t	rsp_cnt;
1643 } DUMP4_VAR;
1644 
1645 /*
1646  * Dump type
1647  */
1648 #define	DMP_MEM_REG	0x1
1649 #define	DMP_NV_PARAMS	0x2
1650 
1651 /*
1652  * Dump region ID
1653  */
1654 #define	NODE_CFG_A_REGION_ID	0
1655 #define	NODE_CFG_B_REGION_ID	1
1656 #define	NODE_CFG_C_REGION_ID	2
1657 #define	NODE_CFG_D_REGION_ID	3
1658 #define	WAKE_UP_PARMS_REGION_ID	4
1659 #define	DEF_PCI_CFG_REGION_ID	5
1660 #define	PCI_CFG_1_REGION_ID	6
1661 #define	PCI_CFG_2_REGION_ID	7
1662 #define	RSVD1_REGION_ID		8
1663 #define	RSVD2_REGION_ID		9
1664 #define	RSVD3_REGION_ID		10
1665 #define	RSVD4_REGION_ID		11
1666 #define	RSVD5_REGION_ID		12
1667 #define	RSVD6_REGION_ID		13
1668 #define	RSVD7_REGION_ID		14
1669 #define	DIAG_TRACE_REGION_ID	15
1670 #define	WWN_REGION_ID		16
1671 
1672 #define	DMP_VPD_REGION		14
1673 #define	DMP_VPD_SIZE		1024
1674 #define	DMP_VPD_DUMP_WCOUNT	24
1675 
1676 #define	DMP_FCOE_REGION		23
1677 #define	DMP_FCOE_DUMP_WCOUNT	256
1678 
1679 
1680 /* Structure for MB Command UPDATE_CFG */
1681 /* Good for SLI2/3 and SLI4 */
1682 
1683 typedef struct
1684 {
1685 #ifdef EMLXS_BIG_ENDIAN
1686 	uint32_t	rsvd2:16;
1687 	uint32_t	proc_type:8;
1688 	uint32_t	rsvd1:1;
1689 	uint32_t	Abit:1;
1690 	uint32_t	Obit:1;
1691 	uint32_t	Vbit:1;
1692 	uint32_t	req_type:4;
1693 #define	INIT_REGION	1
1694 #define	UPDATE_DATA	2
1695 #define	CLEAN_UP_CFG	3
1696 	uint32_t	entry_len:16;
1697 	uint32_t	region_id:16;
1698 #endif
1699 
1700 #ifdef EMLXS_LITTLE_ENDIAN
1701 	uint32_t	req_type:4;
1702 #define	INIT_REGION	1
1703 #define	UPDATE_DATA	2
1704 #define	CLEAN_UP_CFG	3
1705 	uint32_t	Vbit:1;
1706 	uint32_t	Obit:1;
1707 	uint32_t	Abit:1;
1708 	uint32_t	rsvd1:1;
1709 	uint32_t	proc_type:8;
1710 	uint32_t	rsvd2:16;
1711 
1712 	uint32_t	region_id:16;
1713 	uint32_t	entry_len:16;
1714 #endif
1715 
1716 	uint32_t	rsp_info;
1717 	uint32_t	byte_len;
1718 	uint32_t	cfg_data;
1719 } UPDATE_CFG_VAR;
1720 
1721 /* Structure for MB Command DEL_LD_ENTRY (29) */
1722 
1723 typedef struct
1724 {
1725 #ifdef EMLXS_LITTLE_ENDIAN
1726 	uint32_t	list_req:2;
1727 	uint32_t	list_rsp:2;
1728 	uint32_t	rsvd:28;
1729 #else
1730 	uint32_t	rsvd:28;
1731 	uint32_t	list_rsp:2;
1732 	uint32_t	list_req:2;
1733 #endif
1734 
1735 #define	FLASH_LOAD_LIST	1
1736 #define	RAM_LOAD_LIST	2
1737 #define	BOTH_LISTS	3
1738 
1739 	PROG_ID		prog_id;
1740 } DEL_LD_ENTRY_VAR;
1741 
1742 /* Structure for MB Command LOAD_AREA (81) */
1743 typedef struct
1744 {
1745 #ifdef EMLXS_LITTLE_ENDIAN
1746 	uint32_t	load_cmplt:1;
1747 	uint32_t	method:1;
1748 	uint32_t	rsvd1:1;
1749 	uint32_t	update_flash:1;
1750 	uint32_t	erase_or_prog:1;
1751 	uint32_t	version:1;
1752 	uint32_t	rsvd2:2;
1753 	uint32_t	progress:8;
1754 	uint32_t	step:8;
1755 	uint32_t	area_id:8;
1756 #else
1757 	uint32_t	area_id:8;
1758 	uint32_t	step:8;
1759 	uint32_t	progress:8;
1760 	uint32_t	rsvd2:2;
1761 	uint32_t	version:1;
1762 	uint32_t	erase_or_prog:1;
1763 	uint32_t	update_flash:1;
1764 	uint32_t	rsvd1:1;
1765 	uint32_t	method:1;
1766 	uint32_t	load_cmplt:1;
1767 #endif
1768 	uint32_t	dl_to_adr;
1769 	uint32_t	dl_len;
1770 	union
1771 	{
1772 		uint32_t	dl_from_slim_offset;
1773 		ULP_BDE		dl_from_bde;
1774 		ULP_BDE64	dl_from_bde64;
1775 		PROG_ID		prog_id;
1776 	} un;
1777 } LOAD_AREA_VAR;
1778 
1779 /* Structure for MB Command LOAD_EXP_ROM (9C) */
1780 typedef struct
1781 {
1782 #ifdef EMLXS_LITTLE_ENDIAN
1783 	uint32_t	rsvd1:8;
1784 	uint32_t	progress:8;
1785 	uint32_t	step:8;
1786 	uint32_t	rsvd2:8;
1787 #else
1788 	uint32_t	rsvd2:8;
1789 	uint32_t	step:8;
1790 	uint32_t	progress:8;
1791 	uint32_t	rsvd1:8;
1792 #endif
1793 	uint32_t	dl_to_adr;
1794 	uint32_t	rsvd3;
1795 	union
1796 	{
1797 		uint32_t	word[2];
1798 		PROG_ID		prog_id;
1799 	} un;
1800 } LOAD_EXP_ROM_VAR;
1801 
1802 
1803 /* Structure for MB Command CONFIG_HBQ (7C) */
1804 
1805 typedef struct
1806 {
1807 #ifdef EMLXS_BIG_ENDIAN
1808 	uint32_t	rsvd1:7;
1809 	uint32_t	recvNotify:1;	/* Receive Notification */
1810 	uint32_t	numMask:8;	/* # Mask Entries */
1811 	uint32_t	profile:8;	/* Selection Profile */
1812 	uint32_t	rsvd2:8;
1813 #endif
1814 #ifdef EMLXS_LITTLE_ENDIAN
1815 	uint32_t	rsvd2:8;
1816 	uint32_t	profile:8;	/* Selection Profile */
1817 	uint32_t	numMask:8;	/* # Mask Entries */
1818 	uint32_t	recvNotify:1;	/* Receive Notification */
1819 	uint32_t	rsvd1:7;
1820 #endif
1821 
1822 #ifdef EMLXS_BIG_ENDIAN
1823 	uint32_t	hbqId:16;
1824 	uint32_t	rsvd3:12;
1825 	uint32_t	ringMask:4;
1826 #endif
1827 #ifdef EMLXS_LITTLE_ENDIAN
1828 	uint32_t	ringMask:4;
1829 	uint32_t	rsvd3:12;
1830 	uint32_t	hbqId:16;
1831 #endif
1832 
1833 #ifdef EMLXS_BIG_ENDIAN
1834 	uint32_t	numEntries:16;
1835 	uint32_t	rsvd4:8;
1836 	uint32_t	headerLen:8;
1837 #endif
1838 #ifdef EMLXS_LITTLE_ENDIAN
1839 	uint32_t	headerLen:8;
1840 	uint32_t	rsvd4:8;
1841 	uint32_t	numEntries:16;
1842 #endif
1843 
1844 	uint32_t	hbqaddrLow;
1845 	uint32_t	hbqaddrHigh;
1846 
1847 #ifdef EMLXS_BIG_ENDIAN
1848 	uint32_t	rsvd5:31;
1849 	uint32_t	logEntry:1;
1850 #endif
1851 #ifdef EMLXS_LITTLE_ENDIAN
1852 	uint32_t	logEntry:1;
1853 	uint32_t	rsvd5:31;
1854 #endif
1855 
1856 	uint32_t	rsvd6;	/* w7 */
1857 	uint32_t	rsvd7;	/* w8 */
1858 	uint32_t	rsvd8;	/* w9 */
1859 
1860 	HBQ_MASK	hbqMasks[6];
1861 
1862 	union
1863 	{
1864 		uint32_t	allprofiles[12];
1865 
1866 		struct
1867 		{
1868 #ifdef EMLXS_BIG_ENDIAN
1869 			uint32_t	seqlenoff:16;
1870 			uint32_t	maxlen:16;
1871 #endif
1872 #ifdef EMLXS_LITTLE_ENDIAN
1873 			uint32_t	maxlen:16;
1874 			uint32_t	seqlenoff:16;
1875 #endif
1876 #ifdef EMLXS_BIG_ENDIAN
1877 			uint32_t	rsvd1:28;
1878 			uint32_t	seqlenbcnt:4;
1879 #endif
1880 #ifdef EMLXS_LITTLE_ENDIAN
1881 			uint32_t	seqlenbcnt:4;
1882 			uint32_t	rsvd1:28;
1883 #endif
1884 			uint32_t	rsvd[10];
1885 		} profile2;
1886 
1887 		struct
1888 		{
1889 #ifdef EMLXS_BIG_ENDIAN
1890 			uint32_t	seqlenoff:16;
1891 			uint32_t	maxlen:16;
1892 #endif
1893 #ifdef EMLXS_LITTLE_ENDIAN
1894 			uint32_t	maxlen:16;
1895 			uint32_t	seqlenoff:16;
1896 #endif
1897 #ifdef EMLXS_BIG_ENDIAN
1898 			uint32_t	cmdcodeoff:28;
1899 			uint32_t	rsvd1:12;
1900 			uint32_t	seqlenbcnt:4;
1901 #endif
1902 #ifdef EMLXS_LITTLE_ENDIAN
1903 			uint32_t	seqlenbcnt:4;
1904 			uint32_t	rsvd1:12;
1905 			uint32_t	cmdcodeoff:28;
1906 #endif
1907 			uint32_t	cmdmatch[8];
1908 
1909 			uint32_t	rsvd[2];
1910 		} profile3;
1911 
1912 		struct
1913 		{
1914 #ifdef EMLXS_BIG_ENDIAN
1915 			uint32_t	seqlenoff:16;
1916 			uint32_t	maxlen:16;
1917 #endif
1918 #ifdef EMLXS_LITTLE_ENDIAN
1919 			uint32_t	maxlen:16;
1920 			uint32_t	seqlenoff:16;
1921 #endif
1922 #ifdef EMLXS_BIG_ENDIAN
1923 			uint32_t	cmdcodeoff:28;
1924 			uint32_t	rsvd1:12;
1925 			uint32_t	seqlenbcnt:4;
1926 #endif
1927 #ifdef EMLXS_LITTLE_ENDIAN
1928 			uint32_t	seqlenbcnt:4;
1929 			uint32_t	rsvd1:12;
1930 			uint32_t	cmdcodeoff:28;
1931 #endif
1932 			uint32_t	cmdmatch[8];
1933 
1934 			uint32_t	rsvd[2];
1935 		} profile5;
1936 	} profiles;
1937 } CONFIG_HBQ_VAR;
1938 
1939 
1940 /* Structure for MB Command REG_VPI(0x96) */
1941 /* Good for SLI2/3 and SLI4 */
1942 
1943 typedef struct
1944 {
1945 #ifdef EMLXS_BIG_ENDIAN
1946 	uint32_t	rsvd1;
1947 	uint32_t	rsvd2:7;
1948 	uint32_t	upd:1;
1949 	uint32_t	sid:24;
1950 	uint32_t	portname[2];    /* N_PORT name */
1951 	uint32_t	rsvd5;
1952 	uint16_t	vfi;
1953 	uint16_t	vpi;
1954 #endif
1955 #ifdef EMLXS_LITTLE_ENDIAN
1956 	uint32_t	rsvd1;
1957 	uint32_t	sid:24;
1958 	uint32_t	upd:1;
1959 	uint32_t	rsvd2:7;
1960 	uint32_t	portname[2];    /* N_PORT name */
1961 	uint32_t	rsvd5;
1962 	uint16_t	vpi;
1963 	uint16_t	vfi;
1964 #endif
1965 } REG_VPI_VAR;
1966 
1967 /* Structure for MB Command INIT_VPI(0xA3) */
1968 /* Good for SLI4 only */
1969 
1970 typedef struct
1971 {
1972 #ifdef EMLXS_BIG_ENDIAN
1973 	uint16_t	vfi;
1974 	uint16_t	vpi;
1975 #endif
1976 #ifdef EMLXS_LITTLE_ENDIAN
1977 	uint16_t	vpi;
1978 	uint16_t	vfi;
1979 #endif
1980 } INIT_VPI_VAR;
1981 
1982 /* Structure for MB Command UNREG_VPI (0x97) */
1983 /* Good for SLI2/3 */
1984 
1985 typedef struct
1986 {
1987 	uint32_t	rsvd1;
1988 	uint32_t	rsvd2;
1989 	uint32_t	rsvd3;
1990 	uint32_t	rsvd4;
1991 	uint32_t	rsvd5;
1992 #ifdef EMLXS_BIG_ENDIAN
1993 	uint16_t	rsvd6;
1994 	uint16_t	vpi;
1995 #endif
1996 #ifdef EMLXS_LITTLE_ENDIAN
1997 	uint16_t	vpi;
1998 	uint16_t	rsvd6;
1999 #endif
2000 } UNREG_VPI_VAR;
2001 
2002 /* Structure for MB Command UNREG_VPI (0x97) */
2003 /* Good for SLI4 */
2004 
2005 typedef struct
2006 {
2007 	uint32_t	rsvd1;
2008 #ifdef EMLXS_BIG_ENDIAN
2009 	uint8_t		ii:2;
2010 	uint16_t	rsvd2:14;
2011 	uint16_t	index;
2012 #endif
2013 #ifdef EMLXS_LITTLE_ENDIAN
2014 	uint16_t	index;
2015 	uint16_t	rsvd2:14;
2016 	uint8_t		ii:2;
2017 #endif
2018 } UNREG_VPI_VAR4;
2019 
2020 /* Structure for MB Command REG_VFI(0x9F) */
2021 /* Good for SLI4 only */
2022 
2023 typedef struct
2024 {
2025 #ifdef EMLXS_BIG_ENDIAN
2026 	uint16_t	rsvd1:2;
2027 	uint16_t	upd:1;
2028 	uint16_t	vp:1;
2029 	uint16_t	rsvd2:12;
2030 	uint16_t	vfi;
2031 
2032 	uint16_t	vpi;
2033 	uint16_t	fcfi;
2034 
2035 	uint32_t	portname[2];    /* N_PORT name */
2036 
2037 	ULP_BDE64	bde;
2038 
2039 /* CHANGE with next firmware drop */
2040 	uint32_t	edtov;
2041 	uint32_t	ratov;
2042 
2043 	uint32_t	rsvd5:8;
2044 	uint32_t	sid:24;
2045 #endif
2046 #ifdef EMLXS_LITTLE_ENDIAN
2047 	uint16_t	vfi;
2048 	uint16_t	rsvd2:12;
2049 	uint16_t	vp:1;
2050 	uint16_t	upd:1;
2051 	uint16_t	rsvd1:2;
2052 
2053 	uint16_t	fcfi;
2054 	uint16_t	vpi;
2055 
2056 	uint32_t	portname[2];    /* N_PORT name */
2057 
2058 	ULP_BDE64	bde;
2059 
2060 /* CHANGE with next firmware drop */
2061 	uint32_t	edtov;
2062 	uint32_t	ratov;
2063 
2064 	uint32_t	sid:24;
2065 	uint32_t	rsvd5:8;
2066 #endif
2067 } REG_VFI_VAR;
2068 
2069 /* Structure for MB Command INIT_VFI(0xA4) */
2070 /* Good for SLI4 only */
2071 
2072 typedef struct
2073 {
2074 #ifdef EMLXS_BIG_ENDIAN
2075 	uint32_t	vr:1;
2076 	uint32_t	vt:1;
2077 	uint32_t	vf:1;
2078 	uint32_t	rsvd1:13;
2079 	uint32_t	vfi:16;
2080 
2081 	uint16_t	rsvd2;
2082 	uint16_t	fcfi;
2083 
2084 	uint32_t	rsvd3:16;
2085 	uint32_t	pri:3;
2086 	uint32_t	vf_id:12;
2087 	uint32_t	rsvd4:1;
2088 
2089 	uint32_t	hop_count:8;
2090 	uint32_t	rsvd5:24;
2091 #endif
2092 #ifdef EMLXS_LITTLE_ENDIAN
2093 	uint32_t	vfi:16;
2094 	uint32_t	rsvd1:13;
2095 	uint32_t	vf:1;
2096 	uint32_t	vt:1;
2097 	uint32_t	vr:1;
2098 
2099 	uint16_t	fcfi;
2100 	uint16_t	rsvd2;
2101 
2102 	uint32_t	rsvd4:1;
2103 	uint32_t	vf_id:12;
2104 	uint32_t	pri:3;
2105 	uint32_t	rsvd3:16;
2106 
2107 	uint32_t	rsvd5:24;
2108 	uint32_t	hop_count:8;
2109 #endif
2110 } INIT_VFI_VAR;
2111 
2112 /* Structure for MB Command UNREG_VFI (0xA1) */
2113 /* Good for SLI4 only */
2114 
2115 typedef struct
2116 {
2117 #ifdef EMLXS_BIG_ENDIAN
2118 	uint32_t	rsvd1:3;
2119 	uint32_t	vp:1;
2120 	uint32_t	rsvd2:28;
2121 
2122 	uint16_t	vpi;
2123 	uint16_t	vfi;
2124 #endif
2125 #ifdef EMLXS_LITTLE_ENDIAN
2126 	uint32_t	rsvd2:28;
2127 	uint32_t	vp:1;
2128 	uint32_t	rsvd1:3;
2129 
2130 	uint16_t	vfi;
2131 	uint16_t	vpi;
2132 #endif
2133 } UNREG_VFI_VAR;
2134 
2135 
2136 
2137 typedef struct
2138 {
2139 #ifdef EMLXS_BIG_ENDIAN
2140 	uint32_t	read_log:1;
2141 	uint32_t	clear_log:1;
2142 	uint32_t	mbox_rsp:1;
2143 	uint32_t	resv:28;
2144 #endif
2145 #ifdef EMLXS_LITTLE_ENDIAN
2146 	uint32_t	resv:28;
2147 	uint32_t	mbox_rsp:1;
2148 	uint32_t	clear_log:1;
2149 	uint32_t	read_log:1;
2150 #endif
2151 
2152 	uint32_t	offset;
2153 
2154 	union
2155 	{
2156 		ULP_BDE		sp;
2157 		ULP_BDE64	sp64;
2158 	} un;
2159 } READ_EVT_LOG_VAR;
2160 
2161 typedef struct
2162 {
2163 
2164 #ifdef EMLXS_BIG_ENDIAN
2165 	uint16_t	split_log_next;
2166 	uint16_t	log_next;
2167 
2168 	uint32_t	size;
2169 
2170 	uint32_t	format:8;
2171 	uint32_t	resv2:22;
2172 	uint32_t	log_level:1;
2173 	uint32_t	split_log:1;
2174 #endif
2175 #ifdef EMLXS_LITTLE_ENDIAN
2176 	uint16_t	log_next;
2177 	uint16_t	split_log_next;
2178 
2179 	uint32_t	size;
2180 
2181 	uint32_t	split_log:1;
2182 	uint32_t	log_level:1;
2183 	uint32_t	resv2:22;
2184 	uint32_t	format:8;
2185 #endif
2186 
2187 	uint32_t	offset;
2188 } LOG_STATUS_VAR;
2189 
2190 
2191 /* Structure for MB Command CONFIG_PORT (0x88) */
2192 typedef struct
2193 {
2194 #ifdef EMLXS_BIG_ENDIAN
2195 	uint32_t	cBE:1;
2196 	uint32_t	cET:1;
2197 	uint32_t	cHpcb:1;
2198 	uint32_t	rMA:1;
2199 	uint32_t	sli_mode:4;
2200 	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2201 					/* config block */
2202 #endif
2203 #ifdef EMLXS_LITTLE_ENDIAN
2204 	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2205 					/* config block */
2206 	uint32_t	sli_mode:4;
2207 	uint32_t	rMA:1;
2208 	uint32_t	cHpcb:1;
2209 	uint32_t	cET:1;
2210 	uint32_t	cBE:1;
2211 #endif
2212 
2213 	uint32_t	pcbLow;		/* bit 31:0 of memory based port */
2214 					/* config block */
2215 	uint32_t	pcbHigh; 	/* bit 63:32 of memory based port */
2216 					/* config block */
2217 	uint32_t	hbainit[5];
2218 
2219 #ifdef EMLXS_BIG_ENDIAN
2220 	uint32_t	hps:1; /* Host pointers in SLIM */
2221 	uint32_t	rsvd:31;
2222 #endif
2223 #ifdef EMLXS_LITTLE_ENDIAN
2224 	uint32_t	rsvd:31;
2225 	uint32_t	hps:1; /* Host pointers in SLIM */
2226 #endif
2227 
2228 #ifdef EMLXS_BIG_ENDIAN
2229 	uint32_t	rsvd1:24;
2230 	uint32_t	cmv:1;		/* Configure Max VPIs */
2231 	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2232 	uint32_t	csah:1;		/* Configure Synchronous Abort */
2233 					/* Handling */
2234 	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2235 	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2236 					/* Block */
2237 	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2238 					/* Buffer Management */
2239 	uint32_t	cmx:1;		/* Configure Max XRIs */
2240 	uint32_t	cmr:1;		/* Configure Max RPIs */
2241 #endif
2242 #ifdef EMLXS_LITTLE_ENDIAN
2243 	uint32_t	cmr:1;		/* Configure Max RPIs */
2244 	uint32_t	cmx:1;		/* Configure Max XRIs */
2245 	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2246 					/* Buffer Management */
2247 	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2248 					/* Block */
2249 	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2250 	uint32_t	csah:1;		/* Configure Synchronous Abort */
2251 					/* Handling */
2252 	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2253 	uint32_t	cmv:1;		/* Configure Max VPIs */
2254 	uint32_t	rsvd1:24;
2255 #endif
2256 #ifdef EMLXS_BIG_ENDIAN
2257 	uint32_t	rsvd2:19;	/* Reserved */
2258 	uint32_t	gdss:1;		/* Configure Data Security SLI */
2259 	uint32_t	rsvd3:3;	/* Reserved */
2260 	uint32_t	gbg:1;		/* Grant BlockGuard */
2261 	uint32_t	gmv:1;		/* Grant Max VPIs */
2262 	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2263 	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2264 	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2265 	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2266 	uint32_t	gerbm:1;	/* Grant ERBM Request */
2267 	uint32_t	gmx:1;		/* Grant Max XRIs */
2268 	uint32_t	gmr:1;		/* Grant Max RPIs */
2269 #endif
2270 #ifdef EMLXS_LITTLE_ENDIAN
2271 	uint32_t	gmr:1;		/* Grant Max RPIs */
2272 	uint32_t	gmx:1;		/* Grant Max XRIs */
2273 	uint32_t	gerbm:1;	/* Grant ERBM Request */
2274 	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2275 	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2276 	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2277 	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2278 	uint32_t	gmv:1;		/* Grant Max VPIs */
2279 	uint32_t	gbg:1;		/* Grant BlockGuard */
2280 	uint32_t	rsvd3:3;	/* Reserved */
2281 	uint32_t	gdss:1;		/* Configure Data Security SLI */
2282 	uint32_t	rsvd2:19;	/* Reserved */
2283 #endif
2284 
2285 #ifdef EMLXS_BIG_ENDIAN
2286 	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2287 	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2288 #endif
2289 #ifdef EMLXS_LITTLE_ENDIAN
2290 	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2291 	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2292 #endif
2293 
2294 #ifdef EMLXS_BIG_ENDIAN
2295 	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2296 	uint32_t	rsvd4:16;	/* Max HBQs Host expect to configure */
2297 #endif
2298 #ifdef EMLXS_LITTLE_ENDIAN
2299 	uint32_t	rsvd4:16;	/* Max HBQs Host expect to configure */
2300 	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2301 #endif
2302 
2303 	uint32_t	rsvd5;		/* Reserved */
2304 
2305 #ifdef EMLXS_BIG_ENDIAN
2306 	uint32_t	rsvd6:16;	/* Reserved */
2307 	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2308 #endif
2309 #ifdef EMLXS_LITTLE_ENDIAN
2310 	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2311 	uint32_t	rsvd6:16;	/* Reserved */
2312 #endif
2313 } CONFIG_PORT_VAR;
2314 
2315 /* Structure for MB Command REQUEST_FEATURES (0x9D) */
2316 /* Good for SLI4 only */
2317 
2318 typedef struct
2319 {
2320 #ifdef EMLXS_BIG_ENDIAN
2321 	uint32_t	rsvd1:31;
2322 	uint32_t	QueryMode:1;
2323 #endif
2324 #ifdef EMLXS_LITTLE_ENDIAN
2325 	uint32_t	QueryMode:1;
2326 	uint32_t	rsvd1:31;
2327 #endif
2328 
2329 	uint32_t	featuresRequested;
2330 	uint32_t	featuresEnabled;
2331 
2332 } REQUEST_FEATURES_VAR;
2333 
2334 #define	SLI4_FEATURE_INHIBIT_AUTO_ABTS		0x0001
2335 #define	SLI4_FEATURE_NPIV			0x0002
2336 #define	SLI4_FEATURE_DIF			0x0004
2337 #define	SLI4_FEATURE_VIRTUAL_FABRICS		0x0008
2338 #define	SLI4_FEATURE_FCP_INITIATOR		0x0010
2339 #define	SLI4_FEATURE_FCP_TARGET			0x0020
2340 #define	SLI4_FEATURE_FCP_COMBO			0x0040
2341 #define	SLI4_FEATURE_RSVD1			0x0080
2342 #define	SLI4_FEATURE_RQD			0x0100
2343 #define	SLI4_FEATURE_INHIBIT_AUTO_ABTS_R	0x0200
2344 #define	SLI4_FEATURE_HIGH_LOGIN_MODE		0x0400
2345 #define	SLI4_FEATURE_PERF_HINT			0x0800
2346 
2347 
2348 /* SLI-2 Port Control Block */
2349 
2350 /* SLIM POINTER */
2351 #define	SLIMOFF	0x30	/* WORD */
2352 
2353 typedef struct _SLI2_RDSC
2354 {
2355 	uint32_t	cmdEntries;
2356 	uint32_t	cmdAddrLow;
2357 	uint32_t	cmdAddrHigh;
2358 
2359 	uint32_t	rspEntries;
2360 	uint32_t	rspAddrLow;
2361 	uint32_t	rspAddrHigh;
2362 } SLI2_RDSC;
2363 
2364 typedef struct _PCB
2365 {
2366 #ifdef EMLXS_BIG_ENDIAN
2367 	uint32_t	type:8;
2368 #define	TYPE_NATIVE_SLI2	0x01;
2369 	uint32_t	feature:8;
2370 #define	FEATURE_INITIAL_SLI2	0x01;
2371 	uint32_t	rsvd:12;
2372 	uint32_t	maxRing:4;
2373 #endif
2374 #ifdef EMLXS_LITTLE_ENDIAN
2375 	uint32_t	maxRing:4;
2376 	uint32_t	rsvd:12;
2377 	uint32_t	feature:8;
2378 #define	FEATURE_INITIAL_SLI2	0x01;
2379 	uint32_t	type:8;
2380 #define	TYPE_NATIVE_SLI2	0x01;
2381 #endif
2382 
2383 	uint32_t	mailBoxSize;
2384 	uint32_t	mbAddrLow;
2385 	uint32_t	mbAddrHigh;
2386 
2387 	uint32_t	hgpAddrLow;
2388 	uint32_t	hgpAddrHigh;
2389 
2390 	uint32_t	pgpAddrLow;
2391 	uint32_t	pgpAddrHigh;
2392 	SLI2_RDSC	rdsc[MAX_RINGS_AVAILABLE];
2393 } PCB;
2394 
2395 /* NEW_FEATURE */
2396 typedef struct
2397 {
2398 #ifdef EMLXS_BIG_ENDIAN
2399 	uint32_t	rsvd0:27;
2400 	uint32_t	discardFarp:1;
2401 	uint32_t	IPEnable:1;
2402 	uint32_t	nodeName:1;
2403 	uint32_t	portName:1;
2404 	uint32_t	filterEnable:1;
2405 #endif
2406 #ifdef EMLXS_LITTLE_ENDIAN
2407 	uint32_t	filterEnable:1;
2408 	uint32_t	portName:1;
2409 	uint32_t	nodeName:1;
2410 	uint32_t	IPEnable:1;
2411 	uint32_t	discardFarp:1;
2412 	uint32_t	rsvd:27;
2413 #endif
2414 	NAME_TYPE	portname;
2415 	NAME_TYPE	nodename;
2416 	uint32_t	rsvd1;
2417 	uint32_t	rsvd2;
2418 	uint32_t	rsvd3;
2419 	uint32_t	IPAddress;
2420 } CONFIG_FARP_VAR;
2421 
2422 
2423 /* NEW_FEATURE */
2424 typedef struct
2425 {
2426 #ifdef EMLXS_BIG_ENDIAN
2427 	uint32_t	defaultMessageNumber:16;
2428 	uint32_t	rsvd1:3;
2429 	uint32_t	nid:5;
2430 	uint32_t	rsvd2:5;
2431 	uint32_t	defaultPresent:1;
2432 	uint32_t	addAssociations:1;
2433 	uint32_t	reportAssociations:1;
2434 #endif
2435 #ifdef EMLXS_LITTLE_ENDIAN
2436 	uint32_t	reportAssociations:1;
2437 	uint32_t	addAssociations:1;
2438 	uint32_t	defaultPresent:1;
2439 	uint32_t	rsvd2:5;
2440 	uint32_t	nid:5;
2441 	uint32_t	rsvd1:3;
2442 	uint32_t	defaultMessageNumber:16;
2443 #endif
2444 	uint32_t	attConditions;
2445 	uint8_t		attentionId[16];
2446 	uint16_t	messageNumberByHA[32];
2447 	uint16_t	messageNumberByID[16];
2448 	uint32_t	rsvd3;
2449 } CONFIG_MSI_VAR;
2450 
2451 
2452 /* NEW_FEATURE */
2453 typedef struct
2454 {
2455 #ifdef EMLXS_BIG_ENDIAN
2456 	uint32_t	defaultMessageNumber:8;
2457 	uint32_t	rsvd1:11;
2458 	uint32_t	nid:5;
2459 	uint32_t	rsvd2:5;
2460 	uint32_t	defaultPresent:1;
2461 	uint32_t	addAssociations:1;
2462 	uint32_t	reportAssociations:1;
2463 #endif
2464 #ifdef EMLXS_LITTLE_ENDIAN
2465 	uint32_t	reportAssociations:1;
2466 	uint32_t	addAssociations:1;
2467 	uint32_t	defaultPresent:1;
2468 	uint32_t	rsvd2:5;
2469 	uint32_t	nid:5;
2470 	uint32_t	rsvd1:11;
2471 	uint32_t	defaultMessageNumber:8;
2472 #endif
2473 	uint32_t	attConditions1;
2474 	uint32_t	attConditions2;
2475 	uint8_t		attentionId[16];
2476 	uint8_t		messageNumberByHA[64];
2477 	uint8_t		messageNumberByID[16];
2478 	uint32_t	autoClearByHA1;
2479 	uint32_t	autoClearByHA2;
2480 	uint32_t	autoClearByID;
2481 	uint32_t	resv3;
2482 } CONFIG_MSIX_VAR;
2483 
2484 
2485 /* Union of all Mailbox Command types */
2486 
2487 typedef union
2488 {
2489 	uint32_t		varWords[31];
2490 	LOAD_SM_VAR		varLdSM;	/* cmd =  1 (LOAD_SM) */
2491 	READ_NV_VAR		varRDnvp;	/* cmd =  2 (READ_NVPARMS) */
2492 	WRITE_NV_VAR		varWTnvp;	/* cmd =  3 (WRITE_NVPARMS) */
2493 	BIU_DIAG_VAR		varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG) */
2494 	INIT_LINK_VAR		varInitLnk;	/* cmd =  5 (INIT_LINK) */
2495 	DOWN_LINK_VAR		varDwnLnk;	/* cmd =  6 (DOWN_LINK) */
2496 	CONFIG_LINK		varCfgLnk;	/* cmd =  7 (CONFIG_LINK) */
2497 	PART_SLIM_VAR		varSlim;	/* cmd =  8 (PART_SLIM) */
2498 	CONFIG_RING_VAR		varCfgRing;	/* cmd =  9 (CONFIG_RING) */
2499 	RESET_RING_VAR		varRstRing;	/* cmd = 10 (RESET_RING) */
2500 	READ_CONFIG_VAR		varRdConfig;	/* cmd = 11 (READ_CONFIG) */
2501 	READ_RCONF_VAR		varRdRConfig;	/* cmd = 12 (READ_RCONFIG) */
2502 	READ_SPARM_VAR		varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
2503 	READ_STATUS_VAR		varRdStatus;	/* cmd = 14 (READ_STATUS) */
2504 	READ_RPI_VAR		varRdRPI;	/* cmd = 15 (READ_RPI(64)) */
2505 	READ_XRI_VAR		varRdXRI;	/* cmd = 16 (READ_XRI) */
2506 	READ_REV_VAR		varRdRev;	/* cmd = 17 (READ_REV) */
2507 	READ_LNK_VAR		varRdLnk;	/* cmd = 18 (READ_LNK_STAT) */
2508 	REG_LOGIN_VAR		varRegLogin;	/* cmd = 19 (REG_LOGIN(64)) */
2509 	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = 20 (UNREG_LOGIN) */
2510 	READ_LA_VAR		varReadLA;	/* cmd = 21 (READ_LA(64)) */
2511 	CLEAR_LA_VAR		varClearLA;	/* cmd = 22 (CLEAR_LA) */
2512 	DUMP_VAR		varDmp;		/* Warm Start DUMP mbx cmd */
2513 	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = 0x1b Warm Start */
2514 						/* UPDATE_CFG cmd */
2515 	DEL_LD_ENTRY_VAR	varDelLdEntry;	/* cmd = 0x1d (DEL_LD_ENTRY) */
2516 	UNREG_D_ID_VAR		varUnregDID;	/* cmd = 0x23 (UNREG_D_ID) */
2517 	CONFIG_FARP_VAR		varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP) */
2518 	CONFIG_MSI_VAR		varCfgMSI;	/* cmd = 0x90 (CONFIG_MSI) */
2519 	CONFIG_MSIX_VAR		varCfgMSIX;	/* cmd = 0x30 (CONFIG_MSIX) */
2520 	CONFIG_HBQ_VAR		varCfgHbq;	/* cmd = 0x7C (CONFIG_HBQ) */
2521 	LOAD_AREA_VAR		varLdArea;	/* cmd = 0x81 (LOAD_AREA) */
2522 	CONFIG_PORT_VAR		varCfgPort;	/* cmd = 0x88 (CONFIG_PORT) */
2523 	LOAD_EXP_ROM_VAR	varLdExpRom;	/* cmd = 0x9C (LOAD_XP_ROM) */
2524 	REG_VPI_VAR		varRegVpi;	/* cmd = 0x96 (REG_VPI) */
2525 	UNREG_VPI_VAR		varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
2526 	READ_EVT_LOG_VAR	varRdEvtLog;	/* cmd = 0x38 (READ_EVT_LOG) */
2527 	LOG_STATUS_VAR		varLogStat;	/* cmd = 0x37 */
2528 
2529 } MAILVARIANTS;
2530 
2531 #define	MAILBOX_CMD_BSIZE	128
2532 #define	MAILBOX_CMD_WSIZE	32
2533 
2534 /*
2535  * SLI-2 specific structures
2536  */
2537 
2538 typedef struct _SLI1_DESC
2539 {
2540 	emlxs_rings_t	mbxCring[4];
2541 	uint32_t	mbxUnused[24];
2542 } SLI1_DESC; /* 128 bytes */
2543 
2544 typedef struct
2545 {
2546 	uint32_t	cmdPutInx;
2547 	uint32_t	rspGetInx;
2548 } HGP;
2549 
2550 typedef struct
2551 {
2552 	uint32_t	cmdGetInx;
2553 	uint32_t	rspPutInx;
2554 } PGP;
2555 
2556 typedef struct _SLI2_DESC
2557 {
2558 	HGP		host[4];
2559 	PGP		port[4];
2560 	uint32_t	HBQ_PortGetIdx[16];
2561 } SLI2_DESC; /* 128 bytes */
2562 
2563 typedef union
2564 {
2565 	SLI1_DESC	s1;	/* 32 words, 128 bytes */
2566 	SLI2_DESC	s2;	/* 32 words, 128 bytes */
2567 } SLI_VAR;
2568 
2569 typedef volatile struct
2570 {
2571 #ifdef EMLXS_BIG_ENDIAN
2572 	uint16_t	mbxStatus;
2573 	uint8_t		mbxCommand;
2574 	uint8_t		mbxReserved:6;
2575 	uint8_t		mbxHc:1;
2576 	uint8_t		mbxOwner:1;	/* Low order bit first word */
2577 #endif
2578 #ifdef EMLXS_LITTLE_ENDIAN
2579 	uint8_t		mbxOwner:1;	/* Low order bit first word */
2580 	uint8_t		mbxHc:1;
2581 	uint8_t		mbxReserved:6;
2582 	uint8_t		mbxCommand;
2583 	uint16_t	mbxStatus;
2584 #endif
2585 	MAILVARIANTS	un;		/* 124 bytes */
2586 	SLI_VAR		us;		/* 128 bytes */
2587 } MAILBOX;				/* 256 bytes */
2588 
2589 
2590 
2591 /* SLI4 IOCTL Mailbox */
2592 /* ALL SLI4 specific mbox commands have a standard request /response header */
2593 /* Word 0 is just like SLI 3 */
2594 
2595 typedef struct mbox_req_hdr
2596 {
2597 #ifdef EMLXS_BIG_ENDIAN
2598 	uint32_t	domain:8;		/* word 6 */
2599 	uint32_t	port:8;
2600 	uint32_t	subsystem:8;
2601 	uint32_t	opcode:8;
2602 
2603 	uint32_t	timeout;		/* word 7 */
2604 
2605 	uint32_t	req_length;		/* word 8 */
2606 
2607 	uint32_t	reserved1:24;		/* word 9 */
2608 	uint32_t	version:8;		/* word 9 */
2609 #endif
2610 #ifdef EMLXS_LITTLE_ENDIAN
2611 	uint32_t	opcode:8;
2612 	uint32_t	subsystem:8;
2613 	uint32_t	port:8;
2614 	uint32_t	domain:8;		/* word 6 */
2615 
2616 	uint32_t	timeout;		/* word 7 */
2617 
2618 	uint32_t	req_length;		/* word 8 */
2619 
2620 	uint32_t	version:8;		/* word 9 */
2621 	uint32_t	reserved1:24;		/* word 9 */
2622 #endif
2623 
2624 } mbox_req_hdr_t;
2625 
2626 
2627 typedef struct mbox_req_hdr2
2628 {
2629 #ifdef EMLXS_BIG_ENDIAN
2630 	uint32_t	vf_number:16;		/* word 6 */
2631 	uint32_t	subsystem:8;
2632 	uint32_t	opcode:8;
2633 
2634 	uint32_t	timeout;		/* word 7 */
2635 
2636 	uint32_t	req_length;		/* word 8 */
2637 
2638 	uint32_t	vh_number:6;		/* word 9 */
2639 	uint32_t	pf_number:10;
2640 	uint32_t	reserved1:8;
2641 	uint32_t	version:8;
2642 #endif
2643 #ifdef EMLXS_LITTLE_ENDIAN
2644 	uint32_t	opcode:8;
2645 	uint32_t	subsystem:8;
2646 	uint32_t	vf_number:16;		/* word 6 */
2647 
2648 	uint32_t	timeout;		/* word 7 */
2649 
2650 	uint32_t	req_length;		/* word 8 */
2651 
2652 	uint32_t	version:8;
2653 	uint32_t	reserved1:8;
2654 	uint32_t	pf_number:10;
2655 	uint32_t	vh_number:6;		/* word 9 */
2656 #endif
2657 
2658 } mbox_req_hdr2_t;
2659 
2660 typedef struct mbox_rsp_hdr
2661 {
2662 #ifdef EMLXS_BIG_ENDIAN
2663 	uint32_t	domain:8;		/* word 6 */
2664 	uint32_t	reserved1:8;
2665 	uint32_t	subsystem:8;
2666 	uint32_t	opcode:8;
2667 
2668 	uint32_t	reserved2:16;		/* word 7 */
2669 	uint32_t	extra_status:8;
2670 	uint32_t	status:8;
2671 #endif
2672 #ifdef EMLXS_LITTLE_ENDIAN
2673 	uint32_t	opcode:8;
2674 	uint32_t	subsystem:8;
2675 	uint32_t	reserved1:8;
2676 	uint32_t	domain:8;		/* word 6 */
2677 
2678 	uint32_t	status:8;
2679 	uint32_t	extra_status:8;
2680 	uint32_t	reserved2:16;		/* word 7 */
2681 #endif
2682 	uint32_t	rsp_length;		/* word 8 */
2683 	uint32_t	allocated_length;	/* word 9 */
2684 } mbox_rsp_hdr_t;
2685 
2686 #define	MBX_RSP_STATUS_SUCCESS		0x00
2687 #define	MBX_RSP_STATUS_FAILED		0x01
2688 #define	MBX_RSP_STATUS_ILLEGAL_REQ	0x02
2689 #define	MBX_RSP_STATUS_ILLEGAL_FIELD	0x03
2690 #define	MBX_RSP_STATUS_FCF_IN_USE	0x3A
2691 #define	MBX_RSP_STATUS_NO_FCF		0x43
2692 
2693 #define	MGMT_ADDI_STATUS_INCOMPATIBLE	0xA2
2694 
2695 typedef struct be_req_hdr
2696 {
2697 #ifdef EMLXS_BIG_ENDIAN
2698 	uint32_t	special:8;		/* word 1 */
2699 	uint32_t	reserved2:16;		/* word 1 */
2700 	uint32_t	sge_cnt:5;		/* word 1 */
2701 	uint32_t	reserved1:2;		/* word 1 */
2702 	uint32_t	embedded:1;		/* word 1 */
2703 #endif
2704 #ifdef EMLXS_LITTLE_ENDIAN
2705 	uint32_t	embedded:1;		/* word 1 */
2706 	uint32_t	reserved1:2;		/* word 1 */
2707 	uint32_t	sge_cnt:5;		/* word 1 */
2708 	uint32_t	reserved2:16;		/* word 1 */
2709 	uint32_t	special:8;		/* word 1 */
2710 #endif
2711 	uint32_t	payload_length;		/* word 2 */
2712 	uint32_t	tag_low;		/* word 3 */
2713 	uint32_t	tag_hi;			/* word 4 */
2714 	uint32_t	reserved3;		/* word 5 */
2715 	union
2716 	{
2717 		mbox_req_hdr_t	hdr_req;
2718 		mbox_req_hdr2_t hdr_req2;
2719 		mbox_rsp_hdr_t	hdr_rsp;
2720 	} un_hdr;
2721 } be_req_hdr_t;
2722 
2723 #define	EMLXS_MAX_NONEMBED_SIZE		(1024 * 64)
2724 
2725 /* SLI_CONFIG Mailbox commands */
2726 
2727 #define	IOCTL_SUBSYSTEM_COMMON			0x01
2728 #define	IOCTL_SUBSYSTEM_FCOE			0x0C
2729 #define	IOCTL_SUBSYSTEM_DCBX			0x10
2730 
2731 #define	COMMON_OPCODE_READ_FLASHROM		0x06
2732 #define	COMMON_OPCODE_WRITE_FLASHROM		0x07
2733 #define	COMMON_OPCODE_CQ_CREATE			0x0C
2734 #define	COMMON_OPCODE_EQ_CREATE			0x0D
2735 #define	COMMON_OPCODE_MQ_CREATE 		0x15
2736 #define	COMMON_OPCODE_GET_CNTL_ATTRIB		0x20
2737 #define	COMMON_OPCODE_NOP			0x21
2738 #define	COMMON_OPCODE_QUERY_FIRMWARE_CONFIG	0x3A
2739 #define	COMMON_OPCODE_RESET			0x3D
2740 #define	COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1	0x3E
2741 
2742 #define	COMMON_OPCODE_GET_BOOT_CFG		0x42
2743 #define	COMMON_OPCODE_SET_BOOT_CFG		0x43
2744 #define	COMMON_OPCODE_MANAGE_FAT		0x44
2745 #define	COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1	0x47
2746 #define	COMMON_OPCODE_GET_PORT_NAME		0x4D
2747 
2748 #define	COMMON_OPCODE_MQ_CREATE_EXT		0x5A
2749 #define	COMMON_OPCODE_GET_VPD_DATA		0x5B
2750 #define	COMMON_OPCODE_GET_PHY_DETAILS		0x66
2751 #define	COMMON_OPCODE_SEND_ACTIVATION		0x73
2752 #define	COMMON_OPCODE_RESET_LICENSES		0x74
2753 #define	COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB	0x79
2754 
2755 #define	COMMON_OPCODE_GET_EXTENTS_INFO		0x9A
2756 #define	COMMON_OPCODE_GET_EXTENTS		0x9B
2757 #define	COMMON_OPCODE_ALLOC_EXTENTS		0x9C
2758 #define	COMMON_OPCODE_DEALLOC_EXTENTS		0x9D
2759 
2760 #define	COMMON_OPCODE_GET_PROFILE_CAPS		0xA1
2761 #define	COMMON_OPCODE_GET_MR_PROFILE_CAPS	0xA2
2762 #define	COMMON_OPCODE_SET_MR_PROFILE_CAPS	0xA3
2763 #define	COMMON_OPCODE_GET_PROFILE_CFG		0xA4
2764 #define	COMMON_OPCODE_SET_PROFILE_CFG		0xA5
2765 #define	COMMON_OPCODE_GET_PROFILE_LIST		0xA6
2766 #define	COMMON_OPCODE_GET_ACTIVE_PROFILE	0xA7
2767 #define	COMMON_OPCODE_SET_ACTIVE_PROFILE	0xA8
2768 #define	COMMON_OPCODE_SET_FACTORY_PROFILE_CFG	0xA9
2769 
2770 #define	COMMON_OPCODE_READ_OBJ			0xAB
2771 #define	COMMON_OPCODE_WRITE_OBJ			0xAC
2772 #define	COMMON_OPCODE_READ_OBJ_LIST		0xAD
2773 #define	COMMON_OPCODE_DELETE_OBJ		0xAE
2774 #define	COMMON_OPCODE_GET_SLI4_PARAMS		0xB5
2775 
2776 #define	FCOE_OPCODE_WQ_CREATE			0x01
2777 #define	FCOE_OPCODE_CFG_POST_SGL_PAGES		0x03
2778 #define	FCOE_OPCODE_RQ_CREATE			0x05
2779 #define	FCOE_OPCODE_READ_FCF_TABLE		0x08
2780 #define	FCOE_OPCODE_ADD_FCF_TABLE		0x09
2781 #define	FCOE_OPCODE_DELETE_FCF_TABLE		0x0A
2782 #define	FCOE_OPCODE_POST_HDR_TEMPLATES		0x0B
2783 #define	FCOE_OPCODE_REDISCOVER_FCF_TABLE	0x10
2784 #define	FCOE_OPCODE_SET_FCLINK_SETTINGS		0x21
2785 
2786 #define	DCBX_OPCODE_GET_DCBX_MODE		0x04
2787 #define	DCBX_OPCODE_SET_DCBX_MODE		0x05
2788 
2789 typedef	struct
2790 {
2791 	struct
2792 	{
2793 		uint32_t opcode;
2794 #define	MGMT_FLASHROM_OPCODE_FLASH		1
2795 #define	MGMT_FLASHROM_OPCODE_SAVE		2
2796 #define	MGMT_FLASHROM_OPCODE_CLEAR		3
2797 #define	MGMT_FLASHROM_OPCODE_REPORT		4
2798 #define	MGMT_FLASHROM_OPCODE_INFO		5
2799 #define	MGMT_FLASHROM_OPCODE_CRC		6
2800 #define	MGMT_FLASHROM_OPCODE_OFFSET_FLASH	7
2801 #define	MGMT_FLASHROM_OPCODE_OFFSET_SAVE	8
2802 #define	MGMT_PHY_FLASHROM_OPCODE_FLASH		9
2803 #define	MGMT_PHY_FLASHROM_OPCODE_SAVE		10
2804 
2805 		uint32_t optype;
2806 #define	MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE	0
2807 #define	MGMT_FLASHROM_OPTYPE_REDBOOT		1
2808 #define	MGMT_FLASHROM_OPTYPE_ISCSI_BIOS		2
2809 #define	MGMT_FLASHROM_OPTYPE_PXE_BIOS		3
2810 #define	MGMT_FLASHROM_OPTYPE_CTRLS		4
2811 #define	MGMT_FLASHROM_OPTYPE_CFG_IPSEC		5
2812 #define	MGMT_FLASHROM_OPTYPE_CFG_INI		6
2813 #define	MGMT_FLASHROM_OPTYPE_ROM_OFFSET		7
2814 #define	MGMT_FLASHROM_OPTYPE_FCOE_BIOS		8
2815 #define	MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP	9
2816 #define	MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE	10
2817 #define	MGMT_FLASHROM_OPTYPE_FCOE_BACKUP	11
2818 #define	MGMT_FLASHROM_OPTYPE_CTRLP		12
2819 #define	MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE	13
2820 #define	MGMT_FLASHROM_OPTYPE_CFG_NIC		14
2821 #define	MGMT_FLASHROM_OPTYPE_CFG_DCBX		15
2822 #define	MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS	16
2823 #define	MGMT_FLASHROM_OPTYPE_CFG_ALL		17
2824 #define	MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE	0xff /* Driver defined */
2825 
2826 		uint32_t data_buffer_size; /* Align to 4KB */
2827 		uint32_t offset;
2828 		uint32_t data_buffer; /* image starts here */
2829 
2830 	} params;
2831 
2832 } IOCTL_COMMON_FLASHROM;
2833 
2834 
2835 typedef	struct
2836 {
2837 	union
2838 	{
2839 		struct
2840 		{
2841 			uint32_t rsvd;
2842 		} request;
2843 
2844 
2845 		struct
2846 		{
2847 #ifdef EMLXS_BIG_ENDIAN
2848 			uint16_t interface_type;
2849 			uint16_t phy_type;
2850 #endif
2851 #ifdef EMLXS_LITTLE_ENDIAN
2852 			uint16_t phy_type;
2853 			uint16_t interface_type;
2854 #endif
2855 
2856 /* phy_type */
2857 #define	PHY_XAUI		0x0
2858 #define	PHY_AEL_2020		0x1 /* eluris/Netlogic */
2859 #define	PHY_LSI_BRCM1		0x2 /* Peak pre-production board */
2860 #define	PHY_LSI_BRCM2		0x3 /* Peak production board */
2861 #define	PHY_SOLARFLARE		0x4 /* Dell recommended */
2862 #define	PHY_AMCC_QT2025		0x5 /* AMCC PHY */
2863 #define	PHY_AMCC_QT2225		0x6 /* AMCC PHY */
2864 #define	PHY_BRCM_5931		0x7 /* Broadcom Phy used by HP LOM */
2865 #define	PHY_BE3_INTERNAL_10GB	0x8 /* Internal 10GbPHY in BE3 */
2866 #define	PHY_BE3_INTERNAL_1GB	0x9 /* Internal 1Gb PHY in BE3 */
2867 #define	PHY_TN_2022		0xa /* Teranetics dual port 65nm PHY */
2868 #define	PHY_MARVELL_88E1340	0xb /* Marvel 1G PHY */
2869 #define	PHY_MARVELL_88E1322	0xc /* Marvel 1G PHY */
2870 #define	PHY_TN_8022		0xd /* Teranetics dual port 40nm PHY */
2871 #define	PHY_TYPE_NOT_SUPPORTED
2872 
2873 /* interface_type */
2874 #define	CX4_10GB_TYPE		0x0
2875 #define	XFP_10GB_TYPE		0x1
2876 #define	SFP_1GB_TYPE		0x2
2877 #define	SFP_PLUS_10GB_TYPE	0x3
2878 #define	KR_10GB_TYPE		0x4
2879 #define	KX4_10GB_TYPE		0x5
2880 #define	BASET_10GB_TYPE		0x6 /* 10G BaseT */
2881 #define	BASET_1000_TYPE		0x7 /* 1000 BaseT */
2882 #define	BASEX_1000_TYPE		0x8 /* 1000 BaseX */
2883 #define	SGMII_TYPE		0x9
2884 #define	INTERFACE_10GB_DISABLED	0xff /* Interface type not supported */
2885 
2886 			uint32_t misc_params;
2887 			uint32_t rsvd[4];
2888 		} response;
2889 
2890 	} params;
2891 
2892 } IOCTL_COMMON_GET_PHY_DETAILS;
2893 
2894 
2895 typedef	struct
2896 {
2897 	union
2898 	{
2899 		struct
2900 		{
2901 			uint32_t rsvd;
2902 		} request;
2903 
2904 
2905 		struct
2906 		{
2907 #ifdef EMLXS_BIG_ENDIAN
2908 			uint8_t port3_name;
2909 			uint8_t port2_name;
2910 			uint8_t port1_name;
2911 			uint8_t port0_name;
2912 #endif
2913 #ifdef EMLXS_LITTLE_ENDIAN
2914 			uint8_t port0_name;
2915 			uint8_t port1_name;
2916 			uint8_t port2_name;
2917 			uint8_t port3_name;
2918 #endif
2919 		} response;
2920 
2921 	} params;
2922 
2923 } IOCTL_COMMON_GET_PORT_NAME;
2924 
2925 
2926 typedef	struct
2927 {
2928 	union
2929 	{
2930 		struct
2931 		{
2932 #ifdef EMLXS_BIG_ENDIAN
2933 			uint32_t rsvd:30;
2934 			uint32_t pt:2;
2935 #endif
2936 #ifdef EMLXS_LITTLE_ENDIAN
2937 			uint32_t pt:2;
2938 			uint32_t rsvd:30;
2939 #endif
2940 #define	PORT_TYPE_GIGE		0
2941 #define	PORT_TYPE_FC		1
2942 		} request;
2943 
2944 
2945 		struct
2946 		{
2947 #ifdef EMLXS_BIG_ENDIAN
2948 			uint8_t port3_name;
2949 			uint8_t port2_name;
2950 			uint8_t port1_name;
2951 			uint8_t port0_name;
2952 #endif
2953 #ifdef EMLXS_LITTLE_ENDIAN
2954 			uint8_t port0_name;
2955 			uint8_t port1_name;
2956 			uint8_t port2_name;
2957 			uint8_t port3_name;
2958 #endif
2959 		} response;
2960 
2961 	} params;
2962 
2963 } IOCTL_COMMON_GET_PORT_NAME_V1;
2964 
2965 
2966 typedef	struct
2967 {
2968 	union
2969 	{
2970 		struct
2971 		{
2972 			uint32_t fat_operation;
2973 #define	RETRIEVE_FAT		0
2974 #define	QUERY_FAT		1
2975 #define	CLEAR_FAT		2
2976 
2977 			uint32_t read_log_offset;
2978 			uint32_t read_log_length;
2979 			uint32_t data_buffer_size;
2980 			uint32_t data_buffer;
2981 		} request;
2982 
2983 		struct
2984 		{
2985 			uint32_t log_size;
2986 			uint32_t read_log_length;
2987 			uint32_t rsvd0;
2988 			uint32_t rsvd1;
2989 			uint32_t data_buffer;
2990 		} response;
2991 
2992 	} params;
2993 
2994 } IOCTL_COMMON_MANAGE_FAT;
2995 
2996 
2997 typedef	struct
2998 {
2999 	union
3000 	{
3001 		struct
3002 		{
3003 #ifdef EMLXS_BIG_ENDIAN
3004 			uint32_t EOF:1; /* word 4 */
3005 			uint32_t rsvd0:7;
3006 			uint32_t desired_write_length:24;
3007 #endif
3008 #ifdef EMLXS_LITTLE_ENDIAN
3009 			uint32_t desired_write_length:24;
3010 			uint32_t rsvd0:7;
3011 			uint32_t EOF:1;  /* word 4 */
3012 #endif
3013 			uint32_t write_offset;  /* word 5 */
3014 			char object_name[(4 * 26)];   /* word 6 - 31 */
3015 			uint32_t buffer_desc_count; /* word 32 */
3016 
3017 #ifdef EMLXS_BIG_ENDIAN
3018 			uint32_t rsvd:8; /* word 33 */
3019 			uint32_t buffer_length:24;
3020 #endif
3021 #ifdef EMLXS_LITTLE_ENDIAN
3022 			uint32_t buffer_length:24;
3023 			uint32_t rsvd:8; /* word 33 */
3024 #endif
3025 			uint32_t buffer_addrlo; /* word 34 */
3026 			uint32_t buffer_addrhi; /* word 35 */
3027 		} request;
3028 
3029 		struct
3030 		{
3031 			uint32_t actual_write_length;
3032 
3033 #ifdef EMLXS_BIG_ENDIAN
3034 			uint32_t rsvd:24;
3035 			uint32_t change_status:8;
3036 #endif
3037 #ifdef EMLXS_LITTLE_ENDIAN
3038 			uint32_t change_status:8;
3039 			uint32_t rsvd:24;
3040 #endif
3041 #define	CS_NO_RESET		0
3042 #define	CS_REBOOT_RQD		1
3043 #define	CS_FW_RESET_RQD		2
3044 #define	CS_PROTO_RESET_RQD	3
3045 		} response;
3046 
3047 	} params;
3048 
3049 } IOCTL_COMMON_WRITE_OBJECT;
3050 
3051 
3052 typedef	struct
3053 {
3054 	union
3055 	{
3056 		struct
3057 		{
3058 #ifdef EMLXS_BIG_ENDIAN
3059 			uint32_t descriptor_offset:16; /* word 4 */
3060 			uint32_t descriptor_count:16;
3061 #endif
3062 #ifdef EMLXS_LITTLE_ENDIAN
3063 			uint32_t descriptor_count:16;
3064 			uint32_t descriptor_offset:16; /* word 4 */
3065 #endif
3066 			uint32_t reserved;  /* word 5 */
3067 			char object_name[(4 * 26)];   /* word 6 - 31 */
3068 			uint32_t buffer_desc_count; /* word 32 */
3069 
3070 #ifdef EMLXS_BIG_ENDIAN
3071 			uint32_t rsvd:8; /* word 33 */
3072 			uint32_t buffer_length:24;
3073 #endif
3074 #ifdef EMLXS_LITTLE_ENDIAN
3075 			uint32_t buffer_length:24;
3076 			uint32_t rsvd:8; /* word 33 */
3077 #endif
3078 			uint32_t buffer_addrlo; /* word 34 */
3079 			uint32_t buffer_addrhi; /* word 35 */
3080 		} request;
3081 
3082 		struct
3083 		{
3084 #ifdef EMLXS_BIG_ENDIAN
3085 			uint32_t reserved:16;
3086 			uint32_t actual_descriptor_count:16;
3087 #endif
3088 #ifdef EMLXS_LITTLE_ENDIAN
3089 			uint32_t actual_descriptor_count:16;
3090 			uint32_t reserved:16;
3091 #endif
3092 		} response;
3093 
3094 	} params;
3095 
3096 } IOCTL_COMMON_READ_OBJECT_LIST;
3097 
3098 
3099 typedef	struct
3100 {
3101 	union
3102 	{
3103 		struct
3104 		{
3105 #ifdef EMLXS_BIG_ENDIAN
3106 			uint32_t reserved:16; /* word 4 */
3107 			uint32_t boot_instance:8;
3108 			uint32_t boot_status:8;
3109 #endif
3110 #ifdef EMLXS_LITTLE_ENDIAN
3111 			uint32_t boot_status:8;
3112 			uint32_t boot_instance:8;
3113 			uint32_t reserved:16; /* word 4 */
3114 #endif
3115 		} request;
3116 
3117 		struct
3118 		{
3119 #ifdef EMLXS_BIG_ENDIAN
3120 			uint32_t reserved:16; /* word 4 */
3121 			uint32_t boot_instance:8;
3122 			uint32_t boot_status:8;
3123 #endif
3124 #ifdef EMLXS_LITTLE_ENDIAN
3125 			uint32_t boot_status:8;
3126 			uint32_t boot_instance:8;
3127 			uint32_t reserved:16; /* word 4 */
3128 #endif
3129 		} response;
3130 
3131 	} params;
3132 
3133 } IOCTL_COMMON_BOOT_CFG;
3134 
3135 
3136 /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
3137 typedef struct _BE_FW_CFG
3138 {
3139 	uint32_t	BEConfigNumber;
3140 	uint32_t	ASICRevision;
3141 	uint32_t	PhysicalPort;
3142 	uint32_t	FunctionMode;
3143 	uint32_t	ULPMode;
3144 
3145 } BE_FW_CFG;
3146 
3147 typedef	struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3148 {
3149 	union
3150 	{
3151 		struct
3152 		{
3153 			uint32_t	rsvd0;
3154 		} request;
3155 
3156 		BE_FW_CFG	response;
3157 
3158 	}	params;
3159 
3160 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3161 
3162 
3163 
3164 /* IOCTL_FCOE_READ_FCF_TABLE */
3165 typedef struct
3166 {
3167 	uint32_t	max_recv_size;
3168 	uint32_t	fka_adv_period;
3169 	uint32_t	fip_priority;
3170 
3171 #ifdef EMLXS_BIG_ENDIAN
3172 	uint8_t		fcf_mac_address_hi[4];
3173 
3174 	uint8_t		mac_address_provider;
3175 	uint8_t		fcf_available;
3176 	uint8_t		fcf_mac_address_low[2];
3177 
3178 	uint8_t		fabric_name_identifier[8];
3179 
3180 	uint8_t		fcf_sol:1;
3181 	uint8_t		rsvd0:5;
3182 	uint8_t		fcf_fc:1;
3183 	uint8_t		fcf_valid:1;
3184 	uint8_t		fc_map[3];
3185 
3186 	uint16_t	fcf_state;
3187 	uint16_t	fcf_index;
3188 #endif
3189 #ifdef EMLXS_LITTLE_ENDIAN
3190 	uint8_t		fcf_mac_address_hi[4];
3191 
3192 	uint8_t		fcf_mac_address_low[2];
3193 	uint8_t		fcf_available;
3194 	uint8_t		mac_address_provider;
3195 
3196 	uint8_t		fabric_name_identifier[8];
3197 
3198 	uint8_t		fc_map[3];
3199 	uint8_t		fcf_valid:1;
3200 	uint8_t		fcf_fc:1;
3201 	uint8_t		rsvd0:5;
3202 	uint8_t		fcf_sol:1;
3203 
3204 	uint16_t	fcf_index;
3205 	uint16_t	fcf_state;
3206 #endif
3207 
3208 	uint8_t		vlan_bitmap[512];
3209 	uint8_t		switch_name_identifier[8];
3210 
3211 } FCF_RECORD_t;
3212 
3213 #define	EMLXS_FCOE_MAX_RCV_SZ	0x800
3214 
3215 /* defines for mac_address_provider */
3216 #define	EMLXS_MAM_BOTH	0	/* Both SPMA and FPMA */
3217 #define	EMLXS_MAM_FPMA	1	/* Fabric Provided MAC Address */
3218 #define	EMLXS_MAM_SPMA	2	/* Server Provided MAC Address */
3219 
3220 typedef struct
3221 {
3222 	union
3223 	{
3224 		struct
3225 		{
3226 #ifdef EMLXS_BIG_ENDIAN
3227 			uint16_t	rsvd0;
3228 			uint16_t	fcf_index;
3229 #endif
3230 #ifdef EMLXS_LITTLE_ENDIAN
3231 			uint16_t	fcf_index;
3232 			uint16_t	rsvd0;
3233 #endif
3234 
3235 		} request;
3236 
3237 		struct
3238 		{
3239 			uint32_t	event_tag;
3240 #ifdef EMLXS_BIG_ENDIAN
3241 			uint16_t	rsvd0;
3242 			uint16_t	next_valid_fcf_index;
3243 #endif
3244 #ifdef EMLXS_LITTLE_ENDIAN
3245 			uint16_t	next_valid_fcf_index;
3246 			uint16_t	rsvd0;
3247 #endif
3248 			FCF_RECORD_t fcf_entry[1];
3249 
3250 		} response;
3251 
3252 	} params;
3253 
3254 } IOCTL_FCOE_READ_FCF_TABLE;
3255 
3256 
3257 /* IOCTL_FCOE_ADD_FCF_TABLE */
3258 typedef struct
3259 {
3260 	union
3261 	{
3262 		struct
3263 		{
3264 #ifdef EMLXS_BIG_ENDIAN
3265 			uint16_t	rsvd0;
3266 			uint16_t	fcf_index;
3267 #endif
3268 #ifdef EMLXS_LITTLE_ENDIAN
3269 			uint16_t	fcf_index;
3270 			uint16_t	rsvd0;
3271 #endif
3272 			FCF_RECORD_t fcf_entry;
3273 
3274 		} request;
3275 	} params;
3276 
3277 } IOCTL_FCOE_ADD_FCF_TABLE;
3278 
3279 
3280 /* IOCTL_FCOE_DELETE_FCF_TABLE */
3281 typedef struct
3282 {
3283 	union
3284 	{
3285 		struct
3286 		{
3287 #ifdef EMLXS_BIG_ENDIAN
3288 			uint16_t	fcf_indexes[1];
3289 			uint16_t	fcf_count;
3290 #endif
3291 #ifdef EMLXS_LITTLE_ENDIAN
3292 			uint16_t	fcf_count;
3293 			uint16_t	fcf_indexes[1];
3294 #endif
3295 
3296 		} request;
3297 	} params;
3298 
3299 } IOCTL_FCOE_DELETE_FCF_TABLE;
3300 
3301 
3302 /* IOCTL_FCOE_REDISCOVER_FCF_TABLE */
3303 typedef struct
3304 {
3305 	union
3306 	{
3307 		struct
3308 		{
3309 #ifdef EMLXS_BIG_ENDIAN
3310 			uint16_t	rsvd0;
3311 			uint16_t	fcf_count;
3312 #endif
3313 #ifdef EMLXS_LITTLE_ENDIAN
3314 			uint16_t	fcf_count;
3315 			uint16_t	rsvd0;
3316 #endif
3317 			uint32_t	rsvd1;
3318 			uint16_t	fcf_index[1];
3319 
3320 		} request;
3321 	} params;
3322 
3323 } IOCTL_FCOE_REDISCOVER_FCF_TABLE;
3324 
3325 
3326 #define	FCOE_FCF_MAC0	0x0E
3327 #define	FCOE_FCF_MAC1	0xFC
3328 #define	FCOE_FCF_MAC2	0x00
3329 #define	FCOE_FCF_MAC3	0xFF
3330 #define	FCOE_FCF_MAC4	0xFF
3331 #define	FCOE_FCF_MAC5	0xFE
3332 
3333 #define	FCOE_FCF_MAP0	0x0E
3334 #define	FCOE_FCF_MAP1	0xFC
3335 #define	FCOE_FCF_MAP2	0x00
3336 
3337 #define	MGMT_STATUS_FCF_IN_USE	0x3a
3338 
3339 /* IOCTL_COMMON_NOP */
3340 typedef	struct _IOCTL_COMMON_NOP
3341 {
3342 	union
3343 	{
3344 		struct
3345 		{
3346 			uint64_t	context;
3347 		} request;
3348 
3349 		struct
3350 		{
3351 			uint64_t	context;
3352 		} response;
3353 
3354 	} params;
3355 
3356 } IOCTL_COMMON_NOP;
3357 
3358 
3359 /*	Context for EQ create	*/
3360 typedef	struct _EQ_CONTEXT
3361 {
3362 #ifdef EMLXS_BIG_ENDIAN
3363 	uint32_t	Size:1;
3364 	uint32_t	Rsvd2:1;
3365 	uint32_t	Valid:1;
3366 	uint32_t	Rsvd1:29;
3367 
3368 	uint32_t	Armed:1;
3369 	uint32_t	Rsvd4:2;
3370 	uint32_t	Count:3;
3371 	uint32_t	Rsvd3:26;
3372 
3373 	uint32_t	Rsvd6:9;
3374 	uint32_t	DelayMult:10;
3375 	uint32_t	Rsvd5:13;
3376 #endif
3377 #ifdef EMLXS_LITTLE_ENDIAN
3378 	uint32_t	Rsvd1:29;
3379 	uint32_t	Valid:1;
3380 	uint32_t	Rsvd2:1;
3381 	uint32_t	Size:1;
3382 
3383 	uint32_t	Rsvd3:26;
3384 	uint32_t	Count:3;
3385 	uint32_t	Rsvd4:2;
3386 	uint32_t	Armed:1;
3387 
3388 	uint32_t	Rsvd5:13;
3389 	uint32_t	DelayMult:10;
3390 	uint32_t	Rsvd6:9;
3391 #endif
3392 
3393 	uint32_t	Rsvd7;
3394 
3395 } EQ_CONTEXT;
3396 
3397 
3398 /* define for Count field */
3399 #define	EQ_ELEMENT_COUNT_1024	2
3400 #define	EQ_ELEMENT_COUNT_2048	3
3401 #define	EQ_ELEMENT_COUNT_4096	4
3402 
3403 /* define for Size field */
3404 #define	EQ_ELEMENT_SIZE_4	0
3405 
3406 /* define for DelayMullt - used for interrupt coalescing */
3407 #define	EQ_DELAY_MULT		64
3408 
3409 /*	Context for CQ create	*/
3410 typedef	struct _CQ_CONTEXT
3411 {
3412 #ifdef EMLXS_BIG_ENDIAN
3413 	uint32_t	Eventable:1;
3414 	uint32_t	Rsvd3:1;
3415 	uint32_t	Valid:1;
3416 	uint32_t	Count:2;
3417 	uint32_t	Rsvd2:12;
3418 	uint32_t	NoDelay:1;
3419 	uint32_t	CoalesceWM:2;
3420 	uint32_t	Rsvd1:12;
3421 
3422 	uint32_t	Armed:1;
3423 	uint32_t	Rsvd5:1;
3424 	uint32_t	EQId:8;
3425 	uint32_t	Rsvd4:22;
3426 
3427 	uint32_t	Rsvd6;
3428 #endif
3429 #ifdef EMLXS_LITTLE_ENDIAN
3430 	uint32_t	Rsvd1:12;
3431 	uint32_t	CoalesceWM:2;
3432 	uint32_t	NoDelay:1;
3433 	uint32_t	Rsvd2:12;
3434 	uint32_t	Count:2;
3435 	uint32_t	Valid:1;
3436 	uint32_t	Rsvd3:1;
3437 	uint32_t	Eventable:1;
3438 
3439 	uint32_t	Rsvd4:22;
3440 	uint32_t	EQId:8;
3441 	uint32_t	Rsvd5:1;
3442 	uint32_t	Armed:1;
3443 
3444 	uint32_t	Rsvd6;
3445 #endif
3446 
3447 	uint32_t	Rsvd7;
3448 
3449 } CQ_CONTEXT;
3450 
3451 typedef	struct _CQ_CONTEXT_V2
3452 {
3453 #ifdef EMLXS_BIG_ENDIAN
3454 	uint32_t	Eventable:1;
3455 	uint32_t	Rsvd3:1;
3456 	uint32_t	Valid:1;
3457 	uint32_t	CqeCnt:2;
3458 	uint32_t	CqeSize:2;
3459 	uint32_t	Rsvd2:9;
3460 	uint32_t	AutoValid:1;
3461 	uint32_t	NoDelay:1;
3462 	uint32_t	CoalesceWM:2;
3463 	uint32_t	Rsvd1:12;
3464 
3465 	uint32_t	Armed:1;
3466 	uint32_t	Rsvd4:15;
3467 	uint32_t	EQId:16;
3468 
3469 	uint32_t	Rsvd5:16;
3470 	uint32_t	Count1:16;
3471 #endif
3472 #ifdef EMLXS_LITTLE_ENDIAN
3473 	uint32_t	Rsvd1:12;
3474 	uint32_t	CoalesceWM:2;
3475 	uint32_t	NoDelay:1;
3476 	uint32_t	AutoValid:1;
3477 	uint32_t	Rsvd2:9;
3478 	uint32_t	CqeSize:2;
3479 	uint32_t	CqeCnt:2;
3480 	uint32_t	Valid:1;
3481 	uint32_t	Rsvd3:1;
3482 	uint32_t	Eventable:1;
3483 
3484 	uint32_t	EQId:16;
3485 	uint32_t	Rsvd4:15;
3486 	uint32_t	Armed:1;
3487 
3488 	uint32_t	Count1:16;
3489 	uint32_t	Rsvd5:16;
3490 #endif
3491 
3492 	uint32_t	Rsvd7;
3493 
3494 } CQ_CONTEXT_V2;
3495 
3496 /* CqeSize */
3497 #define	CQE_SIZE_16_BYTES	0
3498 #define	CQE_SIZE_32_BYTES	1
3499 
3500 /* define for Count field */
3501 #define	CQ_ELEMENT_COUNT_256	0
3502 #define	CQ_ELEMENT_COUNT_512	1
3503 #define	CQ_ELEMENT_COUNT_1024	2
3504 #define	CQ_ELEMENT_COUNT_SPECIFIED	3
3505 
3506 /*	Context for MQ create	*/
3507 typedef	struct _MQ_CONTEXT
3508 {
3509 #ifdef EMLXS_BIG_ENDIAN
3510 	uint32_t	CQId:10;
3511 	uint32_t	Rsvd2:2;
3512 	uint32_t	Size:4;
3513 	uint32_t	Rsvd1:16;
3514 
3515 	uint32_t	Valid:1;
3516 	uint32_t	Rsvd3:31;
3517 
3518 	uint32_t	Rsvd4:21;
3519 	uint32_t	ACQId:10;
3520 	uint32_t	ACQV:1;
3521 #endif
3522 #ifdef EMLXS_LITTLE_ENDIAN
3523 	uint32_t	Rsvd1:16;
3524 	uint32_t	Size:4;
3525 	uint32_t	Rsvd2:2;
3526 	uint32_t	CQId:10;
3527 
3528 	uint32_t	Rsvd3:31;
3529 	uint32_t	Valid:1;
3530 
3531 	uint32_t	ACQV:1;
3532 	uint32_t	ACQId:10;
3533 	uint32_t	Rsvd4:21;
3534 #endif
3535 
3536 	uint32_t	Rsvd5;
3537 
3538 } MQ_CONTEXT;
3539 
3540 
3541 typedef	struct _MQ_CONTEXT_V1
3542 {
3543 #ifdef EMLXS_BIG_ENDIAN
3544 	uint32_t	Rsvd2:12;
3545 	uint32_t	Size:4;
3546 	uint32_t	ACQId:16;
3547 
3548 	uint32_t	Valid:1;
3549 	uint32_t	Rsvd3:31;
3550 
3551 	uint32_t	Rsvd4:31;
3552 	uint32_t	ACQV:1;
3553 #endif
3554 #ifdef EMLXS_LITTLE_ENDIAN
3555 	uint32_t	ACQId:16;
3556 	uint32_t	Size:4;
3557 	uint32_t	Rsvd2:12;
3558 
3559 	uint32_t	Rsvd3:31;
3560 	uint32_t	Valid:1;
3561 
3562 	uint32_t	ACQV:1;
3563 	uint32_t	Rsvd4:31;
3564 #endif
3565 
3566 	uint32_t	Rsvd5;
3567 
3568 } MQ_CONTEXT_V1;
3569 
3570 
3571 /* define for Size field */
3572 #define	MQ_ELEMENT_COUNT_16 0x05
3573 
3574 /*	Context for RQ create	*/
3575 typedef	struct _RQ_CONTEXT
3576 {
3577 #ifdef EMLXS_BIG_ENDIAN
3578 	uint32_t	Rsvd2:12;
3579 	uint32_t	RqeCnt:4;
3580 	uint32_t	Rsvd1:16;
3581 
3582 	uint32_t	Rsvd3;
3583 
3584 	uint32_t	CQId:16;
3585 	uint32_t	BufferSize:16;
3586 #endif
3587 #ifdef EMLXS_LITTLE_ENDIAN
3588 	uint32_t	Rsvd1:16;
3589 	uint32_t	RqeCnt:4;
3590 	uint32_t	Rsvd2:12;
3591 
3592 	uint32_t	Rsvd3;
3593 
3594 	uint32_t	BufferSize:16;
3595 	uint32_t	CQId:16;
3596 #endif
3597 
3598 	uint32_t  Rsvd5;
3599 
3600 } RQ_CONTEXT;
3601 
3602 typedef	struct _RQ_CONTEXT_V1
3603 {
3604 #ifdef EMLXS_BIG_ENDIAN
3605 	uint32_t	RqeCnt:16;
3606 	uint32_t	Rsvd1:4;
3607 	uint32_t	RqeSize:4;
3608 	uint32_t	PageSize:8;
3609 
3610 	uint32_t	Rsvd2;
3611 
3612 	uint32_t	CQId:16;
3613 	uint32_t	Rsvd:16;
3614 #endif
3615 #ifdef EMLXS_LITTLE_ENDIAN
3616 	uint32_t	PageSize:8;
3617 	uint32_t	RqeSize:4;
3618 	uint32_t	Rsvd1:4;
3619 	uint32_t	RqeCnt:16;
3620 
3621 	uint32_t	Rsvd2;
3622 
3623 	uint32_t	Rsvd:16;
3624 	uint32_t	CQId:16;
3625 #endif
3626 
3627 	uint32_t	BufferSize;
3628 
3629 } RQ_CONTEXT_V1;
3630 
3631 /* RqeSize */
3632 #define	RQE_SIZE_8_BYTES	0x02
3633 #define	RQE_SIZE_16_BYTES	0x03
3634 #define	RQE_SIZE_32_BYTES	0x04
3635 #define	RQE_SIZE_64_BYTES	0x05
3636 #define	RQE_SIZE_128_BYTES	0x06
3637 
3638 /* RQ PageSize */
3639 #define	RQ_PAGE_SIZE_4K		0x01
3640 #define	RQ_PAGE_SIZE_8K		0x02
3641 #define	RQ_PAGE_SIZE_16K	0x04
3642 #define	RQ_PAGE_SIZE_32K	0x08
3643 #define	RQ_PAGE_SIZE_64K	0x10
3644 
3645 
3646 /* IOCTL_COMMON_EQ_CREATE */
3647 typedef	struct
3648 {
3649 	union
3650 	{
3651 		struct
3652 		{
3653 #ifdef EMLXS_BIG_ENDIAN
3654 			uint16_t	Rsvd1;
3655 			uint16_t	NumPages;
3656 #endif
3657 #ifdef EMLXS_LITTLE_ENDIAN
3658 			uint16_t	NumPages;
3659 			uint16_t	Rsvd1;
3660 #endif
3661 			EQ_CONTEXT	EQContext;
3662 			BE_PHYS_ADDR	Pages[8];
3663 		} request;
3664 
3665 		struct
3666 		{
3667 #ifdef EMLXS_BIG_ENDIAN
3668 			uint16_t	MsiIndex; /* V1 only */
3669 			uint16_t	EQId;
3670 #endif
3671 #ifdef EMLXS_LITTLE_ENDIAN
3672 			uint16_t	EQId;
3673 			uint16_t	MsiIndex; /* V1 only */
3674 #endif
3675 		} response;
3676 	} params;
3677 
3678 } IOCTL_COMMON_EQ_CREATE;
3679 
3680 
3681 typedef	struct
3682 {
3683 #ifdef EMLXS_BIG_ENDIAN
3684 		uint32_t	Rsvd1:24;		/* Word 0 */
3685 		uint32_t	ProtocolType:8;
3686 
3687 		uint32_t	Rsvd3:3;		/* Word 1 */
3688 		uint32_t	SliHint2:5;
3689 		uint32_t	SliHint1:8;
3690 		uint32_t	IfType:4;
3691 		uint32_t	SliFamily:4;
3692 		uint32_t	Revision:4;
3693 		uint32_t	Rsvd2:3;
3694 		uint32_t	FT:1;
3695 
3696 		uint32_t	EqRsvd3:4;		/* Word 2 */
3697 		uint32_t	EqeCntMethod:4;
3698 		uint32_t	EqPageSize:8;
3699 		uint32_t	EqRsvd2:4;
3700 		uint32_t	EqeSize:4;
3701 		uint32_t	EqRsvd1:4;
3702 		uint32_t	EqPageCnt:4;
3703 
3704 		uint32_t	EqRsvd4:16;		/* Word 3 */
3705 		uint32_t	EqeCntMask:16;
3706 
3707 		uint32_t	CqRsvd3:4;		/* Word 4 */
3708 		uint32_t	CqeCntMethod:4;
3709 		uint32_t	CqPageSize:8;
3710 		uint32_t	CQV:2;
3711 		uint32_t	CqRsvd2:2;
3712 		uint32_t	CqeSize:4;
3713 		uint32_t	CqRsvd1:4;
3714 		uint32_t	CqPageCnt:4;
3715 
3716 		uint32_t	CqRsvd4:16;		/* Word 5 */
3717 		uint32_t	CqeCntMask:16;
3718 
3719 		uint32_t	MqRsvd2:4;		/* Word 6 */
3720 		uint32_t	MqeCntMethod:4;
3721 		uint32_t	MqPageSize:8;
3722 		uint32_t	MQV:2;
3723 		uint32_t	MqRsvd1:10;
3724 		uint32_t	MqPageCnt:4;
3725 
3726 		uint32_t	MqRsvd3:16;		/* Word 7 */
3727 		uint32_t	MqeCntMask:16;
3728 
3729 		uint32_t	WqRsvd3:4;		/* Word 8 */
3730 		uint32_t	WqeCntMethod:4;
3731 		uint32_t	WqPageSize:8;
3732 		uint32_t	WQV:2;
3733 		uint32_t	WqeRsvd2:2;
3734 		uint32_t	WqeSize:4;
3735 		uint32_t	WqRsvd1:4;
3736 		uint32_t	WqPageCnt:4;
3737 
3738 		uint32_t	WqRsvd4:16;		/* Word 9 */
3739 		uint32_t	WqeCntMask:16;
3740 
3741 		uint32_t	RqRsvd3:4;		/* Word 10 */
3742 		uint32_t	RqeCntMethod:4;
3743 		uint32_t	RqPageSize:8;
3744 		uint32_t	RQV:2;
3745 		uint32_t	RqeRsvd2:2;
3746 		uint32_t	RqeSize:4;
3747 		uint32_t	RqRsvd1:4;
3748 		uint32_t	RqPageCnt:4;
3749 
3750 		uint32_t	RqDbWin:4;		/* Word 11 */
3751 		uint32_t	RqRsvd4:12;
3752 		uint32_t	RqeCntMask:16;
3753 
3754 		uint32_t	Loopback:4;		/* Word 12 */
3755 		uint32_t	Rsvd4:12;
3756 		uint32_t	PHWQ:1;
3757 		uint32_t	PHON:1;
3758 		uint32_t	PHOFF:1;
3759 		uint32_t	TRIR:1;
3760 		uint32_t	TRTY:1;
3761 		uint32_t	TCCA:1;
3762 		uint32_t	MWQE:1;
3763 		uint32_t	ASSI:1;
3764 		uint32_t	TERP:1;
3765 		uint32_t	TGT:1;
3766 		uint32_t	AREG:1;
3767 		uint32_t	FBRR:1;
3768 		uint32_t	SGLR:1;
3769 		uint32_t	HDRR:1;
3770 		uint32_t	EXT:1;
3771 		uint32_t	FCOE:1;
3772 
3773 		uint32_t	SgeLength;		/* Word 13 */
3774 
3775 		uint32_t	SglRsvd2:8;		/* Word 14 */
3776 		uint32_t	SglAlign:8;
3777 		uint32_t	SglPageSize:8;
3778 		uint32_t	SglRsvd1:4;
3779 		uint32_t	SglPageCnt:4;
3780 
3781 		uint32_t	Rsvd5:16;		/* Word 15 */
3782 		uint32_t	MinRqSize:16;
3783 
3784 		uint32_t	MaxRqSize;		/* Word 16 */
3785 
3786 		uint32_t	RPIMax:16;
3787 		uint32_t	XRIMax:16;		/* Word 17 */
3788 
3789 		uint32_t	VFIMax:16;
3790 		uint32_t	VPIMax:16;		/* Word 18 */
3791 #endif
3792 #ifdef EMLXS_LITTLE_ENDIAN
3793 		uint32_t	ProtocolType:8;		/* Word 0 */
3794 		uint32_t	Rsvd1:24;
3795 
3796 		uint32_t	FT:1;			/* Word 1 */
3797 		uint32_t	Rsvd2:3;
3798 		uint32_t	Revision:4;
3799 		uint32_t	SliFamily:4;
3800 		uint32_t	IfType:4;
3801 		uint32_t	SliHint1:8;
3802 		uint32_t	SliHint2:5;
3803 		uint32_t	Rsvd3:3;
3804 
3805 		uint32_t	EqPageCnt:4;		/* Word 2 */
3806 		uint32_t	EqRsvd1:4;
3807 		uint32_t	EqeSize:4;
3808 		uint32_t	EqRsvd2:4;
3809 		uint32_t	EqPageSize:8;
3810 		uint32_t	EqeCntMethod:4;
3811 		uint32_t	EqRsvd3:4;
3812 
3813 		uint32_t	EqeCntMask:16;		/* Word 3 */
3814 		uint32_t	EqRsvd4:16;
3815 
3816 		uint32_t	CqPageCnt:4;		/* Word 4 */
3817 		uint32_t	CqRsvd1:4;
3818 		uint32_t	CqeSize:4;
3819 		uint32_t	CqRsvd2:2;
3820 		uint32_t	CQV:2;
3821 		uint32_t	CqPageSize:8;
3822 		uint32_t	CqeCntMethod:4;
3823 		uint32_t	CqRsvd3:4;
3824 
3825 		uint32_t	CqeCntMask:16;		/* Word 5 */
3826 		uint32_t	CqRsvd4:16;
3827 
3828 		uint32_t	MqPageCnt:4;		/* Word 6 */
3829 		uint32_t	MqRsvd1:10;
3830 		uint32_t	MQV:2;
3831 		uint32_t	MqPageSize:8;
3832 		uint32_t	MqeCntMethod:4;
3833 		uint32_t	MqRsvd2:4;
3834 
3835 		uint32_t	MqeCntMask:16;		/* Word 7 */
3836 		uint32_t	MqRsvd3:16;
3837 
3838 		uint32_t	WqPageCnt:4;		/* Word 8 */
3839 		uint32_t	WqRsvd1:4;
3840 		uint32_t	WqeSize:4;
3841 		uint32_t	WqeRsvd2:2;
3842 		uint32_t	WQV:2;
3843 		uint32_t	WqPageSize:8;
3844 		uint32_t	WqeCntMethod:4;
3845 		uint32_t	WqRsvd3:4;
3846 
3847 		uint32_t	WqeCntMask:16;		/* Word 9 */
3848 		uint32_t	WqRsvd4:16;
3849 
3850 		uint32_t	RqPageCnt:4;		/* Word 10 */
3851 		uint32_t	RqRsvd1:4;
3852 		uint32_t	RqeSize:4;
3853 		uint32_t	RqeRsvd2:2;
3854 		uint32_t	RQV:2;
3855 		uint32_t	RqPageSize:8;
3856 		uint32_t	RqeCntMethod:4;
3857 		uint32_t	RqRsvd3:4;
3858 
3859 		uint32_t	RqeCntMask:16;		/* Word 11 */
3860 		uint32_t	RqRsvd4:12;
3861 		uint32_t	RqDbWin:4;
3862 
3863 		uint32_t	FCOE:1;			/* Word 12 */
3864 		uint32_t	EXT:1;
3865 		uint32_t	HDRR:1;
3866 		uint32_t	SGLR:1;
3867 		uint32_t	FBRR:1;
3868 		uint32_t	AREG:1;
3869 		uint32_t	TGT:1;
3870 		uint32_t	TERP:1;
3871 		uint32_t	ASSI:1;
3872 		uint32_t	MWQE:1;
3873 		uint32_t	TCCA:1;
3874 		uint32_t	TRTY:1;
3875 		uint32_t	TRIR:1;
3876 		uint32_t	PHOFF:1;
3877 		uint32_t	PHON:1;
3878 		uint32_t	PHWQ:1;
3879 		uint32_t	Rsvd4:12;
3880 		uint32_t	Loopback:4;
3881 
3882 		uint32_t	SgeLength;		/* Word 13 */
3883 
3884 		uint32_t	SglPageCnt:4;		/* Word 14 */
3885 		uint32_t	SglRsvd1:4;
3886 		uint32_t	SglPageSize:8;
3887 		uint32_t	SglAlign:8;
3888 		uint32_t	SglRsvd2:8;
3889 
3890 		uint32_t	MinRqSize:16;		/* Word 15 */
3891 		uint32_t	Rsvd5:16;
3892 
3893 		uint32_t	MaxRqSize;		/* Word 16 */
3894 
3895 		uint32_t	XRIMax:16;		/* Word 17 */
3896 		uint32_t	RPIMax:16;
3897 
3898 		uint32_t	VPIMax:16;		/* Word 18 */
3899 		uint32_t	VFIMax:16;
3900 #endif
3901 
3902 		uint32_t	Rsvd6;			/* Word 19 */
3903 
3904 } sli_params_t;
3905 
3906 /* SliFamily values */
3907 #define	SLI_FAMILY_BE2		0x0
3908 #define	SLI_FAMILY_BE3		0x1
3909 #define	SLI_FAMILY_LANCER_A	0xA
3910 #define	SLI_FAMILY_LANCER_B	0xB
3911 
3912 
3913 
3914 /* IOCTL_COMMON_SLI4_PARAMS */
3915 typedef	struct
3916 {
3917 	union
3918 	{
3919 		struct
3920 		{
3921 			uint32_t	Rsvd1;
3922 		} request;
3923 
3924 		struct
3925 		{
3926 			sli_params_t param;
3927 		} response;
3928 	} params;
3929 
3930 } IOCTL_COMMON_SLI4_PARAMS;
3931 
3932 
3933 #define	MAX_EXTENTS		16 /* 1 to 104 */
3934 
3935 /* IOCTL_COMMON_EXTENTS */
3936 typedef	struct
3937 {
3938 	union
3939 	{
3940 		struct
3941 		{
3942 #ifdef EMLXS_BIG_ENDIAN
3943 			uint16_t	RscCnt;
3944 			uint16_t	RscType;
3945 #endif
3946 #ifdef EMLXS_LITTLE_ENDIAN
3947 			uint16_t	RscType;
3948 			uint16_t	RscCnt;
3949 #endif
3950 		} request;
3951 
3952 		struct
3953 		{
3954 #ifdef EMLXS_BIG_ENDIAN
3955 			uint16_t	ExtentSize;
3956 			uint16_t	ExtentCnt;
3957 #endif
3958 #ifdef EMLXS_LITTLE_ENDIAN
3959 			uint16_t	ExtentCnt;
3960 			uint16_t	ExtentSize;
3961 #endif
3962 
3963 			uint16_t	RscId[MAX_EXTENTS];
3964 
3965 		} response;
3966 	} params;
3967 
3968 } IOCTL_COMMON_EXTENTS;
3969 
3970 /* RscType */
3971 #define	RSC_TYPE_FCOE_VFI	0x20
3972 #define	RSC_TYPE_FCOE_VPI	0x21
3973 #define	RSC_TYPE_FCOE_RPI	0x22
3974 #define	RSC_TYPE_FCOE_XRI	0x23
3975 
3976 
3977 
3978 /* IOCTL_COMMON_CQ_CREATE */
3979 typedef	struct
3980 {
3981 	union
3982 	{
3983 		struct
3984 		{
3985 #ifdef EMLXS_BIG_ENDIAN
3986 			uint16_t	Rsvd1;
3987 			uint16_t	NumPages;
3988 #endif
3989 #ifdef EMLXS_LITTLE_ENDIAN
3990 			uint16_t	NumPages;
3991 			uint16_t	Rsvd1;
3992 #endif
3993 			CQ_CONTEXT	CQContext;
3994 			BE_PHYS_ADDR	Pages[4];
3995 		} request;
3996 
3997 		struct
3998 		{
3999 #ifdef EMLXS_BIG_ENDIAN
4000 			uint16_t	Rsvd1;
4001 			uint16_t	CQId;
4002 #endif
4003 #ifdef EMLXS_LITTLE_ENDIAN
4004 			uint16_t	CQId;
4005 			uint16_t	Rsvd1;
4006 #endif
4007 		} response;
4008 	} params;
4009 
4010 } IOCTL_COMMON_CQ_CREATE;
4011 
4012 
4013 /* IOCTL_COMMON_CQ_CREATE_V2 */
4014 typedef	struct
4015 {
4016 	union
4017 	{
4018 		struct
4019 		{
4020 #ifdef EMLXS_BIG_ENDIAN
4021 			uint8_t		Rsvd1;
4022 			uint8_t		PageSize;
4023 			uint16_t	NumPages;
4024 #endif
4025 #ifdef EMLXS_LITTLE_ENDIAN
4026 			uint16_t	NumPages;
4027 			uint8_t		PageSize;
4028 			uint8_t		Rsvd1;
4029 #endif
4030 			CQ_CONTEXT_V2	CQContext;
4031 			BE_PHYS_ADDR	Pages[8];
4032 		} request;
4033 
4034 		struct
4035 		{
4036 #ifdef EMLXS_BIG_ENDIAN
4037 			uint16_t	Rsvd1;
4038 			uint16_t	CQId;
4039 #endif
4040 #ifdef EMLXS_LITTLE_ENDIAN
4041 			uint16_t	CQId;
4042 			uint16_t	Rsvd1;
4043 #endif
4044 		} response;
4045 	} params;
4046 
4047 } IOCTL_COMMON_CQ_CREATE_V2;
4048 
4049 #define	CQ_PAGE_SIZE_4K		0x01
4050 #define	CQ_PAGE_SIZE_8K		0x02
4051 #define	CQ_PAGE_SIZE_16K	0x04
4052 #define	CQ_PAGE_SIZE_32K	0x08
4053 #define	CQ_PAGE_SIZE_64K	0x10
4054 
4055 
4056 
4057 /* IOCTL_COMMON_MQ_CREATE */
4058 typedef	struct
4059 {
4060 	union
4061 	{
4062 		struct
4063 		{
4064 #ifdef EMLXS_BIG_ENDIAN
4065 			uint16_t	Rsvd1;
4066 			uint16_t	NumPages;
4067 #endif
4068 #ifdef EMLXS_LITTLE_ENDIAN
4069 			uint16_t	NumPages;
4070 			uint16_t	Rsvd1;
4071 #endif
4072 			MQ_CONTEXT	MQContext;
4073 			BE_PHYS_ADDR	Pages[8];
4074 		} request;
4075 
4076 		struct
4077 		{
4078 #ifdef EMLXS_BIG_ENDIAN
4079 			uint16_t	Rsvd1;
4080 			uint16_t	MQId;
4081 #endif
4082 #ifdef EMLXS_LITTLE_ENDIAN
4083 			uint16_t	MQId;
4084 			uint16_t	Rsvd1;
4085 #endif
4086 		} response;
4087 	} params;
4088 
4089 } IOCTL_COMMON_MQ_CREATE;
4090 
4091 
4092 /* IOCTL_COMMON_MQ_CREATE_EXT */
4093 typedef	struct
4094 {
4095 	union
4096 	{
4097 		struct
4098 		{
4099 #ifdef EMLXS_BIG_ENDIAN
4100 			uint16_t	rsvd0;
4101 			uint16_t	num_pages;
4102 #endif
4103 #ifdef EMLXS_LITTLE_ENDIAN
4104 			uint16_t	num_pages;
4105 			uint16_t	rsvd0;
4106 #endif
4107 			uint32_t	async_event_bitmap;
4108 
4109 #define	ASYNC_LINK_EVENT	0x00000002
4110 #define	ASYNC_FCF_EVENT		0x00000004
4111 #define	ASYNC_DCBX_EVENT	0x00000008
4112 #define	ASYNC_iSCSI_EVENT	0x00000010
4113 #define	ASYNC_GROUP5_EVENT	0x00000020
4114 #define	ASYNC_FC_EVENT		0x00010000
4115 #define	ASYNC_PORT_EVENT	0x00020000
4116 #define	ASYNC_VF_EVENT		0x00040000
4117 #define	ASYNC_MR_EVENT		0x00080000
4118 
4119 			MQ_CONTEXT	context;
4120 			BE_PHYS_ADDR	pages[8];
4121 		} request;
4122 
4123 		struct
4124 		{
4125 #ifdef EMLXS_BIG_ENDIAN
4126 			uint16_t	rsvd0;
4127 			uint16_t	MQId;
4128 #endif
4129 #ifdef EMLXS_LITTLE_ENDIAN
4130 			uint16_t	MQId;
4131 			uint16_t	rsvd0;
4132 #endif
4133 		} response;
4134 
4135 	} params;
4136 
4137 } IOCTL_COMMON_MQ_CREATE_EXT;
4138 
4139 
4140 /* IOCTL_COMMON_MQ_CREATE_EXT_V1 */
4141 typedef	struct
4142 {
4143 	union
4144 	{
4145 		struct
4146 		{
4147 #ifdef EMLXS_BIG_ENDIAN
4148 			uint16_t	CQId;
4149 			uint16_t	num_pages;
4150 #endif
4151 #ifdef EMLXS_LITTLE_ENDIAN
4152 			uint16_t	num_pages;
4153 			uint16_t	CQId;
4154 #endif
4155 			uint32_t	async_event_bitmap;
4156 
4157 			MQ_CONTEXT_V1	context;
4158 			BE_PHYS_ADDR	pages[8];
4159 		} request;
4160 
4161 		struct
4162 		{
4163 #ifdef EMLXS_BIG_ENDIAN
4164 			uint16_t	rsvd0;
4165 			uint16_t	MQId;
4166 #endif
4167 #ifdef EMLXS_LITTLE_ENDIAN
4168 			uint16_t	MQId;
4169 			uint16_t	rsvd0;
4170 #endif
4171 		} response;
4172 
4173 	} params;
4174 
4175 } IOCTL_COMMON_MQ_CREATE_EXT_V1;
4176 
4177 
4178 /* IOCTL_FCOE_RQ_CREATE */
4179 typedef	struct
4180 {
4181 	union
4182 	{
4183 		struct
4184 		{
4185 #ifdef EMLXS_BIG_ENDIAN
4186 			uint16_t	Rsvd0;
4187 			uint16_t	NumPages;
4188 #endif
4189 #ifdef EMLXS_LITTLE_ENDIAN
4190 			uint16_t	NumPages;
4191 			uint16_t	Rsvd0;
4192 #endif
4193 			RQ_CONTEXT	RQContext;
4194 			BE_PHYS_ADDR	Pages[8];
4195 		} request;
4196 
4197 		struct
4198 		{
4199 #ifdef EMLXS_BIG_ENDIAN
4200 			uint16_t	Rsvd1;
4201 			uint16_t	RQId;
4202 #endif
4203 #ifdef EMLXS_LITTLE_ENDIAN
4204 			uint16_t	RQId;
4205 			uint16_t	Rsvd1;
4206 #endif
4207 		} response;
4208 
4209 	} params;
4210 
4211 } IOCTL_FCOE_RQ_CREATE;
4212 
4213 
4214 /* IOCTL_FCOE_RQ_CREATE_V1 */
4215 typedef	struct
4216 {
4217 	union
4218 	{
4219 		struct
4220 		{
4221 #ifdef EMLXS_BIG_ENDIAN
4222 			uint32_t 	DNB:1;
4223 			uint32_t 	DFD:1;
4224 			uint32_t 	DIM:1;
4225 			uint32_t	Rsvd0:13;
4226 			uint32_t	NumPages:16;
4227 #endif
4228 #ifdef EMLXS_LITTLE_ENDIAN
4229 			uint32_t	NumPages:16;
4230 			uint32_t	Rsvd0:13;
4231 			uint32_t 	DIM:1;
4232 			uint32_t 	DFD:1;
4233 			uint32_t 	DNB:1;
4234 #endif
4235 			RQ_CONTEXT_V1	RQContext;
4236 			BE_PHYS_ADDR	Pages[8];
4237 		} request;
4238 
4239 		struct
4240 		{
4241 #ifdef EMLXS_BIG_ENDIAN
4242 			uint16_t	Rsvd1;
4243 			uint16_t	RQId;
4244 #endif
4245 #ifdef EMLXS_LITTLE_ENDIAN
4246 			uint16_t	RQId;
4247 			uint16_t	Rsvd1;
4248 #endif
4249 		} response;
4250 
4251 	} params;
4252 
4253 } IOCTL_FCOE_RQ_CREATE_V1;
4254 
4255 
4256 /* IOCTL_FCOE_WQ_CREATE */
4257 typedef	struct
4258 {
4259 	union
4260 	{
4261 		struct
4262 		{
4263 #ifdef EMLXS_BIG_ENDIAN
4264 			uint16_t	CQId;
4265 			uint16_t	NumPages;
4266 #endif
4267 #ifdef EMLXS_LITTLE_ENDIAN
4268 			uint16_t	NumPages;
4269 			uint16_t	CQId;
4270 #endif
4271 			BE_PHYS_ADDR	Pages[4];
4272 		} request;
4273 
4274 		struct
4275 		{
4276 #ifdef EMLXS_BIG_ENDIAN
4277 			uint16_t	Rsvd0;
4278 			uint16_t	WQId;
4279 #endif
4280 #ifdef EMLXS_LITTLE_ENDIAN
4281 			uint16_t	WQId;
4282 			uint16_t	Rsvd0;
4283 #endif
4284 		} response;
4285 
4286 	} params;
4287 
4288 } IOCTL_FCOE_WQ_CREATE;
4289 
4290 
4291 /* IOCTL_FCOE_WQ_CREATE_V1 */
4292 typedef	struct
4293 {
4294 	union
4295 	{
4296 		struct
4297 		{
4298 #ifdef EMLXS_BIG_ENDIAN
4299 			uint16_t	CQId;
4300 			uint16_t	NumPages;
4301 
4302 			uint32_t	WqeCnt:16;
4303 			uint32_t	Rsvd1:4;
4304 			uint32_t	WqeSize:4;
4305 			uint32_t	PageSize:8;
4306 #endif
4307 #ifdef EMLXS_LITTLE_ENDIAN
4308 			uint16_t	NumPages;
4309 			uint16_t	CQId;
4310 
4311 			uint32_t	PageSize:8;
4312 			uint32_t	WqeSize:4;
4313 			uint32_t	Rsvd1:4;
4314 			uint32_t	WqeCnt:16;
4315 #endif
4316 			uint32_t	Rsvd:2;
4317 			BE_PHYS_ADDR	Pages[4];
4318 		} request;
4319 
4320 		struct
4321 		{
4322 #ifdef EMLXS_BIG_ENDIAN
4323 			uint16_t	Rsvd0;
4324 			uint16_t	WQId;
4325 #endif
4326 #ifdef EMLXS_LITTLE_ENDIAN
4327 			uint16_t	WQId;
4328 			uint16_t	Rsvd0;
4329 #endif
4330 		} response;
4331 
4332 	} params;
4333 
4334 } IOCTL_FCOE_WQ_CREATE_V1;
4335 
4336 /* WqeSize */
4337 #define	WQE_SIZE_64_BYTES	0x05
4338 #define	WQE_SIZE_128_BYTES	0x06
4339 
4340 /* PageSize */
4341 #define	WQ_PAGE_SIZE_4K		0x01
4342 #define	WQ_PAGE_SIZE_8K		0x02
4343 #define	WQ_PAGE_SIZE_16K	0x04
4344 #define	WQ_PAGE_SIZE_32K	0x08
4345 #define	WQ_PAGE_SIZE_64K	0x10
4346 
4347 
4348 
4349 /* IOCTL_FCOE_CFG_POST_SGL_PAGES */
4350 typedef	struct _FCOE_SGL_PAGES
4351 {
4352 	BE_PHYS_ADDR	sgl_page0;	/* 1st page per XRI */
4353 	BE_PHYS_ADDR	sgl_page1;	/* 2nd page per XRI */
4354 
4355 } FCOE_SGL_PAGES;
4356 
4357 typedef	struct
4358 {
4359 	union
4360 	{
4361 		struct
4362 		{
4363 #ifdef EMLXS_BIG_ENDIAN
4364 			uint16_t	xri_count;
4365 			uint16_t	xri_start;
4366 #endif
4367 #ifdef EMLXS_LITTLE_ENDIAN
4368 			uint16_t	xri_start;
4369 			uint16_t	xri_count;
4370 #endif
4371 			FCOE_SGL_PAGES	pages[1];
4372 		} request;
4373 
4374 		struct
4375 		{
4376 			uint32_t	rsvd0;
4377 		} response;
4378 
4379 	} params;
4380 
4381 	uint32_t	rsvd0[2];
4382 
4383 } IOCTL_FCOE_CFG_POST_SGL_PAGES;
4384 
4385 
4386 /* IOCTL_FCOE_POST_HDR_TEMPLATES */
4387 typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
4388 {
4389 	union
4390 	{
4391 		struct
4392 		{
4393 #ifdef EMLXS_BIG_ENDIAN
4394 			uint16_t	num_pages;
4395 			uint16_t	rpi_offset;
4396 #endif
4397 #ifdef EMLXS_LITTLE_ENDIAN
4398 			uint16_t	rpi_offset;
4399 			uint16_t	num_pages;
4400 #endif
4401 			BE_PHYS_ADDR	pages[32];
4402 
4403 		}request;
4404 
4405 	}params;
4406 
4407 } IOCTL_FCOE_POST_HDR_TEMPLATES;
4408 
4409 
4410 
4411 #define	EMLXS_IOCTL_DCBX_MODE_CEE	0	/* Mapped to FIP mode */
4412 #define	EMLXS_IOCTL_DCBX_MODE_CIN	1	/* Mapped to nonFIP mode */
4413 
4414 /* IOCTL_DCBX_GET_DCBX_MODE */
4415 typedef struct _IOCTL_DCBX_GET_DCBX_MODE
4416 {
4417 	union
4418 	{
4419 		struct
4420 		{
4421 #ifdef EMLXS_BIG_ENDIAN
4422 			uint8_t		rsvd0[3];
4423 			uint8_t		port_num;
4424 #endif
4425 #ifdef EMLXS_LITTLE_ENDIAN
4426 			uint8_t		port_num;
4427 			uint8_t		rsvd0[3];
4428 #endif
4429 		} request;
4430 
4431 		struct
4432 		{
4433 #ifdef EMLXS_BIG_ENDIAN
4434 			uint8_t		rsvd1[3];
4435 			uint8_t		dcbx_mode;
4436 #endif
4437 #ifdef EMLXS_LITTLE_ENDIAN
4438 			uint8_t		dcbx_mode;
4439 			uint8_t		rsvd1[3];
4440 #endif
4441 		} response;
4442 
4443 	} params;
4444 
4445 } IOCTL_DCBX_GET_DCBX_MODE;
4446 
4447 
4448 /* IOCTL_DCBX_SET_DCBX_MODE */
4449 typedef struct _IOCTL_DCBX_SET_DCBX_MODE
4450 {
4451 	union
4452 	{
4453 		struct
4454 		{
4455 #ifdef EMLXS_BIG_ENDIAN
4456 			uint8_t		rsvd0[2];
4457 			uint8_t		dcbx_mode;
4458 			uint8_t		port_num;
4459 #endif
4460 #ifdef EMLXS_LITTLE_ENDIAN
4461 			uint8_t		port_num;
4462 			uint8_t		dcbx_mode;
4463 			uint8_t		rsvd0[2];
4464 #endif
4465 		} request;
4466 
4467 		struct
4468 		{
4469 			uint32_t	rsvd1;
4470 		} response;
4471 
4472 	} params;
4473 
4474 } IOCTL_DCBX_SET_DCBX_MODE;
4475 
4476 
4477 /* IOCTL_COMMON_GET_CNTL_ATTRIB */
4478 typedef	struct
4479 {
4480 	char		flashrom_version_string[32];
4481 	char		manufacturer_name[32];
4482 	char		rsvd0[28];
4483 	uint32_t	default_extended_timeout;
4484 	char		controller_model_number[32];
4485 	char		controller_description[64];
4486 	char		controller_serial_number[32];
4487 	char		ip_version_string[32];
4488 	char		firmware_version_string[32];
4489 	char		bios_version_string[32];
4490 	char		redboot_version_string[32];
4491 	char		driver_version_string[32];
4492 	char		fw_on_flash_version_string[32];
4493 	uint32_t	functionalities_supported;
4494 	uint16_t	max_cdblength;
4495 	uint8_t		asic_revision;
4496 	uint8_t		generational_guid[16];
4497 	uint8_t		hba_port_count;
4498 	uint16_t	default_link_down_timeout;
4499 	uint8_t		iscsi_ver_min_max;
4500 	uint8_t		multifunction_device;
4501 	uint8_t		cache_valid;
4502 	uint8_t		hba_status;
4503 	uint8_t		max_domains_supported;
4504 	uint8_t		phy_port;
4505 	uint32_t	firmware_post_status;
4506 	uint32_t	hba_mtu[2];
4507 
4508 } MGMT_HBA_ATTRIB;
4509 
4510 typedef	struct
4511 {
4512 	MGMT_HBA_ATTRIB		hba_attribs;
4513 	uint16_t		pci_vendor_id;
4514 	uint16_t		pci_device_id;
4515 	uint16_t		pci_sub_vendor_id;
4516 	uint16_t		pci_sub_system_id;
4517 	uint8_t			pci_bus_number;
4518 	uint8_t			pci_device_number;
4519 	uint8_t			pci_function_number;
4520 	uint8_t			interface_type;
4521 	uint64_t		unique_identifier;
4522 
4523 } MGMT_CONTROLLER_ATTRIB;
4524 
4525 typedef	struct
4526 {
4527 	union
4528 	{
4529 		struct
4530 		{
4531 			uint32_t rsvd0;
4532 		} request;
4533 
4534 		struct
4535 		{
4536 			MGMT_CONTROLLER_ATTRIB cntl_attributes_info;
4537 		} response;
4538 
4539 	} params;
4540 
4541 } IOCTL_COMMON_GET_CNTL_ATTRIB;
4542 
4543 
4544 typedef	union
4545 {
4546 	IOCTL_COMMON_NOP		NOPVar;
4547 	IOCTL_FCOE_WQ_CREATE		WQCreateVar;
4548 	IOCTL_FCOE_WQ_CREATE_V1		WQCreateVar1;
4549 	IOCTL_FCOE_RQ_CREATE		RQCreateVar;
4550 	IOCTL_FCOE_RQ_CREATE_V1		RQCreateVar1;
4551 	IOCTL_COMMON_EQ_CREATE		EQCreateVar;
4552 	IOCTL_COMMON_CQ_CREATE		CQCreateVar;
4553 	IOCTL_COMMON_CQ_CREATE_V2	CQCreateVar2;
4554 	IOCTL_COMMON_MQ_CREATE		MQCreateVar;
4555 	IOCTL_COMMON_MQ_CREATE_EXT	MQCreateExtVar;
4556 	IOCTL_COMMON_MQ_CREATE_EXT_V1	MQCreateExtVar1;
4557 	IOCTL_FCOE_CFG_POST_SGL_PAGES	PostSGLVar;
4558 	IOCTL_COMMON_GET_CNTL_ATTRIB	GetCntlAttributesVar;
4559 	IOCTL_FCOE_READ_FCF_TABLE	ReadFCFTableVar;
4560 	IOCTL_FCOE_ADD_FCF_TABLE	AddFCFTableVar;
4561 	IOCTL_FCOE_REDISCOVER_FCF_TABLE	RediscoverFCFTableVar;
4562 	IOCTL_COMMON_FLASHROM		FlashRomVar;
4563 	IOCTL_COMMON_MANAGE_FAT		FATVar;
4564 	IOCTL_DCBX_GET_DCBX_MODE	GetDCBX;
4565 	IOCTL_DCBX_SET_DCBX_MODE	SetDCBX;
4566 	IOCTL_COMMON_SLI4_PARAMS	Sli4ParamVar;
4567 	IOCTL_COMMON_EXTENTS		ExtentsVar;
4568 	IOCTL_COMMON_GET_PHY_DETAILS	PHYDetailsVar;
4569 	IOCTL_COMMON_GET_PORT_NAME	PortNameVar;
4570 	IOCTL_COMMON_GET_PORT_NAME_V1	PortNameVar1;
4571 	IOCTL_COMMON_WRITE_OBJECT	WriteObjVar;
4572 	IOCTL_COMMON_BOOT_CFG		BootCfgVar;
4573 
4574 } IOCTL_VARIANTS;
4575 
4576 /* Structure for MB Command SLI_CONFIG(0x9b) */
4577 /* Good for SLI4 only */
4578 
4579 typedef struct
4580 {
4581 	be_req_hdr_t	be;
4582 	BE_PHYS_ADDR	payload;
4583 } SLI_CONFIG_VAR;
4584 
4585 #define	IOCTL_HEADER_SZ	(4 * sizeof (uint32_t))
4586 
4587 
4588 typedef union
4589 {
4590 	uint32_t		varWords[63];
4591 	READ_NV_VAR		varRDnvp;	/* cmd = x02 (READ_NVPARMS) */
4592 	INIT_LINK_VAR		varInitLnk;	/* cmd = x05 (INIT_LINK) */
4593 	CONFIG_LINK		varCfgLnk;	/* cmd = x07 (CONFIG_LINK) */
4594 	READ_REV4_VAR		varRdRev4;	/* cmd = x11 (READ_REV) */
4595 	READ_LNK_VAR		varRdLnk;	/* cmd = x12 (READ_LNK_STAT) */
4596 	DUMP4_VAR		varDmp4;	/* cmd = x17 (DUMP) */
4597 	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = x1b (update Cfg) */
4598 	BIU_DIAG_VAR		varBIUdiag;	/* cmd = x84 (RUN_BIU_DIAG64) */
4599 	READ_SPARM_VAR		varRdSparm;	/* cmd = x8D (READ_SPARM64) */
4600 	REG_FCFI_VAR		varRegFCFI;	/* cmd = xA0 (REG_FCFI) */
4601 	UNREG_FCFI_VAR		varUnRegFCFI;	/* cmd = xA2 (UNREG_FCFI) */
4602 	READ_LA_VAR		varReadLA;	/* cmd = x95 (READ_LA64) */
4603 	READ_CONFIG4_VAR	varRdConfig4;	/* cmd = x0B (READ_CONFIG) */
4604 	RESUME_RPI_VAR		varResumeRPI;	/* cmd = x9E (RESUME_RPI) */
4605 	REG_LOGIN_VAR		varRegLogin;	/* cmd = x93 (REG_RPI) */
4606 	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = x14 (UNREG_RPI) */
4607 	REG_VPI_VAR		varRegVPI4;	/* cmd = x96 (REG_VPI) */
4608 	UNREG_VPI_VAR4		varUnRegVPI4;	/* cmd = x97 (UNREG_VPI) */
4609 	REG_VFI_VAR		varRegVFI4;	/* cmd = x9F (REG_VFI) */
4610 	UNREG_VFI_VAR		varUnRegVFI4;	/* cmd = xA1 (UNREG_VFI) */
4611 	REQUEST_FEATURES_VAR	varReqFeatures;	/* cmd = x9D (REQ_FEATURES) */
4612 	SLI_CONFIG_VAR		varSLIConfig;	/* cmd = x9B (SLI_CONFIG) */
4613 	INIT_VPI_VAR		varInitVPI4;	/* cmd = xA3 (INIT_VPI) */
4614 	INIT_VFI_VAR		varInitVFI4;	/* cmd = xA4 (INIT_VFI) */
4615 
4616 } MAILVARIANTS4;		/* Used for SLI-4 */
4617 
4618 #define	MAILBOX_CMD_SLI4_BSIZE	256
4619 #define	MAILBOX_CMD_SLI4_WSIZE	64
4620 
4621 #define	MAILBOX_CMD_MAX_BSIZE	256
4622 #define	MAILBOX_CMD_MAX_WSIZE	64
4623 
4624 
4625 typedef volatile struct
4626 {
4627 #ifdef EMLXS_BIG_ENDIAN
4628 	uint16_t	mbxStatus;
4629 	uint8_t		mbxCommand;
4630 	uint8_t		mbxReserved:6;
4631 	uint8_t		mbxHc:1;
4632 	uint8_t		mbxOwner:1;	/* Low order bit first word */
4633 #endif
4634 #ifdef EMLXS_LITTLE_ENDIAN
4635 	uint8_t		mbxOwner:1;	/* Low order bit first word */
4636 	uint8_t		mbxHc:1;
4637 	uint8_t		mbxReserved:6;
4638 	uint8_t		mbxCommand;
4639 	uint16_t	mbxStatus;
4640 #endif
4641 	MAILVARIANTS4	un;		/* 252 bytes */
4642 } MAILBOX4;				/* Used for SLI-4 */
4643 
4644 /*
4645  * End Structure Definitions for Mailbox Commands
4646  */
4647 
4648 
4649 typedef struct emlxs_mbq
4650 {
4651 	volatile uint32_t	mbox[MAILBOX_CMD_MAX_WSIZE];
4652 	struct emlxs_mbq	*next;
4653 
4654 	/* Defferred handling pointers */
4655 	void			*nonembed;	/* ptr to data buffer */
4656 						/* structure */
4657 	void			*bp;		/* ptr to data buffer */
4658 						/* structure */
4659 	void			*sbp;		/* ptr to emlxs_buf_t */
4660 						/* structure */
4661 	void			*ubp;		/* ptr to fc_unsol_buf_t */
4662 						/* structure */
4663 	void			*iocbq;		/* ptr to IOCBQ structure */
4664 	void			*context;	/* ptr to mbox context data */
4665 	void			*port;		/* Sending port */
4666 	uint32_t		flag;
4667 
4668 #define	MBQ_POOL_ALLOCATED	0x00000001
4669 #define	MBQ_PASSTHRU		0x00000002
4670 #define	MBQ_EMBEDDED		0x00000004
4671 #define	MBQ_BOOTSTRAP		0x00000008
4672 #define	MBQ_COMPLETED		0x00010000	/* Used for MBX_SLEEP */
4673 #define	MBQ_INIT_MASK		0x0000ffff
4674 
4675 #ifdef MBOX_EXT_SUPPORT
4676 	uint8_t			*extbuf;	/* ptr to mailbox ext buffer */
4677 	uint32_t		extsize;	/* size of mailbox ext buffer */
4678 #endif /* MBOX_EXT_SUPPORT */
4679 	uint32_t		(*mbox_cmpl)();
4680 } emlxs_mbq_t;
4681 typedef emlxs_mbq_t MAILBOXQ;
4682 
4683 
4684 /* We currently do not support IOCBs in SLI1 mode */
4685 typedef struct
4686 {
4687 	MAILBOX		mbx;
4688 #ifdef MBOX_EXT_SUPPORT
4689 	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
4690 #endif /* MBOX_EXT_SUPPORT */
4691 	uint8_t		pad[(SLI_SLIM1_SIZE -
4692 				(sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
4693 } SLIM1;
4694 
4695 
4696 typedef struct
4697 {
4698 	MAILBOX		mbx;
4699 #ifdef MBOX_EXT_SUPPORT
4700 	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
4701 #endif /* MBOX_EXT_SUPPORT */
4702 	PCB		pcb;
4703 	uint8_t		IOCBs[SLI_IOCB_MAX_SIZE];
4704 } SLIM2;
4705 
4706 
4707 /* def for new 2MB Flash (Pegasus ...) */
4708 #define	MBX_LOAD_AREA		0x81
4709 #define	MBX_LOAD_EXP_ROM	0x9C
4710 
4711 #define	FILE_TYPE_AWC		0xE1A01001
4712 #define	FILE_TYPE_DWC		0xE1A02002
4713 #define	FILE_TYPE_BWC		0xE1A03003
4714 
4715 #define	AREA_ID_MASK		0xFFFFFF0F
4716 #define	AREA_ID_AWC		0x00000001
4717 #define	AREA_ID_DWC		0x00000002
4718 #define	AREA_ID_BWC		0x00000003
4719 
4720 #define	CMD_START_ERASE		1
4721 #define	CMD_CONTINUE_ERASE	2
4722 #define	CMD_DOWNLOAD		3
4723 #define	CMD_END_DOWNLOAD	4
4724 
4725 #define	RSP_ERASE_STARTED	1
4726 #define	RSP_ERASE_COMPLETE	2
4727 #define	RSP_DOWNLOAD_MORE	3
4728 #define	RSP_DOWNLOAD_DONE	4
4729 
4730 #define	EROM_CMD_FIND_IMAGE	8
4731 #define	EROM_CMD_CONTINUE_ERASE	9
4732 #define	EROM_CMD_COPY		10
4733 
4734 #define	EROM_RSP_ERASE_STARTED	8
4735 #define	EROM_RSP_ERASE_COMPLETE	9
4736 #define	EROM_RSP_COPY_MORE	10
4737 #define	EROM_RSP_COPY_DONE	11
4738 
4739 #define	ALLext			1
4740 #define	DWCext			2
4741 #define	BWCext			3
4742 
4743 #define	NO_ALL			0
4744 #define	ALL_WITHOUT_BWC		1
4745 #define	ALL_WITH_BWC		2
4746 
4747 #define	KERNEL_START_ADDRESS	0x000000
4748 #define	DOWNLOAD_START_ADDRESS	0x040000
4749 #define	EXP_ROM_START_ADDRESS	0x180000
4750 #define	SCRATCH_START_ADDRESS	0x1C0000
4751 #define	CONFIG_START_ADDRESS	0x1E0000
4752 
4753 
4754 typedef struct SliAifHdr
4755 {
4756 	uint32_t	CompressBr;
4757 	uint32_t	RelocBr;
4758 	uint32_t	ZinitBr;
4759 	uint32_t	EntryBr;
4760 	uint32_t	Area_ID;
4761 	uint32_t	RoSize;
4762 	uint32_t	RwSize;
4763 	uint32_t	DbgSize;
4764 	uint32_t	ZinitSize;
4765 	uint32_t	DbgType;
4766 	uint32_t	ImageBase;
4767 	uint32_t	Area_Size;
4768 	uint32_t	AddressMode;
4769 	uint32_t	DataBase;
4770 	uint32_t	AVersion;
4771 	uint32_t	Spare2;
4772 	uint32_t	DebugSwi;
4773 	uint32_t	ZinitCode[15];
4774 } AIF_HDR, *PAIF_HDR;
4775 
4776 typedef struct ImageHdr
4777 {
4778 	uint32_t	BlockSize;
4779 	PROG_ID		Id;
4780 	uint32_t	Flags;
4781 	uint32_t	EntryAdr;
4782 	uint32_t	InitAdr;
4783 	uint32_t	ExitAdr;
4784 	uint32_t	ImageBase;
4785 	uint32_t	ImageSize;
4786 	uint32_t	ZinitSize;
4787 	uint32_t	RelocSize;
4788 	uint32_t	HdrCks;
4789 } IMAGE_HDR, *PIMAGE_HDR;
4790 
4791 
4792 
4793 typedef struct
4794 {
4795 	PROG_ID		prog_id;
4796 #ifdef EMLXS_BIG_ENDIAN
4797 	uint32_t	pci_cfg_rsvd:27;
4798 	uint32_t	use_hdw_def:1;
4799 	uint32_t	pci_cfg_sel:3;
4800 	uint32_t	pci_cfg_lookup_sel:1;
4801 #endif
4802 #ifdef EMLXS_LITTLE_ENDIAN
4803 	uint32_t	pci_cfg_lookup_sel:1;
4804 	uint32_t	pci_cfg_sel:3;
4805 	uint32_t	use_hdw_def:1;
4806 	uint32_t	pci_cfg_rsvd:27;
4807 #endif
4808 	union
4809 	{
4810 		PROG_ID		boot_bios_id;
4811 		uint32_t	boot_bios_wd[2];
4812 	} u0;
4813 	PROG_ID		sli1_prog_id;
4814 	PROG_ID		sli2_prog_id;
4815 	PROG_ID		sli3_prog_id;
4816 	PROG_ID		sli4_prog_id;
4817 	union
4818 	{
4819 		PROG_ID		EROM_prog_id;
4820 		uint32_t	EROM_prog_wd[2];
4821 	} u1;
4822 } WAKE_UP_PARMS, *PWAKE_UP_PARMS;
4823 
4824 
4825 #define	PROG_DESCR_STR_LEN	24
4826 #define	MAX_LOAD_ENTRY		32
4827 
4828 typedef struct
4829 {
4830 	uint32_t	next;
4831 	uint32_t	prev;
4832 	uint32_t	start_adr;
4833 	uint32_t	len;
4834 	union
4835 	{
4836 		PROG_ID		id;
4837 		uint32_t	wd[2];
4838 	} un;
4839 	uint8_t		prog_descr[PROG_DESCR_STR_LEN];
4840 } LOAD_ENTRY;
4841 
4842 typedef struct
4843 {
4844 	uint32_t	head;
4845 	uint32_t	tail;
4846 	uint32_t	entry_cnt;
4847 	LOAD_ENTRY	load_entry[MAX_LOAD_ENTRY];
4848 } LOAD_LIST;
4849 
4850 #ifdef	__cplusplus
4851 }
4852 #endif
4853 
4854 #endif	/* _EMLXS_MBOX_H */
4855