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Searched refs:PEX_ERR_PIN_MASK_WR (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/intel/io/intel_nb5000/
H A Dnb5000_init.c934 PEX_ERR_PIN_MASK_WR(i, 0x10); in nb_pex_init()
H A Dnb5000.h1338 #define PEX_ERR_PIN_MASK_WR(pex, val) nb_pci_putw(0, pex, 0, 0x146, val) macro