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Searched refs:PCI_REG_REG_G (Results 1 – 11 of 11) sorted by relevance

/titanic_41/usr/src/uts/common/io/scsi/adapters/smrt/
H A Dsmrt_device.c76 unsigned bar = PCI_REG_REG_G(regs[i].pci_phys_hi); in smrt_locate_cfgtbl()
/titanic_41/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c1386 offset = PCI_REG_REG_G(phys_spec.pci_phys_hi); in pci_alloc_resource()
1390 if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) { in pci_alloc_resource()
1608 offset = PCI_REG_REG_G(phys_spec.pci_phys_hi); in pci_free_resource()
1618 if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) { in pci_free_resource()
/titanic_41/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c973 if (PCI_REG_REG_G(prp->pci_phys_hi) == er[0].ebus_phys_hi) { in acebus_update_props()
997 if (PCI_REG_REG_G(prp->pci_phys_hi) == er[1].ebus_phys_hi) { in acebus_update_props()
/titanic_41/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c892 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in cardbus_bridge_assign()
2103 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); in cardbus_sum_resources()
2121 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); in cardbus_sum_resources()
2135 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); in cardbus_sum_resources()
2287 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in cardbus_free_device_resources()
2298 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in cardbus_free_device_resources()
2308 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in cardbus_free_device_resources()
/titanic_41/usr/src/uts/sun4/io/
H A Dpcicfg.c1514 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1520 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1984 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_bridge_assign()
2129 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_device_assign()
2940 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) > PCI_CONF_BASE5) && in pcicfg_free_device_resources()
2941 (PCI_REG_REG_G(assigned[i].pci_phys_hi) != PCI_CONF_ROM)) in pcicfg_free_device_resources()
6412 offset = PCI_REG_REG_G(phys_spec.pci_phys_hi); in pcicfg_alloc_resource()
6416 if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) { in pcicfg_alloc_resource()
6583 offset = PCI_REG_REG_G(phys_spec.pci_phys_hi); in pcicfg_free_resource()
6592 if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) { in pcicfg_free_resource()
/titanic_41/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1415 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1420 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1425 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1880 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_bridge_assign()
2039 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_device_assign()
2737 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in pcicfg_free_device_resources()
2762 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in pcicfg_free_device_resources()
2779 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in pcicfg_free_device_resources()
/titanic_41/usr/src/uts/common/io/
H A Dpci_intr_lib.c842 offset = PCI_REG_REG_G(rp->pci_phys_hi); in pci_msix_init()
891 offset = PCI_REG_REG_G(rp->pci_phys_hi); in pci_msix_init()
/titanic_41/usr/src/uts/common/sys/
H A Dpci.h1175 #define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M) macro
/titanic_41/usr/src/uts/common/io/ib/adapters/hermon/
H A Dhermon.c4689 offset = PCI_REG_REG_G(rp->pci_phys_hi); in hermon_set_msix_info()
4732 offset = PCI_REG_REG_G(rp->pci_phys_hi); in hermon_set_msix_info()
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Ddb21554.c1020 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in db_enable_io()
/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000g_main.c1198 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { in e1000g_get_bar_info()