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Searched refs:PCI_CONF_BASE5 (Results 1 – 17 of 17) sorted by relevance

/titanic_41/usr/src/uts/sun4u/sys/pci/
H A Ddb21554_config.h54 #define DB_PCONF_DS_UMEM3 PCI_CONF_BASE5
68 #define DB_SCONF_DS_UMEM3 DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE5
/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_tools.c62 PCI_CONF_BASE5,
577 if (cfg_prg.offset >= PCI_CONF_BASE5) { in pxtool_get_bar()
/titanic_41/usr/src/uts/common/io/igb/
H A Digb_debug.c115 pci_config_get32(handle, PCI_CONF_BASE5)); in pci_dump()
/titanic_41/usr/src/uts/common/os/
H A Dsunpci.c524 chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
878 pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
900 (void) pci_config_get32(confhdl, PCI_CONF_BASE5);
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpci_tools.c95 PCI_CONF_BASE5,
786 if (bar_offset >= PCI_CONF_BASE5) { in pcitool_get_bar()
H A Ddb21554.c1638 ph->bar5 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE5); in db_pci_get_header()
/titanic_41/usr/src/uts/i86pc/io/pci/
H A Dpci_tools.c73 PCI_CONF_BASE5,
1103 if (prg2.offset >= PCI_CONF_BASE5) { in pcitool_dev_reg_ops()
/titanic_41/usr/src/uts/common/sys/
H A Dpci.h58 #define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */ macro
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c242 pci_config_get32(handle, PCI_CONF_BASE5)); in ixgbe_pci_dump()
/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000g_debug.c423 pciconfig_bar(Adapter, PCI_CONF_BASE5, "PCI_CONF_BASE5"); in pciconfig_dump()
H A De1000g_main.c728 offset <= PCI_CONF_BASE5; offset += 4) { in e1000g_regs_map()
1182 (bar_offset <= PCI_CONF_BASE5)); in e1000g_get_bar_info()
/titanic_41/usr/src/uts/sun4/io/
H A Dpcicfg.c468 pci_config_get32(config_handle, PCI_CONF_BASE5)); in pcicfg_dump_device_config()
2940 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) > PCI_CONF_BASE5) && in pcicfg_free_device_resources()
4204 while (i <= PCI_CONF_BASE5) { in pcicfg_populate_reg_props()
4792 while (i <= PCI_CONF_BASE5) { in pcicfg_populate_props_from_bar()
6021 for (i = PCI_CONF_BASE0; i <= PCI_CONF_BASE5; ) { in pcicfg_fcode_assign_bars()
/titanic_41/usr/src/cmd/pcitool/
H A Dpcitool.c280 { PCI_CONF_BASE5, 4, "BAR5", "Base Address Register 5 (@24)" },
/titanic_41/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c439 pci_config_get32(config_handle, PCI_CONF_BASE5)); in pcicfg_dump_device_config()
3858 while (i <= PCI_CONF_BASE5) { in pcicfg_populate_reg_props()
3940 while (i <= PCI_CONF_BASE5) { in pcicfg_populate_props_from_bar()
/titanic_41/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c2962 while (i <= PCI_CONF_BASE5) { in cardbus_probe_children()
4370 pci_config_get32(config_handle, PCI_CONF_BASE5));
/titanic_41/usr/src/uts/common/io/scsi/adapters/pmcs/
H A Dpmcs_fwlog.c761 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE5)); in pmcs_dump_pcie_conf()
/titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_api.c15227 chs.chs_base5 = ql_pci_config_get32(ha, PCI_CONF_BASE5); in ql_save_config_regs()
15292 ql_pci_config_put32(ha, PCI_CONF_BASE5, chs_p->chs_base5); in ql_restore_config_regs()