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Searched refs:PCI_CONF_BASE2 (Results 1 – 18 of 18) sorted by relevance

/titanic_41/usr/src/uts/sun4u/sys/pci/
H A Ddb21554_config.h51 #define DB_PCONF_DS_IO_MEM1 PCI_CONF_BASE2
56 #define DB_PCONF_US_IO_MEM0 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE2
62 #define DB_SCONF_US_IO_MEM0 PCI_CONF_BASE2
65 #define DB_SCONF_DS_IO_MEM1 DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE2
/titanic_41/usr/src/uts/common/io/igb/
H A Digb_debug.c103 pci_config_get32(handle, PCI_CONF_BASE2)); in pci_dump()
/titanic_41/usr/src/uts/common/sys/
H A Dpci.h55 #define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */ macro
/titanic_41/usr/src/uts/common/os/
H A Dsunpci.c521 chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
875 pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c230 pci_config_get32(handle, PCI_CONF_BASE2)); in ixgbe_pci_dump()
/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000g_debug.c420 pciconfig_bar(Adapter, PCI_CONF_BASE2, "PCI_CONF_BASE2"); in pciconfig_dump()
/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_tools.c59 PCI_CONF_BASE2,
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpci_tools.c92 PCI_CONF_BASE2,
H A Ddb21554.c1052 (off_t)(p_offset + PCI_CONF_BASE2))) & ~DB_IO_BIT)); in db_enable_io()
1064 (off_t)(s_offset + PCI_CONF_BASE2))) & ~DB_IO_BIT)); in db_enable_io()
1635 ph->bar2 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE2); in db_pci_get_header()
/titanic_41/usr/src/uts/i86pc/io/pci/
H A Dpci_tools.c70 PCI_CONF_BASE2,
/titanic_41/usr/src/uts/common/io/audio/drv/audiosolo/
H A Daudiosolo.c1210 data = pci_config_get32(dev->pcih, PCI_CONF_BASE2); in solo_init_hw()
/titanic_41/usr/src/cmd/pcitool/
H A Dpcitool.c277 { PCI_CONF_BASE2, 4, "BAR2", "Base Address Register 2 (@18)" },
/titanic_41/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c163 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,
433 pci_config_get32(config_handle, PCI_CONF_BASE2)); in pcicfg_dump_device_config()
/titanic_41/usr/src/uts/common/io/scsi/adapters/pmcs/
H A Dpmcs_fwlog.c755 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE2)); in pmcs_dump_pcie_conf()
/titanic_41/usr/src/uts/sun4/io/
H A Dpcicfg.c203 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,
462 pci_config_get32(config_handle, PCI_CONF_BASE2)); in pcicfg_dump_device_config()
/titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_dbg.c670 pci_config_get32(qlge->pci_handle, PCI_CONF_BASE2); in ql_dump_pci_config()
/titanic_41/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c4365 pci_config_get32(config_handle, PCI_CONF_BASE2),
/titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_api.c15224 chs.chs_base2 = ql_pci_config_get32(ha, PCI_CONF_BASE2); in ql_save_config_regs()
15289 ql_pci_config_put32(ha, PCI_CONF_BASE2, chs_p->chs_base2); in ql_restore_config_regs()