| /titanic_41/usr/src/uts/sun4u/sys/pci/ |
| H A D | db21554_config.h | 49 #define DB_PCONF_MEM_CSR PCI_CONF_BASE0
60 #define DB_SCONF_MEM_CSR PCI_CONF_BASE0
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| /titanic_41/usr/src/uts/common/io/igb/ |
| H A D | igb_debug.c | 97 pci_config_get32(handle, PCI_CONF_BASE0)); in pci_dump()
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| /titanic_41/usr/src/uts/common/io/cardbus/ |
| H A D | cardbus_cfg.c | 2722 PCI_CONF_BASE0, 0xffffffff); in cardbus_probe_children()
2725 PCI_CONF_BASE0); in cardbus_probe_children()
2743 PCI_CONF_BASE0) != PCICFG_SUCCESS) { in cardbus_probe_children()
2749 PCI_CONF_BASE0, request, in cardbus_probe_children()
2848 PCI_CONF_BASE0) != PCICFG_SUCCESS) { in cardbus_probe_children()
2960 i = PCI_CONF_BASE0; in cardbus_probe_children()
4361 pci_config_get32(config_handle, PCI_CONF_BASE0),
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| /titanic_41/usr/src/uts/common/sys/ |
| H A D | pci.h | 53 #define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */ macro
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| /titanic_41/usr/src/uts/common/os/ |
| H A D | sunpci.c | 519 chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
873 pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
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| /titanic_41/usr/src/uts/common/io/ixgbe/ |
| H A D | ixgbe_debug.c | 224 pci_config_get32(handle, PCI_CONF_BASE0)); in ixgbe_pci_dump()
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| /titanic_41/usr/src/uts/common/io/e1000g/ |
| H A D | e1000g_debug.c | 418 pciconfig_bar(Adapter, PCI_CONF_BASE0, "PCI_CONF_BASE0"); in pciconfig_dump()
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| H A D | e1000g_main.c | 1181 ASSERT((bar_offset >= PCI_CONF_BASE0) && in e1000g_get_bar_info()
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| /titanic_41/usr/src/cmd/pcitool/ |
| H A D | pcitool.c | 275 { PCI_CONF_BASE0, 4, "BAR0", "Base Address Register 0 (@10)" },
287 { PCI_CONF_BASE0, 4, "BAR0", "Base Address Register 0 (@10)" },
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| /titanic_41/usr/src/uts/sun4u/io/pci/ |
| H A D | db21554.c | 1021 if ((offset == PCI_CONF_BASE0) && in db_enable_io()
1035 (off_t)(p_offset + PCI_CONF_BASE0))); in db_enable_io()
1040 (off_t)(p_offset + PCI_CONF_BASE0))); in db_enable_io()
1633 ph->bar0 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE0); in db_pci_get_header()
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| H A D | pci_tools.c | 90 PCI_CONF_BASE0,
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| /titanic_41/usr/src/uts/sun4/io/px/ |
| H A D | px_tools.c | 57 PCI_CONF_BASE0,
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| /titanic_41/usr/src/uts/intel/io/pci/ |
| H A D | pci_boot.c | 2426 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); in add_reg_props()
2427 for (j = 0, offset = PCI_CONF_BASE0; offset < end; in add_reg_props()
3295 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); in create_ioapic_node()
3302 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); in create_ioapic_node()
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| /titanic_41/usr/src/uts/intel/io/hotplug/pcicfg/ |
| H A D | pcicfg.c | 419 pci_config_get32(config_handle, PCI_CONF_BASE0)); in pcicfg_dump_common_config()
1876 offset = PCI_CONF_BASE0; in pcicfg_bridge_assign()
2033 offset = PCI_CONF_BASE0; in pcicfg_device_assign()
3856 i = PCI_CONF_BASE0; in pcicfg_populate_reg_props()
3938 i = PCI_CONF_BASE0; in pcicfg_populate_props_from_bar()
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| /titanic_41/usr/src/uts/i86pc/io/pci/ |
| H A D | pci_tools.c | 68 PCI_CONF_BASE0,
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| /titanic_41/usr/src/uts/sun4/io/ |
| H A D | pcicfg.c | 448 pci_config_get32(config_handle, PCI_CONF_BASE0)); in pcicfg_dump_common_config()
1979 offset = PCI_CONF_BASE0; in pcicfg_bridge_assign()
4202 i = PCI_CONF_BASE0; in pcicfg_populate_reg_props()
4790 i = PCI_CONF_BASE0; in pcicfg_populate_props_from_bar()
6021 for (i = PCI_CONF_BASE0; i <= PCI_CONF_BASE5; ) { in pcicfg_fcode_assign_bars()
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| /titanic_41/usr/src/uts/common/io/scsi/adapters/pmcs/ |
| H A D | pmcs_fwlog.c | 751 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE0)); in pmcs_dump_pcie_conf()
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| /titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlge/ |
| H A D | qlge_dbg.c | 664 pci_config_get32(qlge->pci_handle, PCI_CONF_BASE0); in ql_dump_pci_config()
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| /titanic_41/usr/src/uts/common/io/mega_sas/ |
| H A D | megaraid_sas.c | 460 instance->pci_handle, PCI_CONF_BASE0); in megasas_attach()
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| /titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlc/ |
| H A D | ql_api.c | 997 size = ql_pci_config_get32(ha, PCI_CONF_BASE0) & BIT_0 ? in ql_attach()
15222 chs.chs_base0 = ql_pci_config_get32(ha, PCI_CONF_BASE0); in ql_save_config_regs()
15287 ql_pci_config_put32(ha, PCI_CONF_BASE0, chs_p->chs_base0); in ql_restore_config_regs()
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| H A D | ql_xioctl.c | 1375 chip.IoAddr = ql_pci_config_get32(ha, PCI_CONF_BASE0); in ql_qry_chip()
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| /titanic_41/usr/src/uts/common/io/mr_sas/ |
| H A D | mr_sas.c | 606 instance->pci_handle, PCI_CONF_BASE0); in mrsas_attach()
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| /titanic_41/usr/src/uts/common/io/aac/ |
| H A D | aac.c | 2201 pci_config_get32(pci_config_handle, PCI_CONF_BASE0); in aac_check_card_type()
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