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Searched refs:PCI_CAP_GET32 (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/common/io/
H A Dpci_intr_lib.c226 PCI_CAP_GET32(h, NULL, caps_ptr, PCI_MSI_ADDR_OFFSET))); in pci_msi_configure()
233 "32bit msi_addr = %x\n", PCI_CAP_GET32(h, NULL, in pci_msi_configure()
510 if ((mask_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr, in pci_msi_set_mask()
573 if ((mask_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr, in pci_msi_clr_mask()
640 if ((pending_bits = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr, in pci_msi_get_pending()
812 msix_p->msix_tbl_offset = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr, in pci_msix_init()
873 msix_p->msix_pba_offset = PCI_CAP_GET32(cfg_hdle, NULL, caps_ptr, in pci_msix_init()
/titanic_41/usr/src/uts/common/sys/
H A Dpci_cap.h82 #define PCI_CAP_GET32(h, i, b, o) ((uint32_t) \ macro
/titanic_41/usr/src/uts/i86pc/io/amd_iommu/
H A Damd_iommu_impl.c937 low_addr32 = PCI_CAP_GET32(handle, 0, cap_base, in amd_iommu_init()
973 caphdr = PCI_CAP_GET32(handle, 0, cap_base, AMD_IOMMU_CAP_HDR_OFF); in amd_iommu_init()
994 hi_addr32 = PCI_CAP_GET32(handle, 0, cap_base, in amd_iommu_init()
1010 range = PCI_CAP_GET32(handle, 0, cap_base, AMD_IOMMU_CAP_RANGE_OFF); in amd_iommu_init()
1036 misc = PCI_CAP_GET32(handle, 0, cap_base, AMD_IOMMU_CAP_MISC_OFF); in amd_iommu_init()
1300 caphdr = PCI_CAP_GET32(handle, 0, cap_base, in amd_iommu_setup()
/titanic_41/usr/src/uts/common/io/pciex/
H A Dpcie.c2295 val = PCI_CAP_GET32(handle, NULL, cap_ptr, PCIE_ARI_CAP); in pcie_ari_get_next_function()
/titanic_41/usr/src/uts/common/io/ib/adapters/hermon/
H A Dhermon.c4662 state->hs_msix_tbl_offset = PCI_CAP_GET32(pci_cfg_hdl, NULL, caps_ctrl, in hermon_set_msix_info()
4712 state->hs_msix_pba_offset = PCI_CAP_GET32(pci_cfg_hdl, NULL, caps_ctrl, in hermon_set_msix_info()
/titanic_41/usr/src/uts/sun4/io/
H A Dpcicfg.c582 config = PCI_CAP_GET32(handle, NULL, cap_ptr, in pcicfg_get_nslots()
3544 wordval = (PCI_CAP_GET32(config_handle, NULL, in pcicfg_set_standard_props()