xref: /titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/pcics_reg_driver.h (revision f391a51a4e9639750045473dba1cc2831267c93e)
1 
2 /* offset of configuration space in the pci core register */
3 #define PCICFG_OFFSET					0x2000
4 #define PCICFG_VENDOR_ID_OFFSET				0x00
5 #define PCICFG_DEVICE_ID_OFFSET				0x02
6 #define PCICFG_COMMAND_OFFSET				0x04
7 #define PCICFG_COMMAND_IO_SPACE			(1<<0)
8 #define PCICFG_COMMAND_MEM_SPACE		(1<<1)
9 #define PCICFG_COMMAND_BUS_MASTER		(1<<2)
10 #define PCICFG_COMMAND_SPECIAL_CYCLES		(1<<3)
11 #define PCICFG_COMMAND_MWI_CYCLES		(1<<4)
12 #define PCICFG_COMMAND_VGA_SNOOP		(1<<5)
13 #define PCICFG_COMMAND_PERR_ENA			(1<<6)
14 #define PCICFG_COMMAND_STEPPING			(1<<7)
15 #define PCICFG_COMMAND_SERR_ENA			(1<<8)
16 #define PCICFG_COMMAND_FAST_B2B			(1<<9)
17 #define PCICFG_COMMAND_INT_DISABLE		(1<<10)
18 #define PCICFG_COMMAND_RESERVED			(0x1f<<11)
19 #define PCICFG_STATUS_OFFSET				0x06
20 #define PCICFG_REVISION_ID_OFFSET			0x08
21 #define PCICFG_REVESION_ID_MASK			0xff
22 #define PCICFG_REVESION_ID_ERROR_VAL		0xff
23 #define PCICFG_CACHE_LINE_SIZE				0x0c
24 #define PCICFG_LATENCY_TIMER				0x0d
25 #define PCICFG_HEADER_TYPE  				0x0e
26 #define PCICFG_HEADER_TYPE_NORMAL          0
27 #define PCICFG_HEADER_TYPE_BRIDGE          1
28 #define PCICFG_HEADER_TYPE_CARDBUS         2
29 #define PCICFG_BAR_1_LOW				0x10
30 #define PCICFG_BAR_1_HIGH				0x14
31 #define PCICFG_BAR_2_LOW				0x18
32 #define PCICFG_BAR_2_HIGH				0x1c
33 #define PCICFG_BAR_3_LOW				0x20
34 #define PCICFG_BAR_3_HIGH				0x24
35 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET		0x2c
36 #define PCICFG_SUBSYSTEM_ID_OFFSET			0x2e
37 #define PCICFG_INT_LINE					0x3c
38 #define PCICFG_INT_PIN					0x3d
39 #define PCICFG_PM_CAPABILITY				0x48
40 #define PCICFG_PM_CAPABILITY_VERSION		(0x3<<16)
41 #define PCICFG_PM_CAPABILITY_CLOCK		(1<<19)
42 #define PCICFG_PM_CAPABILITY_RESERVED		(1<<20)
43 #define PCICFG_PM_CAPABILITY_DSI		(1<<21)
44 #define PCICFG_PM_CAPABILITY_AUX_CURRENT	(0x7<<22)
45 #define PCICFG_PM_CAPABILITY_D1_SUPPORT		(1<<25)
46 #define PCICFG_PM_CAPABILITY_D2_SUPPORT		(1<<26)
47 #define PCICFG_PM_CAPABILITY_PME_IN_D0		(1<<27)
48 #define PCICFG_PM_CAPABILITY_PME_IN_D1		(1<<28)
49 #define PCICFG_PM_CAPABILITY_PME_IN_D2		(1<<29)
50 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT	(1<<30)
51 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD	(1<<31)
52 #define PCICFG_PM_CSR_OFFSET				0x4c
53 #define PCICFG_PM_CSR_STATE			(0x3<<0)
54 #define PCICFG_PM_CSR_PME_ENABLE		(1<<8)
55 #define PCICFG_PM_CSR_PME_STATUS		(1<<15)
56 #define PCICFG_VPD_FLAG_ADDR_OFFSET			0x50
57 #define PCICFG_VPD_DATA_OFFSET				0x54
58 #define PCICFG_MSI_CAP_ID_OFFSET			0x58
59 #define PCICFG_MSI_CONTROL_ENABLE		(0x1<<16)
60 #define PCICFG_MSI_CONTROL_MCAP			(0x7<<17)
61 #define PCICFG_MSI_CONTROL_MENA			(0x7<<20)
62 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP	(0x1<<23)
63 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE	(0x1<<24)
64 #define PCICFG_MSI_ADDR_LOW_OFFSET			0x5c
65 #define PCICFG_MSI_ADDR_HIGH_OFFSET			0x60
66 #define PCICFG_MSI_DATA_OFFSET				0x64
67 #define PCICFG_GRC_ADDRESS				0x78
68 #define PCICFG_GRC_DATA					0x80
69 #define PCICFG_ME_REGISTER                  0x98
70 #define PCICFG_MSIX_CAP_ID_OFFSET			0xa0
71 #define PCICFG_MSIX_CONTROL_TABLE_SIZE		(0x7ff<<16)
72 #define PCICFG_MSIX_CONTROL_RESERVED		(0x7<<27)
73 #define PCICFG_MSIX_CONTROL_FUNC_MASK		(0x1<<30)
74 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE		(0x1<<31)
75 
76 #define PCICFG_DEVICE_CONTROL				0xb4
77 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND   (1<<21)
78 #define PCICFG_DEVICE_STATUS				0xb6
79 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET	(1<<0)
80 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET	(1<<1)
81 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET	(1<<2)
82 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET	(1<<3)
83 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET	(1<<4)
84 #define PCICFG_DEVICE_STATUS_NO_PEND		(1<<5)
85 #define PCICFG_LINK_CONTROL				0xbc
86 
87 
88 /* config_2 offset */
89 #define GRC_CONFIG_2_SIZE_REG				0x408
90 #define PCI_CONFIG_2_BAR1_SIZE			(0xfL<<0)
91 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED		(0L<<0)
92 #define PCI_CONFIG_2_BAR1_SIZE_64K		(1L<<0)
93 #define PCI_CONFIG_2_BAR1_SIZE_128K		(2L<<0)
94 #define PCI_CONFIG_2_BAR1_SIZE_256K		(3L<<0)
95 #define PCI_CONFIG_2_BAR1_SIZE_512K		(4L<<0)
96 #define PCI_CONFIG_2_BAR1_SIZE_1M		(5L<<0)
97 #define PCI_CONFIG_2_BAR1_SIZE_2M		(6L<<0)
98 #define PCI_CONFIG_2_BAR1_SIZE_4M		(7L<<0)
99 #define PCI_CONFIG_2_BAR1_SIZE_8M		(8L<<0)
100 #define PCI_CONFIG_2_BAR1_SIZE_16M		(9L<<0)
101 #define PCI_CONFIG_2_BAR1_SIZE_32M		(10L<<0)
102 #define PCI_CONFIG_2_BAR1_SIZE_64M		(11L<<0)
103 #define PCI_CONFIG_2_BAR1_SIZE_128M		(12L<<0)
104 #define PCI_CONFIG_2_BAR1_SIZE_256M		(13L<<0)
105 #define PCI_CONFIG_2_BAR1_SIZE_512M		(14L<<0)
106 #define PCI_CONFIG_2_BAR1_SIZE_1G		(15L<<0)
107 #define PCI_CONFIG_2_BAR1_64ENA			(1L<<4)
108 #define PCI_CONFIG_2_EXP_ROM_RETRY		(1L<<5)
109 #define PCI_CONFIG_2_CFG_CYCLE_RETRY		(1L<<6)
110 #define PCI_CONFIG_2_FIRST_CFG_DONE		(1L<<7)
111 #define PCI_CONFIG_2_EXP_ROM_SIZE		(0xffL<<8)
112 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED	(0L<<8)
113 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K		(1L<<8)
114 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K		(2L<<8)
115 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K		(3L<<8)
116 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K		(4L<<8)
117 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K		(5L<<8)
118 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K		(6L<<8)
119 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K		(7L<<8)
120 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K		(8L<<8)
121 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K		(9L<<8)
122 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M		(10L<<8)
123 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M		(11L<<8)
124 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M		(12L<<8)
125 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M		(13L<<8)
126 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M		(14L<<8)
127 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M		(15L<<8)
128 #define PCI_CONFIG_2_BAR_PREFETCH		(1L<<16)
129 #define PCI_CONFIG_2_RESERVED0			(0x7fffL<<17)
130 
131 /* config_3 offset */
132 #define GRC_CONFIG_3_SIZE_REG				0x40c
133 #define PCI_CONFIG_3_STICKY_BYTE			(0xffL<<0)
134 #define PCI_CONFIG_3_FORCE_PME			(1L<<24)
135 #define PCI_CONFIG_3_PME_STATUS			(1L<<25)
136 #define PCI_CONFIG_3_PME_ENABLE			(1L<<26)
137 #define PCI_CONFIG_3_PM_STATE			(0x3L<<27)
138 #define PCI_CONFIG_3_VAUX_PRESET			(1L<<30)
139 #define PCI_CONFIG_3_PCI_POWER			(1L<<31)
140 
141 #define GRC_REG_DEVICE_CONTROL              0x4d8
142 #define PCIE_SRIOV_DISABLE_IN_PROGRESS      (1 << 29) /*When VF Enable is cleared(after it was previously set),
143                                                         this register will read a value of 1, indicating that all the
144                                                         VFs that belong to this PF should be flushed.
145                                                         Software should clear this bit within 1 second of VF Enable
146                                                         being set by writing a 1 to it, so that VFs are visible to the system again.
147                                                         WC */
148 #define PCIE_FLR_IN_PROGRESS                (1 << 27) /*When FLR is initiated, this register will read a value of 1 indicating that the
149                                                         Function is in FLR state. Func can be brought out of FLR state either by
150                                                         writing 1 to this register (at least 50 ms after FLR was initiated),
151                                                         or it can also be cleared automatically after 55 ms if auto_clear bit
152                                                         in private reg space is set. This bit also exists in VF register space
153                                                         WC */
154 
155 #define GRC_BAR2_CONFIG					0x4e0
156 #define PCI_CONFIG_2_BAR2_SIZE			(0xfL<<0)
157 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED		(0L<<0)
158 #define PCI_CONFIG_2_BAR2_SIZE_64K		(1L<<0)
159 #define PCI_CONFIG_2_BAR2_SIZE_128K		(2L<<0)
160 #define PCI_CONFIG_2_BAR2_SIZE_256K		(3L<<0)
161 #define PCI_CONFIG_2_BAR2_SIZE_512K		(4L<<0)
162 #define PCI_CONFIG_2_BAR2_SIZE_1M		(5L<<0)
163 #define PCI_CONFIG_2_BAR2_SIZE_2M		(6L<<0)
164 #define PCI_CONFIG_2_BAR2_SIZE_4M		(7L<<0)
165 #define PCI_CONFIG_2_BAR2_SIZE_8M		(8L<<0)
166 #define PCI_CONFIG_2_BAR2_SIZE_16M		(9L<<0)
167 #define PCI_CONFIG_2_BAR2_SIZE_32M		(10L<<0)
168 #define PCI_CONFIG_2_BAR2_SIZE_64M		(11L<<0)
169 #define PCI_CONFIG_2_BAR2_SIZE_128M		(12L<<0)
170 #define PCI_CONFIG_2_BAR2_SIZE_256M		(13L<<0)
171 #define PCI_CONFIG_2_BAR2_SIZE_512M		(14L<<0)
172 #define PCI_CONFIG_2_BAR2_SIZE_1G		(15L<<0)
173 #define PCI_CONFIG_2_BAR2_64ENA			(1L<<4)
174 
175 #define GRC_BAR3_CONFIG					0x4f4
176 #define PCI_CONFIG_2_BAR3_SIZE			(0xfL<<0)
177 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED		(0L<<0)
178 #define PCI_CONFIG_2_BAR3_SIZE_64K		(1L<<0)
179 #define PCI_CONFIG_2_BAR3_SIZE_128K		(2L<<0)
180 #define PCI_CONFIG_2_BAR3_SIZE_256K		(3L<<0)
181 #define PCI_CONFIG_2_BAR3_SIZE_512K		(4L<<0)
182 #define PCI_CONFIG_2_BAR3_SIZE_1M		(5L<<0)
183 #define PCI_CONFIG_2_BAR3_SIZE_2M		(6L<<0)
184 #define PCI_CONFIG_2_BAR3_SIZE_4M		(7L<<0)
185 #define PCI_CONFIG_2_BAR3_SIZE_8M		(8L<<0)
186 #define PCI_CONFIG_2_BAR3_SIZE_16M		(9L<<0)
187 #define PCI_CONFIG_2_BAR3_SIZE_32M		(10L<<0)
188 #define PCI_CONFIG_2_BAR3_SIZE_64M		(11L<<0)
189 #define PCI_CONFIG_2_BAR3_SIZE_128M		(12L<<0)
190 #define PCI_CONFIG_2_BAR3_SIZE_256M		(13L<<0)
191 #define PCI_CONFIG_2_BAR3_SIZE_512M		(14L<<0)
192 #define PCI_CONFIG_2_BAR3_SIZE_1G		(15L<<0)
193 #define PCI_CONFIG_2_BAR3_64ENA			(1L<<4)
194 
195 #define PCI_PM_DATA_A					0x410
196 #define PCI_PM_DATA_B					0x414
197 #define PCI_ID_VAL1					0x434
198 #define PCI_ID_VAL2					0x438
199 #define PCI_ID_VAL3					0x43c
200 #define PCI_ID_VAL3_REVISION_ID_ERROR             (0xffL<<24)
201 
202 
203 #define GRC_CONFIG_REG_VF_BAR_REG_1             0x608
204 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE     0xf
205 
206 #define GRC_CONFIG_REG_VF_MSIX_CONTROL              0x61C
207 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK   0x3F  /*This field resides in VF only and does not exist in PF.
208                                                             This register controls the read value of the MSIX_CONTROL[10:0] register
209                                                             in the VF configuration space. A value of "00000000011" indicates
210                                                             a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ
211                                                             define in version.v */
212 
213 #define GRC_CONFIG_REG_PF_INIT_VF               0x624
214 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK  0xf /*First VF_NUM for PF is encoded in this register.
215                                                     The number of VFs assigned to a PF is assumed to be a multiple of 8.
216                                                     Software should program these bits based on Total Number of VFs programmed for each PF.
217                                                     Since registers from 0x000-0x7ff are spilt across functions, each PF will have
218                                                     the same location for the same 4 bits*/
219 
220 #define PXPCS_TL_CONTROL_5                      0x814
221 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN    (1 << 29) /*WC*/
222 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN     (1 << 28)   /*WC*/
223 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN   (1 << 27)   /*WC*/
224 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN    (1 << 26)   /*WC*/
225 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR  (1 << 25)   /*WC*/
226 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW     (1 << 24)   /*WC*/
227 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN    (1 << 23)   /*RO*/
228 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN     (1 << 22)   /*RO*/
229 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE   (1 << 21)   /*WC*/
230 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG  (1 << 20)   /*WC*/
231 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1   (1 << 19)   /*WC*/
232 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1   (1 << 18)   /*WC*/
233 #define PXPCS_TL_CONTROL_5_ERR_ECRC1   (1 << 17)   /*WC*/
234 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1   (1 << 16)   /*WC*/
235 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1   (1 << 15)   /*WC*/
236 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1  (1 << 14)   /*WC*/
237 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1    (1 << 13)   /*WC*/
238 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1    (1 << 12)   /*WC*/
239 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1    (1 << 11)   /*WC*/
240 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1   (1 << 10)   /*WC*/
241 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT    (1 << 9)    /*WC*/
242 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT    (1 << 8)    /*WC*/
243 #define PXPCS_TL_CONTROL_5_ERR_ECRC    (1 << 7)    /*WC*/
244 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP    (1 << 6)    /*WC*/
245 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW    (1 << 5)    /*WC*/
246 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL   (1 << 4)    /*WC*/
247 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT     (1 << 3)    /*WC*/
248 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT     (1 << 2)    /*WC*/
249 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL     (1 << 1)    /*WC*/
250 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP    (1 << 0)    /*WC*/
251 
252 
253 
254 
255 
256 #define PXPCS_TL_FUNC345_STAT      0x854
257 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4    (1 << 29)   /* WC */
258 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4    (1 << 28)   /* Unsupported Request Error Status in function4, if set, generate pcie_err_attn output when this error is seen.  WC */
259 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4    (1 << 27)   /* ECRC Error TLP Status Status in function 4, if set, generate pcie_err_attn output when this error is seen..  WC */
260 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4    (1 << 26)   /* Malformed TLP Status Status in function 4, if set, generate pcie_err_attn output when this error is seen..  WC */
261 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4    (1 << 25)   /* Receiver Overflow Status Status in function 4, if set, generate pcie_err_attn output when this error is seen..  WC */
262 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4   (1 << 24)   /* Unexpected Completion Status Status in function 4, if set, generate pcie_err_attn output when this error is seen.  WC */
263 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4     (1 << 23)   /* Receive UR Statusin function 4. If set, generate pcie_err_attn output when this error is seen.  WC */
264 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4     (1 << 22)   /* Completer Timeout Status Status in function 4, if set, generate pcie_err_attn output when this error is seen.  WC */
265 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4     (1 << 21)   /* Flow Control Protocol Error Status Status in function 4, if set, generate pcie_err_attn output when this error is seen.  WC */
266 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4    (1 << 20)   /* Poisoned Error Status Status in function 4, if set, generate pcie_err_attn output when this error is seen..  WC */
267 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3    (1 << 19)   /* WC */
268 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3    (1 << 18)   /* Unsupported Request Error Status in function3, if set, generate pcie_err_attn output when this error is seen.  WC */
269 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3    (1 << 17)   /* ECRC Error TLP Status Status in function 3, if set, generate pcie_err_attn output when this error is seen..  WC */
270 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3    (1 << 16)   /* Malformed TLP Status Status in function 3, if set, generate pcie_err_attn output when this error is seen..  WC */
271 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3    (1 << 15)   /* Receiver Overflow Status Status in function 3, if set, generate pcie_err_attn output when this error is seen..  WC */
272 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3   (1 << 14)   /* Unexpected Completion Status Status in function 3, if set, generate pcie_err_attn output when this error is seen.  WC */
273 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3     (1 << 13)   /* Receive UR Statusin function 3. If set, generate pcie_err_attn output when this error is seen.  WC */
274 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3     (1 << 12)   /* Completer Timeout Status Status in function 3, if set, generate pcie_err_attn output when this error is seen.  WC */
275 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3     (1 << 11)   /* Flow Control Protocol Error Status Status in function 3, if set, generate pcie_err_attn output when this error is seen.  WC */
276 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3    (1 << 10)   /* Poisoned Error Status Status in function 3, if set, generate pcie_err_attn output when this error is seen..  WC */
277 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2    (1 << 9)    /* WC */
278 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2    (1 << 8)    /* Unsupported Request Error Status for Function 2, if set, generate pcie_err_attn output when this error is seen.  WC */
279 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2    (1 << 7)    /* ECRC Error TLP Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen..  WC */
280 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2    (1 << 6)    /* Malformed TLP Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen..  WC */
281 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2    (1 << 5)    /* Receiver Overflow Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen..  WC */
282 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2   (1 << 4)    /* Unexpected Completion Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen.  WC */
283 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2     (1 << 3)    /* Receive UR Statusfor Function 2. If set, generate pcie_err_attn output when this error is seen.  WC */
284 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2     (1 << 2)    /* Completer Timeout Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen.  WC */
285 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2     (1 << 1)    /* Flow Control Protocol Error Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen.  WC */
286 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2    (1 << 0)    /* Poisoned Error Status Status for Function 2, if set, generate pcie_err_attn output when this error is seen..  WC */
287 
288 
289 
290 
291 #define PXPCS_TL_FUNC678_STAT  0x85C
292 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7    (1 << 29)   /*    WC */
293 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7    (1 << 28)   /* Unsupported Request Error Status in function7, if set, generate pcie_err_attn output when this error is seen. WC */
294 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7    (1 << 27)   /* ECRC Error TLP Status Status in function 7, if set, generate pcie_err_attn output when this error is seen.. WC */
295 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7    (1 << 26)   /* Malformed TLP Status Status in function 7, if set, generate pcie_err_attn output when this error is seen.. WC */
296 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7    (1 << 25)   /* Receiver Overflow Status Status in function 7, if set, generate pcie_err_attn output when this error is seen.. WC */
297 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7   (1 << 24)   /* Unexpected Completion Status Status in function 7, if set, generate pcie_err_attn output when this error is seen. WC */
298 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7     (1 << 23)   /* Receive UR Statusin function 7. If set, generate pcie_err_attn output when this error is seen. WC */
299 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7     (1 << 22)   /* Completer Timeout Status Status in function 7, if set, generate pcie_err_attn output when this error is seen. WC */
300 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7     (1 << 21)   /* Flow Control Protocol Error Status Status in function 7, if set, generate pcie_err_attn output when this error is seen. WC */
301 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7    (1 << 20)   /* Poisoned Error Status Status in function 7, if set, generate pcie_err_attn output when this error is seen.. WC */
302 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6    (1 << 19)    /*    WC */
303 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6    (1 << 18)   /* Unsupported Request Error Status in function6, if set, generate pcie_err_attn output when this error is seen. WC */
304 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6    (1 << 17)   /* ECRC Error TLP Status Status in function 6, if set, generate pcie_err_attn output when this error is seen.. WC */
305 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6    (1 << 16)   /* Malformed TLP Status Status in function 6, if set, generate pcie_err_attn output when this error is seen.. WC */
306 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6    (1 << 15)   /* Receiver Overflow Status Status in function 6, if set, generate pcie_err_attn output when this error is seen.. WC */
307 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6   (1 << 14)   /* Unexpected Completion Status Status in function 6, if set, generate pcie_err_attn output when this error is seen. WC */
308 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6     (1 << 13)   /* Receive UR Statusin function 6. If set, generate pcie_err_attn output when this error is seen. WC */
309 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6     (1 << 12)   /* Completer Timeout Status Status in function 6, if set, generate pcie_err_attn output when this error is seen. WC */
310 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6     (1 << 11)   /* Flow Control Protocol Error Status Status in function 6, if set, generate pcie_err_attn output when this error is seen. WC */
311 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6    (1 << 10)   /* Poisoned Error Status Status in function 6, if set, generate pcie_err_attn output when this error is seen.. WC */
312 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5    (1 << 9) /*    WC */
313 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5    (1 << 8)    /* Unsupported Request Error Status for Function 5, if set, generate pcie_err_attn output when this error is seen. WC */
314 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5    (1 << 7)    /* ECRC Error TLP Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen.. WC */
315 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5    (1 << 6)    /* Malformed TLP Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen.. WC */
316 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5    (1 << 5)    /* Receiver Overflow Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen.. WC */
317 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5   (1 << 4)    /* Unexpected Completion Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen. WC */
318 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5     (1 << 3)    /* Receive UR Statusfor Function 5. If set, generate pcie_err_attn output when this error is seen. WC */
319 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5     (1 << 2)    /* Completer Timeout Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen. WC */
320 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5     (1 << 1)    /* Flow Control Protocol Error Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen. WC */
321 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5    (1 << 0)    /* Poisoned Error Status Status for Function 5, if set, generate pcie_err_attn output when this error is seen.. WC */
322 
323 
324 
325 #define BAR_USTRORM_INTMEM				0x400000
326 #define BAR_CSTRORM_INTMEM				0x410000
327 #define BAR_XSTRORM_INTMEM				0x420000
328 #define BAR_TSTRORM_INTMEM				0x430000
329 
330 /* for accessing the IGU in case of status block ACK */
331 #define BAR_IGU_INTMEM  				0x440000
332 
333 #define BAR_DOORBELL_OFFSET     			0x800000
334 
335 #define BAR_ME_REGISTER 				0x450000
336 #define ME_REG_PF_NUM_SHIFT             0
337 #define ME_REG_PF_NUM                   (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
338 #define ME_REG_VF_VALID                 (1<<8)
339 #define ME_REG_VF_NUM_SHIFT             9
340 #define ME_REG_VF_NUM_MASK              (0x3f<<ME_REG_VF_NUM_SHIFT)
341 #define ME_REG_VF_ERR			(0x1<<3)
342 #define ME_REG_ABS_PF_NUM_SHIFT         16
343 #define ME_REG_ABS_PF_NUM               (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
344 
345 
346 // Everest Address Space Mapping - For Virtual Functions - Bar 0
347 
348 #define PXP_VF_ADRR_NUM_QUEUES		136
349 #define PXP_ADDR_QUEUE_SIZE			32
350 #define PXP_ADDR_REG_SIZE			512
351 
352 
353 #define PXP_VF_ADDR_IGU_START		0
354 #define PXP_VF_ADDR_IGU_SIZE		(0x3000)
355 #define PXP_VF_ADDR_IGU_END			((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
356 
357 #define PXP_VF_ADDR_USDM_QUEUES_START		0x3000
358 #define PXP_VF_ADDR_USDM_QUEUES_SIZE		(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
359 #define PXP_VF_ADDR_USDM_QUEUES_END			((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
360 
361 #define PXP_VF_ADDR_CSDM_QUEUES_START		0x4100
362 #define PXP_VF_ADDR_CSDM_QUEUES_SIZE		(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
363 #define PXP_VF_ADDR_CSDM_QUEUES_END			((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1)
364 
365 #define PXP_VF_ADDR_XSDM_QUEUES_START		0x5200
366 #define PXP_VF_ADDR_XSDM_QUEUES_SIZE		(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
367 #define PXP_VF_ADDR_XSDM_QUEUES_END			((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1)
368 
369 #define PXP_VF_ADDR_TSDM_QUEUES_START		0x6300
370 #define PXP_VF_ADDR_TSDM_QUEUES_SIZE		(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
371 #define PXP_VF_ADDR_TSDM_QUEUES_END			((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1)
372 
373 #define PXP_VF_ADDR_USDM_GLOBAL_START		0x7400
374 #define PXP_VF_ADDR_USDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
375 #define PXP_VF_ADDR_USDM_GLOBAL_END			((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1)
376 
377 #define PXP_VF_ADDR_CSDM_GLOBAL_START		0x7600
378 #define PXP_VF_ADDR_CSDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
379 #define PXP_VF_ADDR_CSDM_GLOBAL_END			((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
380 
381 #define PXP_VF_ADDR_XSDM_GLOBAL_START		0x7800
382 #define PXP_VF_ADDR_XSDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
383 #define PXP_VF_ADDR_XSDM_GLOBAL_END			((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1)
384 
385 #define PXP_VF_ADDR_TSDM_GLOBAL_START		0x7a00
386 #define PXP_VF_ADDR_TSDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
387 #define PXP_VF_ADDR_TSDM_GLOBAL_END			((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1)
388 
389 // DB in BAR1
390 #define PXP_VF_ADDR_DB_START				0x7c00
391 #define PXP_VF_ADDR_DB_SIZE					(0x200)
392 #define PXP_VF_ADDR_DB_END					((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
393 
394 #define PXP_VF_ADDR_GRC_START				0x7e00
395 #define PXP_VF_ADDR_GRC_SIZE				(0x200)
396 #define PXP_VF_ADDR_GRC_END					((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1)
397 
398 // DB in BAR2
399 #define PXP_VF_ADDR_DORQ_START				(0x0)
400 #define PXP_VF_ADDR_DORQ_SIZE				(0xffffffff)
401 #define PXP_VF_ADDR_DORQ_END				(0xffffffff)
402 
403 // function numbers
404 #define PXP_BAR_GRC		0
405 #define PXP_BAR_TSDM	0
406 #define PXP_BAR_USDM	0
407 #define PXP_BAR_XSDM	0
408 #define PXP_BAR_CSDM	0
409 #define PXP_BAR_IGU		0
410 #define PXP_BAR_DQ		1
411 
412 #define PXP_VF_BAR_IGU	0
413 #define PXP_VF_BAR_USDM_QUEUES	0
414 #define PXP_VF_BAR_TSDM_QUEUES	0
415 #define PXP_VF_BAR_XSDM_QUEUES	0
416 #define PXP_VF_BAR_CSDM_QUEUES	0
417 #define PXP_VF_BAR_USDM_GLOBAL	0
418 #define PXP_VF_BAR_TSDM_GLOBAL	0
419 #define PXP_VF_BAR_XSDM_GLOBAL	0
420 #define PXP_VF_BAR_CSDM_GLOBAL	0
421 #define PXP_VF_BAR_DB	0
422 #define PXP_VF_BAR_GRC	0
423 #define PXP_VF_BAR_DORQ	1
424 
425 /* PCI CAPABILITIES*/
426 
427 #define PCI_CAP_PCIE                            0x10    /*PCIe capability ID*/
428 
429 #define PCIE_DEV_CAPS                           0x04
430 #ifndef PCIE_DEV_CAPS_FLR_CAPABILITY
431     #define PCIE_DEV_CAPS_FLR_CAPABILITY        (1 << 28)
432 #endif
433 
434 #define PCIE_DEV_CTRL                           0x08
435 #define PCIE_DEV_CTRL_FLR                               0x8000;
436 
437 #define PCIE_DEV_STATUS                         0x0A
438 #ifndef PCIE_DEV_STATUS_PENDING_TRANSACTION
439     #define PCIE_DEV_STATUS_PENDING_TRANSACTION     (1 << 5)
440 #endif
441 
442 #define PCI_CAP_MSIX                            0x11    /*MSI-X capability ID*/
443 #define PCI_MSIX_CONTROL_SHIFT                  16
444 #define PCI_MSIX_TABLE_SIZE_MASK                0x07FF
445 #define PCI_MSIX_TABLE_ENABLE_MASK              0x8000
446 
447 #ifndef PCI_CAPABILITY_LIST
448     #define PCI_CAPABILITY_LIST                     0x34    /* Ofset of first capability list entry*/
449 #endif
450 #ifndef PCI_CB_CAPABILITY_LIST
451     #define PCI_CB_CAPABILITY_LIST                  0x14
452 #endif
453 
454 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID))
455 #define PCI_CAP_LIST_ID_DEF
456 #endif
457 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT))
458 #define PCI_CAP_LIST_NEXT_DEF
459 #endif
460 #if (defined(__LINUX)) || (defined(PCI_STATUS))
461 #define PCI_STATUS_DEF
462 #endif
463 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST))
464 #define PCI_STATUS_CAP_LIST_DEF
465 #endif
466 
467 #ifndef PCI_CAP_LIST_ID_DEF
468     #define PCI_CAP_LIST_ID                         0x0     /* Capability ID */
469 #endif
470 #ifndef PCI_CAP_LIST_NEXT_DEF
471     #define PCI_CAP_LIST_NEXT                       0x1     /* Next capability in the list */
472 #endif
473 #ifndef PCI_STATUS_DEF
474     #define PCI_STATUS                              0x6     /* 16 bits */
475 #endif
476 #ifndef PCI_STATUS_CAP_LIST_DEF
477     #define PCI_STATUS_CAP_LIST                     0x10    /* Support Capability List */
478 #endif
479