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Searched refs:OUT_RING_REG (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/uts/intel/io/drm/
H A Dradeon_state.c185 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); in radeon_check_and_fixup_packets()
1025 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE, in radeon_cp_dispatch_clear()
1028 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0); in radeon_cp_dispatch_clear()
1030 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT, in radeon_cp_dispatch_clear()
1253 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL); in radeon_cp_dispatch_clear()
1254 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL); in radeon_cp_dispatch_clear()
1255 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL); in radeon_cp_dispatch_clear()
1256 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); in radeon_cp_dispatch_clear()
1257 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, in radeon_cp_dispatch_clear()
1259 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK); in radeon_cp_dispatch_clear()
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H A Dradeon_irq.c129 OUT_RING_REG(RADEON_LAST_SWI_REG, ret); in radeon_emit_irq()
130 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE); in radeon_emit_irq()
H A Dr300_cmdbuf.c108 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]); in r300_emit_cliprects()
138 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0); in r300_emit_cliprects()
383 OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0); in r300_emit_vpu()
384 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); in r300_emit_vpu()
H A Dradeon_drv.h1175 #define OUT_RING_REG(reg, val) do { \ macro