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Searched refs:OUT_RING (Results 1 – 7 of 7) sorted by relevance

/titanic_41/usr/src/uts/intel/io/drm/
H A Dradeon_state.c452 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeon_emit_clip_rect()
453 OUT_RING((box->y1 << 16) | box->x1); in radeon_emit_clip_rect()
454 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeon_emit_clip_rect()
455 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); in radeon_emit_clip_rect()
481 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); in radeon_emit_state()
482 OUT_RING(ctx->pp_misc); in radeon_emit_state()
483 OUT_RING(ctx->pp_fog_color); in radeon_emit_state()
484 OUT_RING(ctx->re_solid_color); in radeon_emit_state()
485 OUT_RING(ctx->rb3d_blendcntl); in radeon_emit_state()
486 OUT_RING(ctx->rb3d_depthoffset); in radeon_emit_state()
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H A Di915_dma.c394 OUT_RING(cmd); in i915_emit_cmds()
402 OUT_RING(cmd); in i915_emit_cmds()
407 OUT_RING(0); in i915_emit_cmds()
435 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); in i915_emit_box()
436 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); in i915_emit_box()
437 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); in i915_emit_box()
438 OUT_RING(DR4); in i915_emit_box()
442 OUT_RING(GFX_OP_DRAWRECT_INFO); in i915_emit_box()
443 OUT_RING(DR1); in i915_emit_box()
444 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); in i915_emit_box()
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H A Dr300_cmdbuf.c80 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); in r300_emit_cliprects()
102 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
104 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
116 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); in r300_emit_cliprects()
117 OUT_RING(0); in r300_emit_cliprects()
118 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); in r300_emit_cliprects()
297 OUT_RING(CP_PACKET0(reg, sz - 1)); in r300_emit_carefully_checked_packet0()
347 OUT_RING(CP_PACKET0(reg, sz - 1)); in r300_emit_packet0()
385 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); in r300_emit_vpu()
409 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); in r300_emit_clear()
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H A Dradeon_drv.h1045 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1046 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
1051 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1052 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \
1057 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1058 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
1064 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1065 OUT_RING(RADEON_WAIT_CRTC_PFLIP); \
1069 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1070 OUT_RING(RADEON_RB3D_DC_FLUSH); \
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H A Di915_irq.c576 OUT_RING(MI_STORE_DWORD_INDEX); in i915_emit_irq()
577 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in i915_emit_irq()
578 OUT_RING(dev_priv->counter); in i915_emit_irq()
583 OUT_RING(0); in i915_emit_irq()
584 OUT_RING(MI_USER_INTERRUPT); in i915_emit_irq()
589 OUT_RING(MI_STORE_DWORD_INDEX); in i915_emit_irq()
590 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in i915_emit_irq()
591 OUT_RING(dev_priv->counter); in i915_emit_irq()
592 OUT_RING(MI_USER_INTERRUPT); in i915_emit_irq()
606 OUT_RING(0); in i915_emit_irq()
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H A Di915_gem.c613 OUT_RING(MI_STORE_DWORD_INDEX); in i915_add_request()
614 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in i915_add_request()
615 OUT_RING(seqno); in i915_add_request()
616 OUT_RING(0); in i915_add_request()
620 OUT_RING(0); in i915_add_request()
621 OUT_RING(MI_USER_INTERRUPT); in i915_add_request()
678 OUT_RING(cmd); in i915_retire_commands()
679 OUT_RING(0); /* noop */ in i915_retire_commands()
1005 OUT_RING(cmd); in i915_gem_flush()
1006 OUT_RING(0); /* noop */ in i915_gem_flush()
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H A Di915_drv.h629 #define OUT_RING(n) do { \ macro
637 #define OUT_RING(n) do { \ macro