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Searched refs:NXGE_REG_RD64 (Results 1 – 19 of 19) sorted by relevance

/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_espc.c87 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val); in npi_espc_eeprom_entry()
100 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val); in npi_espc_eeprom_entry()
119 NXGE_REG_RD64(handle, ESPC_MAC_ADDR_0, &mac0.value); in npi_espc_mac_addr_get()
125 NXGE_REG_RD64(handle, ESPC_MAC_ADDR_1, &mac1.value); in npi_espc_mac_addr_get()
137 NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val); in npi_espc_num_ports_get()
149 NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val); in npi_espc_num_macs_get()
164 NXGE_REG_RD64(handle, ESPC_MOD_STR_LEN, &val); in npi_espc_model_str_get()
181 NXGE_REG_RD64(handle, ESPC_MOD_STR(j), &val); in npi_espc_model_str_get()
200 NXGE_REG_RD64(handle, ESPC_BD_MOD_STR_LEN, &val); in npi_espc_bd_model_str_get()
218 NXGE_REG_RD64(handle, ESPC_BD_MOD_STR(j), &val); in npi_espc_bd_model_str_get()
[all …]
H A Dnpi_vir.c121 NXGE_REG_RD64(handle, pio_offset[i], &value); in npi_vir_dump_pio_fzc_regs_one()
130 NXGE_REG_RD64(handle, fzc_pio_offset[i], &value); in npi_vir_dump_pio_fzc_regs_one()
156 NXGE_REG_RD64(handle, offset, &value); in npi_vir_dump_ldgnum()
185 NXGE_REG_RD64(handle, offset, &value); in npi_vir_dump_ldsv()
214 NXGE_REG_RD64(handle, offset, in npi_vir_dump_imask0()
228 NXGE_REG_RD64(handle, offset, in npi_vir_dump_imask0()
258 NXGE_REG_RD64(handle, offset, in npi_vir_dump_sid()
295 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); in npi_dev_func_sr_init()
349 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); in npi_dev_func_sr_lock_enter()
422 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); in npi_dev_func_sr_lock_free()
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H A Dnpi_txc.c164 NXGE_REG_RD64(handle, offset, &value); in npi_txc_dump_tdc_fzc_regs()
198 NXGE_REG_RD64(handle, txc_fzc_offset[i], &value); in npi_txc_dump_fzc_regs()
236 NXGE_REG_RD64(handle, offset, &value); in npi_txc_dump_port_fzc_regs()
397 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &txc_control_p->value); in npi_txc_control()
436 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_global_enable()
463 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_global_disable()
529 NXGE_REG_RD64(handle, (TXC_TRAINING_REG & TXC_TRAINING_VECTOR_MASK), in npi_txc_training_get()
557 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_port_enable()
584 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_port_disable()
729 NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val); in npi_txc_reorder_set()
[all …]
H A Dnpi_zcp.c51 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val); in npi_zcp_config()
79 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val); in npi_zcp_config()
131 NXGE_REG_RD64(handle, ZCP_INT_MASK_REG, &val); in npi_zcp_iconfig()
168 NXGE_REG_RD64(handle, ZCP_INT_STAT_REG, &val); in npi_zcp_get_istatus()
198 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val); in npi_zcp_set_dma_thresh()
635 NXGE_REG_RD64(handle, offset, &cfifo_reg.value); in npi_zcp_rest_cfifo_port()
715 NXGE_REG_RD64(handle, ZCP_RAM_DATA0_REG, &val->w0); in zcp_mem_read()
716 NXGE_REG_RD64(handle, ZCP_RAM_DATA1_REG, &val->w1); in zcp_mem_read()
717 NXGE_REG_RD64(handle, ZCP_RAM_DATA2_REG, &val->w2); in zcp_mem_read()
718 NXGE_REG_RD64(handle, ZCP_RAM_DATA3_REG, &val->w3); in zcp_mem_read()
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H A Dnpi_rxdma.c196 NXGE_REG_RD64(handle, rx_fzc_offset[i], &value); in npi_rxdma_dump_fzc_regs()
239 NXGE_REG_RD64(handle, valid_offset, &page_vld.value); in npi_rxdma_cfg_logical_page_disable()
282 NXGE_REG_RD64(handle, valid_offset, &page_vld.value); in npi_rxdma_cfg_logical_page()
872 NXGE_REG_RD64(handle, offset, &cnt->value); in npi_rxdma_red_discard_stat_get()
917 NXGE_REG_RD64(handle, offset, &cnt.value); in npi_rxdma_red_discard_oflow_clear()
1044 NXGE_REG_RD64(handle, pre_offset, &pre_log->value); in npi_rxdma_ring_perr_stat_get()
1045 NXGE_REG_RD64(handle, sha_offset, &sha_log->value); in npi_rxdma_ring_perr_stat_get()
1112 NXGE_REG_RD64(handle, pre_offset, &clr.value); in npi_rxdma_ring_perr_stat_clear()
1135 NXGE_REG_RD64(handle, sha_offset, &clr.value); in npi_rxdma_ring_perr_stat_clear()
1214 NXGE_REG_RD64(handle, d4_offset, &d4.value); in npi_rxdma_rdmc_memory_io()
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H A Dnpi_mac.h283 NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
289 NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
295 NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
301 NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
307 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
326 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
333 NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
H A Dnpi_txc.h68 NXGE_REG_RD64(handle, \
76 NXGE_REG_RD64(handle, \
H A Dnpi_ipp.c125 NXGE_REG_RD64(handle, (uint32_t)offset, &value); in npi_ipp_dump_regs()
127 NXGE_REG_RD64(handle, offset, &value); in npi_ipp_dump_regs()
155 NXGE_REG_RD64(handle, (uint32_t)offset, &value); in npi_ipp_read_regs()
157 NXGE_REG_RD64(handle, offset, &value); in npi_ipp_read_regs()
H A Dnpi_espc.h42 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG),\
H A Dnpi_zcp.h117 NXGE_REG_RD64(handle, ZCP_RAM_ACC_REG, &val);\
H A Dnpi_ipp.h124 NXGE_REG_RD64(handle, IPP_REG_ADDR(portn, reg), val);\
H A Dnpi_txdma.c192 NXGE_REG_RD64(handle, (uint32_t)tx_fzc_offset[i], &value); in npi_txdma_dump_fzc_regs()
194 NXGE_REG_RD64(handle, tx_fzc_offset[i], &value); in npi_txdma_dump_fzc_regs()
1855 NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value); in npi_txdma_inj_par_error_update()
1868 NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value); in npi_txdma_inj_par_error_get()
H A Dnpi_txdma.h135 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_common_impl.h314 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
324 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
329 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
H A Dnxge_fflp_hw.h1098 NXGE_REG_RD64((handle), (offset), (val_p))
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_zcp.c333 NXGE_REG_RD64(nxgep->npi_handle, ZCP_INT_STAT_TEST_REG, in nxge_zcp_inject_err()
H A Dnxge_txc.c570 NXGE_REG_RD64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG, in nxge_txc_inject_err()
H A Dnxge_intr.c1074 NXGE_REG_RD64(nxge->npi_handle, offset, value); in nxge_hio_ldsv_im()
H A Dnxge_main.c1845 NXGE_REG_RD64(nxgep->npi_handle, reg, &regdata); in nxge_get64()