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Searched refs:NLP2020_CL45_PORT1_ADDR0 (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_phy_hw.h119 #define NLP2020_CL45_PORT1_ADDR0 0x11 macro
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_mac.c7546 if (nxge_is_phy_present(nxgep, NLP2020_CL45_PORT1_ADDR0, in nxge_hswap_phy_present()
7548 nxgep->xcvr_addr = NLP2020_CL45_PORT1_ADDR0; in nxge_hswap_phy_present()
8201 case NLP2020_CL45_PORT1_ADDR0: in nxge_scan_ports_phy()
8234 case NLP2020_CL45_PORT1_ADDR0: in nxge_scan_ports_phy()