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Searched refs:Mask (Results 1 – 16 of 16) sorted by relevance

/titanic_41/usr/src/uts/intel/io/acpica/executer/
H A Dexfldio.c619 UINT64 Mask, in AcpiExWriteWithUpdateRule() argument
628 ACPI_FUNCTION_TRACE_U32 (ExWriteWithUpdateRule, Mask); in AcpiExWriteWithUpdateRule()
637 if (Mask != ACPI_UINT64_MAX) in AcpiExWriteWithUpdateRule()
648 if ((~Mask << (ACPI_MUL_8 (sizeof (Mask)) - in AcpiExWriteWithUpdateRule()
662 MergedValue |= (CurrentValue & ~Mask); in AcpiExWriteWithUpdateRule()
670 MergedValue |= ~Mask; in AcpiExWriteWithUpdateRule()
677 MergedValue &= Mask; in AcpiExWriteWithUpdateRule()
693 ACPI_FORMAT_UINT64 (Mask), in AcpiExWriteWithUpdateRule()
890 UINT64 Mask; in AcpiExInsertIntoField() local
963 Mask = WidthMask & in AcpiExInsertIntoField()
[all …]
/titanic_41/usr/src/uts/intel/io/acpica/resources/
H A Drsutils.c69 UINT16 Mask, in AcpiRsDecodeBitmask() argument
81 for (i = 0, BitCount = 0; Mask; i++) in AcpiRsDecodeBitmask()
83 if (Mask & 0x0001) in AcpiRsDecodeBitmask()
89 Mask >>= 1; in AcpiRsDecodeBitmask()
115 UINT16 Mask; in AcpiRsEncodeBitmask() local
123 for (i = 0, Mask = 0; i < Count; i++) in AcpiRsEncodeBitmask()
125 Mask |= (0x1 << List[i]); in AcpiRsEncodeBitmask()
128 return (Mask); in AcpiRsEncodeBitmask()
/titanic_41/usr/src/uts/intel/sys/acpi/
H A Dacmacros.h278 #define ACPI_REGISTER_PREPARE_BITS(Val, Pos, Mask) \ argument
279 ((Val << Pos) & Mask)
281 #define ACPI_REGISTER_INSERT_VALUE(Reg, Pos, Mask, Val) \ argument
282 Reg = (Reg & (~(Mask))) | ACPI_REGISTER_PREPARE_BITS(Val, Pos, Mask)
284 #define ACPI_INSERT_BITS(Target, Mask, Source) \ argument
285 Target = ((Target & (~(Mask))) | (Source & Mask))
289 #define ACPI_GET_BITS(SourcePtr, Position, Mask) \ argument
290 ((*(SourcePtr) >> (Position)) & (Mask))
292 #define ACPI_SET_BITS(TargetPtr, Position, Mask, Value) \ argument
293 (*(TargetPtr) |= (((Value) & (Mask)) << (Position)))
H A Dacresrc.h320 UINT16 Mask,
H A Dactbl2.h199 UINT8 Mask; member
1612 UINT32 Mask; /* Bitmask required for this register instruction */ member
H A Dacinterp.h188 UINT64 Mask,
H A Dacdisasm.h844 UINT16 Mask);
H A Dactbl1.h124 UINT64 Mask; /* Bitmask required for this register instruction */ member
/titanic_41/usr/src/uts/intel/io/acpica/disassembler/
H A Ddmresrc.c193 UINT16 Mask) in AcpiDmBitList() argument
209 if (Mask & 1) in AcpiDmBitList()
220 Mask >>= 1; in AcpiDmBitList()
/titanic_41/usr/src/uts/common/io/yge/
H A Dyge.h651 #define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) argument
/titanic_41/usr/src/uts/sun4v/cpu/
H A Dcommon_asm.s445 andn %o2, 1, %o2 ! Mask off lowest bit
/titanic_41/usr/src/uts/sun4u/cpu/
H A Dcommon_asm.s599 andn %o2, 1, %o2 ! Mask off lowest bit
/titanic_41/usr/src/uts/common/smbsrv/ndl/
H A Dsamrpc.ndl181 * Alias Access Mask values for SAMR
/titanic_41/usr/src/data/hwdata/
H A Dusb.ids18633 281a RK2818 in Mask ROM mode
18634 290a RK2918 in Mask ROM mode
18635 292a RK2928 in Mask ROM mode
18636 292c RK3026 in Mask ROM mode
18637 300a RK3066 in Mask ROM mode
18638 300b RK3168 in Mask ROM mode
18639 301a RK3036 in Mask ROM mode
18640 310a RK3066B in Mask ROM mode
18641 310b RK3188 in Mask ROM mode
18642 310c RK3126/RK3128 in Mask ROM mode
[all …]
/titanic_41/usr/src/grub/grub-0.97/
H A DChangeLog2863 * stage2/disk_io.c (next_partition): Mask out bsd partition sub
5135 * stage2/boot.c (load_initrd): Mask the address with 0x3FFFFFFF
5231 Mask *DATAPTR with MASK when calling convert_to_ascii.
5317 * stage2/disk_io.c [!STAGE1_5] (print_fsys_type): Mask
5559 value. Mask FIRST_FAT_ENTRY with 0xFFF if FAT_SIZE is equal to
6805 * stage2/disk_io.c (set_bootdev): Mask 0x7F instead of 0x79 of
/titanic_41/usr/src/cmd/cmd-inet/sbin/dhcpagent/
H A DREADME.v6203 in IPv4 would have been the use of ICMP Address Mask Request /