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Searched refs:MSR_MC_STATUS_MISCV (Results 1 – 3 of 3) sorted by relevance

/titanic_41/usr/src/uts/i86pc/cpu/generic_cpu/
H A Dgcpu_mca.c586 switch (status & (MSR_MC_STATUS_ADDRV | MSR_MC_STATUS_MISCV)) { in gcpu_bleat()
587 case MSR_MC_STATUS_ADDRV | MSR_MC_STATUS_MISCV: in gcpu_bleat()
604 case MSR_MC_STATUS_MISCV: in gcpu_bleat()
805 bstat & MSR_MC_STATUS_MISCV) { in gcpu_ereport_add_logout()
1790 if (status & MSR_MC_STATUS_MISCV) in gcpu_mca_logout()
/titanic_41/usr/src/uts/intel/sys/
H A Dmca_x86.h188 #define MSR_MC_STATUS_MISCV 0x0800000000000000ULL macro
/titanic_41/usr/src/uts/i86pc/cpu/genuineintel/
H A Dgintel_main.c487 if (status & MSR_MC_STATUS_MISCV) { in gintel_ereport_add_logout()