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Searched refs:MSR_DEBUGCTL (Results 1 – 4 of 4) sorted by relevance

/titanic_41/usr/src/cmd/mdb/intel/kmdb/
H A Dkvm_cpu_p4.c166 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
167 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_p4.p4_debugctl },
183 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
184 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_p4.p4_debugctl },
205 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
206 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_p4.p4_debugctl },
250 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
251 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_p4.p4_debugctl },
H A Dkvm_cpu_amd.c75 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
76 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_amd.amd_debugctl },
88 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
89 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_amd.amd_debugctl },
/titanic_41/usr/src/cmd/mdb/intel/ia32/kmdb/
H A Dkvm_cpu_p6.c94 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
95 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_p6.p6_debugctl },
/titanic_41/usr/src/uts/intel/sys/
H A Dx86_archext.h260 #define MSR_DEBUGCTL 0x1d9 macro