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Searched refs:MSR_AMD_TSCAUX (Results 1 – 3 of 3) sorted by relevance

/titanic_41/usr/src/uts/intel/sys/
H A Dcontrolregs.h186 #define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */ macro
/titanic_41/usr/src/uts/i86pc/os/
H A Dmlsetup.c271 (void) wrmsr(MSR_AMD_TSCAUX, 0); in mlsetup()
H A Dmp_startup.c1708 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); in mp_startup_common()