xref: /titanic_41/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h (revision 6824ee06c346d29bf3a2627dcbb6d0d2f4c7b9d7)
1 /*-
2  * Copyright (c) 2013 LSI Corp.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the author nor the names of any co-contributors
14  *    may be used to endorse or promote products derived from this software
15  *    without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /*
31  *  Copyright (c) 2000-2013 LSI Corporation.
32  *
33  *
34  *           Name:  mpi2_cnfg.h
35  *          Title:  MPI Configuration messages and pages
36  *  Creation Date:  November 10, 2006
37  *
38  *    mpi2_cnfg.h Version:  02.00.27
39  *
40  *  NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
41  *        prefix are for use only on MPI v2.5 products, and must not be used
42  *        with MPI v2.0 products. Unless otherwise noted, names beginning with
43  *        MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
44  *
45  *  Version History
46  *  ---------------
47  *
48  *  Date      Version   Description
49  *  --------  --------  ------------------------------------------------------
50  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
51  *  06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
52  *                      Added Manufacturing Page 11.
53  *                      Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
54  *                      define.
55  *  06-26-07  02.00.02  Adding generic structure for product-specific
56  *                      Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
57  *                      Rework of BIOS Page 2 configuration page.
58  *                      Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
59  *                      forms.
60  *                      Added configuration pages IOC Page 8 and Driver
61  *                      Persistent Mapping Page 0.
62  *  08-31-07  02.00.03  Modified configuration pages dealing with Integrated
63  *                      RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
64  *                      RAID Physical Disk Pages 0 and 1, RAID Configuration
65  *                      Page 0).
66  *                      Added new value for AccessStatus field of SAS Device
67  *                      Page 0 (_SATA_NEEDS_INITIALIZATION).
68  *  10-31-07  02.00.04  Added missing SEPDevHandle field to
69  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
70  *  12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
71  *                      NVDATA.
72  *                      Modified IOC Page 7 to use masks and added field for
73  *                      SASBroadcastPrimitiveMasks.
74  *                      Added MPI2_CONFIG_PAGE_BIOS_4.
75  *                      Added MPI2_CONFIG_PAGE_LOG_0.
76  *  02-29-08  02.00.06  Modified various names to make them 32-character unique.
77  *                      Added SAS Device IDs.
78  *                      Updated Integrated RAID configuration pages including
79  *                      Manufacturing Page 4, IOC Page 6, and RAID Configuration
80  *                      Page 0.
81  *  05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
82  *                      Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
83  *                      Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
84  *                      Added missing MaxNumRoutedSasAddresses field to
85  *                      MPI2_CONFIG_PAGE_EXPANDER_0.
86  *                      Added SAS Port Page 0.
87  *                      Modified structure layout for
88  *                      MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
89  *  06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
90  *                      MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
91  *  10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
92  *                      to 0x000000FF.
93  *                      Added two new values for the Physical Disk Coercion Size
94  *                      bits in the Flags field of Manufacturing Page 4.
95  *                      Added product-specific Manufacturing pages 16 to 31.
96  *                      Modified Flags bits for controlling write cache on SATA
97  *                      drives in IO Unit Page 1.
98  *                      Added new bit to AdditionalControlFlags of SAS IO Unit
99  *                      Page 1 to control Invalid Topology Correction.
100  *                      Added additional defines for RAID Volume Page 0
101  *                      VolumeStatusFlags field.
102  *                      Modified meaning of RAID Volume Page 0 VolumeSettings
103  *                      define for auto-configure of hot-swap drives.
104  *                      Added SupportedPhysDisks field to RAID Volume Page 1 and
105  *                      added related defines.
106  *                      Added PhysDiskAttributes field (and related defines) to
107  *                      RAID Physical Disk Page 0.
108  *                      Added MPI2_SAS_PHYINFO_PHY_VACANT define.
109  *                      Added three new DiscoveryStatus bits for SAS IO Unit
110  *                      Page 0 and SAS Expander Page 0.
111  *                      Removed multiplexing information from SAS IO Unit pages.
112  *                      Added BootDeviceWaitTime field to SAS IO Unit Page 4.
113  *                      Removed Zone Address Resolved bit from PhyInfo and from
114  *                      Expander Page 0 Flags field.
115  *                      Added two new AccessStatus values to SAS Device Page 0
116  *                      for indicating routing problems. Added 3 reserved words
117  *                      to this page.
118  *  01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
119  *                      Inserted missing reserved field into structure for IOC
120  *                      Page 6.
121  *                      Added more pending task bits to RAID Volume Page 0
122  *                      VolumeStatusFlags defines.
123  *                      Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
124  *                      Added a new DiscoveryStatus bit for SAS IO Unit Page 0
125  *                      and SAS Expander Page 0 to flag a downstream initiator
126  *                      when in simplified routing mode.
127  *                      Removed SATA Init Failure defines for DiscoveryStatus
128  *                      fields of SAS IO Unit Page 0 and SAS Expander Page 0.
129  *                      Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
130  *                      Added PortGroups, DmaGroup, and ControlGroup fields to
131  *                      SAS Device Page 0.
132  *  05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
133  *                      Unit Page 6.
134  *                      Added expander reduced functionality data to SAS
135  *                      Expander Page 0.
136  *                      Added SAS PHY Page 2 and SAS PHY Page 3.
137  *  07-30-09  02.00.12  Added IO Unit Page 7.
138  *                      Added new device ids.
139  *                      Added SAS IO Unit Page 5.
140  *                      Added partial and slumber power management capable flags
141  *                      to SAS Device Page 0 Flags field.
142  *                      Added PhyInfo defines for power condition.
143  *                      Added Ethernet configuration pages.
144  *  10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
145  *                      Added SAS PHY Page 4 structure and defines.
146  *  02-10-10  02.00.14  Modified the comments for the configuration page
147  *                      structures that contain an array of data. The host
148  *                      should use the "count" field in the page data (e.g. the
149  *                      NumPhys field) to determine the number of valid elements
150  *                      in the array.
151  *                      Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
152  *                      Added PowerManagementCapabilities to IO Unit Page 7.
153  *                      Added PortWidthModGroup field to
154  *                      MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
155  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
156  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
157  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
158  *  05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
159  *                      define.
160  *                      Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
161  *                      Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
162  *  08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
163  *                      defines.
164  *  11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
165  *                      MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
166  *                      the Pinout field.
167  *                      Added BoardTemperature and BoardTemperatureUnits fields
168  *                      to MPI2_CONFIG_PAGE_IO_UNIT_7.
169  *                      Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
170  *                      and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
171  *  02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
172  *                      Added IO Unit Page 8, IO Unit Page 9,
173  *                      and IO Unit Page 10.
174  *                      Added SASNotifyPrimitiveMasks field to
175  *                      MPI2_CONFIG_PAGE_IOC_7.
176  *  03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
177  *  05-25-11  02.00.20  Cleaned up a few comments.
178  *  08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
179  *                      for PCIe link as obsolete.
180  *                      Added SpinupFlags field containing a Disable Spin-up bit
181  *                      to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
182  *                      Unit Page 4.
183  *  11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
184  *                      Added UEFIVersion field to BIOS Page 1 and defined new
185  *                      BiosOptions bits.
186  *                      Incorporating additions for MPI v2.5.
187  *  11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
188  *                      Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
189  *  12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
190  *                      obsolete for MPI v2.5 and later.
191  *                      Added some defines for 12G SAS speeds.
192  *  04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
193  *                      Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
194  *                      match the specification.
195  *  08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
196  *                      future use.
197  *  12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
198  *                      MPI2_CONFIG_PAGE_MAN_7.
199  *                      Added EnclosureLevel and ConnectorName fields to
200  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
201  *                      Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
202  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
203  *                      Added EnclosureLevel field to
204  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
205  *                      Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
206  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
207  *  --------------------------------------------------------------------------
208  */
209 
210 #ifndef MPI2_CNFG_H
211 #define MPI2_CNFG_H
212 
213 /*****************************************************************************
214 *   Configuration Page Header and defines
215 *****************************************************************************/
216 
217 /* Config Page Header */
218 typedef struct _MPI2_CONFIG_PAGE_HEADER
219 {
220     U8                 PageVersion;                /* 0x00 */
221     U8                 PageLength;                 /* 0x01 */
222     U8                 PageNumber;                 /* 0x02 */
223     U8                 PageType;                   /* 0x03 */
224 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
225   Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
226 
227 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
228 {
229    MPI2_CONFIG_PAGE_HEADER  Struct;
230    U8                       Bytes[4];
231    U16                      Word16[2];
232    U32                      Word32;
233 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
234   Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
235 
236 /* Extended Config Page Header */
237 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
238 {
239     U8                  PageVersion;                /* 0x00 */
240     U8                  Reserved1;                  /* 0x01 */
241     U8                  PageNumber;                 /* 0x02 */
242     U8                  PageType;                   /* 0x03 */
243     U16                 ExtPageLength;              /* 0x04 */
244     U8                  ExtPageType;                /* 0x06 */
245     U8                  Reserved2;                  /* 0x07 */
246 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
247   MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
248   Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
249 
250 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
251 {
252    MPI2_CONFIG_PAGE_HEADER          Struct;
253    MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
254    U8                               Bytes[8];
255    U16                              Word16[4];
256    U32                              Word32[2];
257 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
258   Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
259 
260 
261 /* PageType field values */
262 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
263 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
264 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
265 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
266 
267 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
268 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
269 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
270 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
271 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
272 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
273 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
274 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
275 
276 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
277 
278 
279 /* ExtPageType field values */
280 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
281 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
282 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
283 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
284 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
285 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
286 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
287 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
288 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
289 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
290 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
291 
292 
293 /*****************************************************************************
294 *   PageAddress defines
295 *****************************************************************************/
296 
297 /* RAID Volume PageAddress format */
298 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
299 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
300 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
301 
302 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
303 
304 
305 /* RAID Physical Disk PageAddress format */
306 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
307 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
308 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
309 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
310 
311 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
312 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
313 
314 
315 /* SAS Expander PageAddress format */
316 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
317 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
318 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
319 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
320 
321 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
322 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
323 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
324 
325 
326 /* SAS Device PageAddress format */
327 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
328 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
329 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
330 
331 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
332 
333 
334 /* SAS PHY PageAddress format */
335 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
336 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
337 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
338 
339 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
340 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
341 
342 
343 /* SAS Port PageAddress format */
344 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
345 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
346 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
347 
348 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
349 
350 
351 /* SAS Enclosure PageAddress format */
352 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
353 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
354 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
355 
356 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
357 
358 
359 /* RAID Configuration PageAddress format */
360 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
361 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
362 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
363 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
364 
365 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
366 
367 
368 /* Driver Persistent Mapping PageAddress format */
369 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
370 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
371 
372 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
373 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
374 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
375 
376 
377 /* Ethernet PageAddress format */
378 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
379 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
380 
381 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
382 
383 
384 
385 /****************************************************************************
386 *   Configuration messages
387 ****************************************************************************/
388 
389 /* Configuration Request Message */
390 typedef struct _MPI2_CONFIG_REQUEST
391 {
392     U8                      Action;                     /* 0x00 */
393     U8                      SGLFlags;                   /* 0x01 */
394     U8                      ChainOffset;                /* 0x02 */
395     U8                      Function;                   /* 0x03 */
396     U16                     ExtPageLength;              /* 0x04 */
397     U8                      ExtPageType;                /* 0x06 */
398     U8                      MsgFlags;                   /* 0x07 */
399     U8                      VP_ID;                      /* 0x08 */
400     U8                      VF_ID;                      /* 0x09 */
401     U16                     Reserved1;                  /* 0x0A */
402     U8                      Reserved2;                  /* 0x0C */
403     U8                      ProxyVF_ID;                 /* 0x0D */
404     U16                     Reserved4;                  /* 0x0E */
405     U32                     Reserved3;                  /* 0x10 */
406     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
407     U32                     PageAddress;                /* 0x18 */
408     MPI2_SGE_IO_UNION       PageBufferSGE;              /* 0x1C */
409 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
410   Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
411 
412 /* values for the Action field */
413 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
414 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
415 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
416 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
417 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
418 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
419 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
420 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
421 
422 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
423 
424 
425 /* Config Reply Message */
426 typedef struct _MPI2_CONFIG_REPLY
427 {
428     U8                      Action;                     /* 0x00 */
429     U8                      SGLFlags;                   /* 0x01 */
430     U8                      MsgLength;                  /* 0x02 */
431     U8                      Function;                   /* 0x03 */
432     U16                     ExtPageLength;              /* 0x04 */
433     U8                      ExtPageType;                /* 0x06 */
434     U8                      MsgFlags;                   /* 0x07 */
435     U8                      VP_ID;                      /* 0x08 */
436     U8                      VF_ID;                      /* 0x09 */
437     U16                     Reserved1;                  /* 0x0A */
438     U16                     Reserved2;                  /* 0x0C */
439     U16                     IOCStatus;                  /* 0x0E */
440     U32                     IOCLogInfo;                 /* 0x10 */
441     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
442 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
443   Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
444 
445 
446 
447 /*****************************************************************************
448 *
449 *               C o n f i g u r a t i o n    P a g e s
450 *
451 *****************************************************************************/
452 
453 /****************************************************************************
454 *   Manufacturing Config pages
455 ****************************************************************************/
456 
457 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
458 
459 /* MPI v2.0 SAS products */
460 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
461 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
462 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
463 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
464 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
465 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
466 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
467 
468 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
469 
470 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
471 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
472 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
473 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
474 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
475 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
476 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
477 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
478 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
479 
480 /* MPI v2.5 SAS products */
481 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
482 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
483 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
484 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
485 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
486 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
487 
488 
489 
490 
491 /* Manufacturing Page 0 */
492 
493 typedef struct _MPI2_CONFIG_PAGE_MAN_0
494 {
495     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
496     U8                      ChipName[16];               /* 0x04 */
497     U8                      ChipRevision[8];            /* 0x14 */
498     U8                      BoardName[16];              /* 0x1C */
499     U8                      BoardAssembly[16];          /* 0x2C */
500     U8                      BoardTracerNumber[16];      /* 0x3C */
501 } MPI2_CONFIG_PAGE_MAN_0,
502   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
503   Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
504 
505 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
506 
507 
508 /* Manufacturing Page 1 */
509 
510 typedef struct _MPI2_CONFIG_PAGE_MAN_1
511 {
512     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
513     U8                      VPD[256];                   /* 0x04 */
514 } MPI2_CONFIG_PAGE_MAN_1,
515   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
516   Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
517 
518 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
519 
520 
521 typedef struct _MPI2_CHIP_REVISION_ID
522 {
523     U16 DeviceID;                                       /* 0x00 */
524     U8  PCIRevisionID;                                  /* 0x02 */
525     U8  Reserved;                                       /* 0x03 */
526 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
527   Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
528 
529 
530 /* Manufacturing Page 2 */
531 
532 /*
533  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
534  * one and check Header.PageLength at runtime.
535  */
536 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
537 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
538 #endif
539 
540 typedef struct _MPI2_CONFIG_PAGE_MAN_2
541 {
542     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
543     MPI2_CHIP_REVISION_ID   ChipId;                     /* 0x04 */
544     U32                     HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
545 } MPI2_CONFIG_PAGE_MAN_2,
546   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
547   Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
548 
549 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
550 
551 
552 /* Manufacturing Page 3 */
553 
554 /*
555  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
556  * one and check Header.PageLength at runtime.
557  */
558 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
559 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
560 #endif
561 
562 typedef struct _MPI2_CONFIG_PAGE_MAN_3
563 {
564     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
565     MPI2_CHIP_REVISION_ID               ChipId;         /* 0x04 */
566     U32                                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
567 } MPI2_CONFIG_PAGE_MAN_3,
568   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
569   Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
570 
571 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
572 
573 
574 /* Manufacturing Page 4 */
575 
576 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
577 {
578     U8                          PowerSaveFlags;                 /* 0x00 */
579     U8                          InternalOperationsSleepTime;    /* 0x01 */
580     U8                          InternalOperationsRunTime;      /* 0x02 */
581     U8                          HostIdleTime;                   /* 0x03 */
582 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
583   MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
584   Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
585 
586 /* defines for the PowerSaveFlags field */
587 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
588 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
589 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
590 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
591 
592 typedef struct _MPI2_CONFIG_PAGE_MAN_4
593 {
594     MPI2_CONFIG_PAGE_HEADER             Header;                 /* 0x00 */
595     U32                                 Reserved1;              /* 0x04 */
596     U32                                 Flags;                  /* 0x08 */
597     U8                                  InquirySize;            /* 0x0C */
598     U8                                  Reserved2;              /* 0x0D */
599     U16                                 Reserved3;              /* 0x0E */
600     U8                                  InquiryData[56];        /* 0x10 */
601     U32                                 RAID0VolumeSettings;    /* 0x48 */
602     U32                                 RAID1EVolumeSettings;   /* 0x4C */
603     U32                                 RAID1VolumeSettings;    /* 0x50 */
604     U32                                 RAID10VolumeSettings;   /* 0x54 */
605     U32                                 Reserved4;              /* 0x58 */
606     U32                                 Reserved5;              /* 0x5C */
607     MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /* 0x60 */
608     U8                                  MaxOCEDisks;            /* 0x64 */
609     U8                                  ResyncRate;             /* 0x65 */
610     U16                                 DataScrubDuration;      /* 0x66 */
611     U8                                  MaxHotSpares;           /* 0x68 */
612     U8                                  MaxPhysDisksPerVol;     /* 0x69 */
613     U8                                  MaxPhysDisks;           /* 0x6A */
614     U8                                  MaxVolumes;             /* 0x6B */
615 } MPI2_CONFIG_PAGE_MAN_4,
616   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
617   Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
618 
619 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
620 
621 /* Manufacturing Page 4 Flags field */
622 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
623 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
624 
625 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
626 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
627 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
628 
629 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
630 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
631 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
632 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
633 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
634 
635 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
636 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
637 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
638 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
639 
640 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
641 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
642 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
643 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
644 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
645 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
646 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
647 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
648 
649 
650 /* Manufacturing Page 5 */
651 
652 /*
653  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
654  * one and check the value returned for NumPhys at runtime.
655  */
656 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
657 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
658 #endif
659 
660 typedef struct _MPI2_MANUFACTURING5_ENTRY
661 {
662     U64                                 WWID;           /* 0x00 */
663     U64                                 DeviceName;     /* 0x08 */
664 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
665   Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
666 
667 typedef struct _MPI2_CONFIG_PAGE_MAN_5
668 {
669     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
670     U8                                  NumPhys;        /* 0x04 */
671     U8                                  Reserved1;      /* 0x05 */
672     U16                                 Reserved2;      /* 0x06 */
673     U32                                 Reserved3;      /* 0x08 */
674     U32                                 Reserved4;      /* 0x0C */
675     MPI2_MANUFACTURING5_ENTRY           Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
676 } MPI2_CONFIG_PAGE_MAN_5,
677   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
678   Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
679 
680 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
681 
682 
683 /* Manufacturing Page 6 */
684 
685 typedef struct _MPI2_CONFIG_PAGE_MAN_6
686 {
687     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
688     U32                             ProductSpecificInfo;/* 0x04 */
689 } MPI2_CONFIG_PAGE_MAN_6,
690   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
691   Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
692 
693 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
694 
695 
696 /* Manufacturing Page 7 */
697 
698 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
699 {
700     U32                         Pinout;                 /* 0x00 */
701     U8                          Connector[16];          /* 0x04 */
702     U8                          Location;               /* 0x14 */
703     U8                          ReceptacleID;           /* 0x15 */
704     U16                         Slot;                   /* 0x16 */
705     U32                         Reserved2;              /* 0x18 */
706 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
707   Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
708 
709 /* defines for the Pinout field */
710 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
711 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
712 
713 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
714 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
715 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
716 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
717 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
718 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
719 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
720 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
721 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
722 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
723 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
724 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
725 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
726 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
727 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
728 
729 /* defines for the Location field */
730 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
731 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
732 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
733 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
734 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
735 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
736 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
737 
738 /*
739  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
740  * one and check the value returned for NumPhys at runtime.
741  */
742 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
743 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
744 #endif
745 
746 typedef struct _MPI2_CONFIG_PAGE_MAN_7
747 {
748     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
749     U32                             Reserved1;          /* 0x04 */
750     U32                             Reserved2;          /* 0x08 */
751     U32                             Flags;              /* 0x0C */
752     U8                              EnclosureName[16];  /* 0x10 */
753     U8                              NumPhys;            /* 0x20 */
754     U8                              Reserved3;          /* 0x21 */
755     U16                             Reserved4;          /* 0x22 */
756     MPI2_MANPAGE7_CONNECTOR_INFO    ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
757 } MPI2_CONFIG_PAGE_MAN_7,
758   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
759   Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
760 
761 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
762 
763 /* defines for the Flags field */
764 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
765 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
766 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
767 
768 
769 /*
770  * Generic structure to use for product-specific manufacturing pages
771  * (currently Manufacturing Page 8 through Manufacturing Page 31).
772  */
773 
774 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
775 {
776     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
777     U32                             ProductSpecificInfo;/* 0x04 */
778 } MPI2_CONFIG_PAGE_MAN_PS,
779   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
780   Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
781 
782 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
783 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
784 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
785 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
786 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
787 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
788 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
789 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
790 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
791 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
792 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
793 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
794 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
795 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
796 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
797 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
798 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
799 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
800 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
801 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
802 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
803 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
804 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
805 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
806 
807 
808 /****************************************************************************
809 *   IO Unit Config Pages
810 ****************************************************************************/
811 
812 /* IO Unit Page 0 */
813 
814 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
815 {
816     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
817     U64                     UniqueValue;                /* 0x04 */
818     MPI2_VERSION_UNION      NvdataVersionDefault;       /* 0x08 */
819     MPI2_VERSION_UNION      NvdataVersionPersistent;    /* 0x0A */
820 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
821   Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
822 
823 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
824 
825 
826 /* IO Unit Page 1 */
827 
828 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
829 {
830     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
831     U32                     Flags;                      /* 0x04 */
832 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
833   Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
834 
835 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
836 
837 /* IO Unit Page 1 Flags defines */
838 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
839 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
840 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
841 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
842 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
843 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
844 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
845 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
846 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
847 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
848 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
849 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
850 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
851 
852 
853 /* IO Unit Page 3 */
854 
855 /*
856  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
857  * one and check the value returned for GPIOCount at runtime.
858  */
859 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
860 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
861 #endif
862 
863 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
864 {
865     MPI2_CONFIG_PAGE_HEADER Header;                                   /* 0x00 */
866     U8                      GPIOCount;                                /* 0x04 */
867     U8                      Reserved1;                                /* 0x05 */
868     U16                     Reserved2;                                /* 0x06 */
869     U16                     GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
870 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
871   Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
872 
873 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
874 
875 /* defines for IO Unit Page 3 GPIOVal field */
876 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
877 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
878 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
879 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
880 
881 
882 /* IO Unit Page 5 */
883 
884 /*
885  * Upper layer code (drivers, utilities, etc.) should leave this define set to
886  * one and check the value returned for NumDmaEngines at runtime.
887  */
888 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
889 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
890 #endif
891 
892 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
893 {
894     MPI2_CONFIG_PAGE_HEADER Header;                                     /* 0x00 */
895     U64                     RaidAcceleratorBufferBaseAddress;           /* 0x04 */
896     U64                     RaidAcceleratorBufferSize;                  /* 0x0C */
897     U64                     RaidAcceleratorControlBaseAddress;          /* 0x14 */
898     U8                      RAControlSize;                              /* 0x1C */
899     U8                      NumDmaEngines;                              /* 0x1D */
900     U8                      RAMinControlSize;                           /* 0x1E */
901     U8                      RAMaxControlSize;                           /* 0x1F */
902     U32                     Reserved1;                                  /* 0x20 */
903     U32                     Reserved2;                                  /* 0x24 */
904     U32                     Reserved3;                                  /* 0x28 */
905     U32                     DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
906 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
907   Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
908 
909 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
910 
911 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
912 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
913 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
914 
915 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
916 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
917 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
918 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
919 
920 
921 /* IO Unit Page 6 */
922 
923 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
924 {
925     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
926     U16                     Flags;                                  /* 0x04 */
927     U8                      RAHostControlSize;                      /* 0x06 */
928     U8                      Reserved0;                              /* 0x07 */
929     U64                     RaidAcceleratorHostControlBaseAddress;  /* 0x08 */
930     U32                     Reserved1;                              /* 0x10 */
931     U32                     Reserved2;                              /* 0x14 */
932     U32                     Reserved3;                              /* 0x18 */
933 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
934   Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
935 
936 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
937 
938 /* defines for IO Unit Page 6 Flags field */
939 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
940 
941 
942 /* IO Unit Page 7 */
943 
944 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
945 {
946     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
947     U8                      CurrentPowerMode;                       /* 0x04 */ /* reserved in MPI 2.0 */
948     U8                      PreviousPowerMode;                      /* 0x05 */ /* reserved in MPI 2.0 */
949     U8                      PCIeWidth;                              /* 0x06 */
950     U8                      PCIeSpeed;                              /* 0x07 */
951     U32                     ProcessorState;                         /* 0x08 */
952     U32                     PowerManagementCapabilities;            /* 0x0C */
953     U16                     IOCTemperature;                         /* 0x10 */
954     U8                      IOCTemperatureUnits;                    /* 0x12 */
955     U8                      IOCSpeed;                               /* 0x13 */
956     U16                     BoardTemperature;                       /* 0x14 */
957     U8                      BoardTemperatureUnits;                  /* 0x16 */
958     U8                      Reserved3;                              /* 0x17 */
959     U32                     Reserved4;                              /* 0x18 */
960     U32                     Reserved5;                              /* 0x1C */
961     U32                     Reserved6;                              /* 0x20 */
962     U32                     Reserved7;                              /* 0x24 */
963 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
964   Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
965 
966 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x04)
967 
968 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
969 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
970 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
971 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
972 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
973 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
974 
975 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
976 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
977 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
978 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
979 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
980 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
981 
982 
983 /* defines for IO Unit Page 7 PCIeWidth field */
984 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
985 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
986 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
987 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
988 
989 /* defines for IO Unit Page 7 PCIeSpeed field */
990 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
991 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
992 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
993 
994 /* defines for IO Unit Page 7 ProcessorState field */
995 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
996 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
997 
998 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
999 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
1000 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
1001 
1002 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
1003 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
1004 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
1005 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
1006 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
1007 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
1008 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
1009 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
1010 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
1011 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
1012 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
1013 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
1014 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
1015 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
1016 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
1017 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
1018 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008) /* obsolete */
1019 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004) /* obsolete */
1020 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002) /* obsolete */
1021 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001) /* obsolete */
1022 
1023 /* obsolete names for the PowerManagementCapabilities bits (above) */
1024 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
1025 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
1026 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
1027 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /* obsolete */
1028 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /* obsolete */
1029 
1030 
1031 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
1032 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
1033 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
1034 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
1035 
1036 /* defines for IO Unit Page 7 IOCSpeed field */
1037 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
1038 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1039 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1040 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1041 
1042 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
1043 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1044 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1045 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1046 
1047 
1048 /* IO Unit Page 8 */
1049 
1050 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1051 
1052 typedef struct _MPI2_IOUNIT8_SENSOR
1053 {
1054     U16                     Flags;                                  /* 0x00 */
1055     U16                     Reserved1;                              /* 0x02 */
1056     U16                     Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
1057     U32                     Reserved2;                              /* 0x0C */
1058     U32                     Reserved3;                              /* 0x10 */
1059     U32                     Reserved4;                              /* 0x14 */
1060 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
1061   Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
1062 
1063 /* defines for IO Unit Page 8 Sensor Flags field */
1064 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1065 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1066 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1067 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1068 
1069 /*
1070  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1071  * one and check the value returned for NumSensors at runtime.
1072  */
1073 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1074 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1075 #endif
1076 
1077 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8
1078 {
1079     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1080     U32                     Reserved1;                              /* 0x04 */
1081     U32                     Reserved2;                              /* 0x08 */
1082     U8                      NumSensors;                             /* 0x0C */
1083     U8                      PollingInterval;                        /* 0x0D */
1084     U16                     Reserved3;                              /* 0x0E */
1085     MPI2_IOUNIT8_SENSOR     Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1086 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1087   Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
1088 
1089 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1090 
1091 
1092 /* IO Unit Page 9 */
1093 
1094 typedef struct _MPI2_IOUNIT9_SENSOR
1095 {
1096     U16                     CurrentTemperature;                     /* 0x00 */
1097     U16                     Reserved1;                              /* 0x02 */
1098     U8                      Flags;                                  /* 0x04 */
1099     U8                      Reserved2;                              /* 0x05 */
1100     U16                     Reserved3;                              /* 0x06 */
1101     U32                     Reserved4;                              /* 0x08 */
1102     U32                     Reserved5;                              /* 0x0C */
1103 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
1104   Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
1105 
1106 /* defines for IO Unit Page 9 Sensor Flags field */
1107 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1108 
1109 /*
1110  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1111  * one and check the value returned for NumSensors at runtime.
1112  */
1113 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1114 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1115 #endif
1116 
1117 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9
1118 {
1119     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1120     U32                     Reserved1;                              /* 0x04 */
1121     U32                     Reserved2;                              /* 0x08 */
1122     U8                      NumSensors;                             /* 0x0C */
1123     U8                      Reserved4;                              /* 0x0D */
1124     U16                     Reserved3;                              /* 0x0E */
1125     MPI2_IOUNIT9_SENSOR     Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1126 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1127   Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1128 
1129 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1130 
1131 
1132 /* IO Unit Page 10 */
1133 
1134 typedef struct _MPI2_IOUNIT10_FUNCTION
1135 {
1136     U8                      CreditPercent;      /* 0x00 */
1137     U8                      Reserved1;          /* 0x01 */
1138     U16                     Reserved2;          /* 0x02 */
1139 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1140   Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1141 
1142 /*
1143  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1144  * one and check the value returned for NumFunctions at runtime.
1145  */
1146 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1147 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1148 #endif
1149 
1150 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10
1151 {
1152     MPI2_CONFIG_PAGE_HEADER Header;                                         /* 0x00 */
1153     U8                      NumFunctions;                                   /* 0x04 */
1154     U8                      Reserved1;                                      /* 0x05 */
1155     U16                     Reserved2;                                      /* 0x06 */
1156     U32                     Reserved3;                                      /* 0x08 */
1157     U32                     Reserved4;                                      /* 0x0C */
1158     MPI2_IOUNIT10_FUNCTION  Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];   /* 0x10 */
1159 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1160   Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1161 
1162 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1163 
1164 
1165 
1166 /****************************************************************************
1167 *   IOC Config Pages
1168 ****************************************************************************/
1169 
1170 /* IOC Page 0 */
1171 
1172 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1173 {
1174     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1175     U32                     Reserved1;                  /* 0x04 */
1176     U32                     Reserved2;                  /* 0x08 */
1177     U16                     VendorID;                   /* 0x0C */
1178     U16                     DeviceID;                   /* 0x0E */
1179     U8                      RevisionID;                 /* 0x10 */
1180     U8                      Reserved3;                  /* 0x11 */
1181     U16                     Reserved4;                  /* 0x12 */
1182     U32                     ClassCode;                  /* 0x14 */
1183     U16                     SubsystemVendorID;          /* 0x18 */
1184     U16                     SubsystemID;                /* 0x1A */
1185 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1186   Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1187 
1188 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1189 
1190 
1191 /* IOC Page 1 */
1192 
1193 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1194 {
1195     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1196     U32                     Flags;                      /* 0x04 */
1197     U32                     CoalescingTimeout;          /* 0x08 */
1198     U8                      CoalescingDepth;            /* 0x0C */
1199     U8                      PCISlotNum;                 /* 0x0D */
1200     U8                      PCIBusNum;                  /* 0x0E */
1201     U8                      PCIDomainSegment;           /* 0x0F */
1202     U32                     Reserved1;                  /* 0x10 */
1203     U32                     Reserved2;                  /* 0x14 */
1204 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1205   Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1206 
1207 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1208 
1209 /* defines for IOC Page 1 Flags field */
1210 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1211 
1212 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1213 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1214 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1215 
1216 /* IOC Page 6 */
1217 
1218 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1219 {
1220     MPI2_CONFIG_PAGE_HEADER Header;                         /* 0x00 */
1221     U32                     CapabilitiesFlags;              /* 0x04 */
1222     U8                      MaxDrivesRAID0;                 /* 0x08 */
1223     U8                      MaxDrivesRAID1;                 /* 0x09 */
1224     U8                      MaxDrivesRAID1E;                /* 0x0A */
1225     U8                      MaxDrivesRAID10;                /* 0x0B */
1226     U8                      MinDrivesRAID0;                 /* 0x0C */
1227     U8                      MinDrivesRAID1;                 /* 0x0D */
1228     U8                      MinDrivesRAID1E;                /* 0x0E */
1229     U8                      MinDrivesRAID10;                /* 0x0F */
1230     U32                     Reserved1;                      /* 0x10 */
1231     U8                      MaxGlobalHotSpares;             /* 0x14 */
1232     U8                      MaxPhysDisks;                   /* 0x15 */
1233     U8                      MaxVolumes;                     /* 0x16 */
1234     U8                      MaxConfigs;                     /* 0x17 */
1235     U8                      MaxOCEDisks;                    /* 0x18 */
1236     U8                      Reserved2;                      /* 0x19 */
1237     U16                     Reserved3;                      /* 0x1A */
1238     U32                     SupportedStripeSizeMapRAID0;    /* 0x1C */
1239     U32                     SupportedStripeSizeMapRAID1E;   /* 0x20 */
1240     U32                     SupportedStripeSizeMapRAID10;   /* 0x24 */
1241     U32                     Reserved4;                      /* 0x28 */
1242     U32                     Reserved5;                      /* 0x2C */
1243     U16                     DefaultMetadataSize;            /* 0x30 */
1244     U16                     Reserved6;                      /* 0x32 */
1245     U16                     MaxBadBlockTableEntries;        /* 0x34 */
1246     U16                     Reserved7;                      /* 0x36 */
1247     U32                     IRNvsramVersion;                /* 0x38 */
1248 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1249   Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1250 
1251 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1252 
1253 /* defines for IOC Page 6 CapabilitiesFlags */
1254 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1255 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1256 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1257 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1258 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1259 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1260 
1261 
1262 /* IOC Page 7 */
1263 
1264 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1265 
1266 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1267 {
1268     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1269     U32                     Reserved1;                  /* 0x04 */
1270     U32                     EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1271     U16                     SASBroadcastPrimitiveMasks; /* 0x18 */
1272     U16                     SASNotifyPrimitiveMasks;    /* 0x1A */
1273     U32                     Reserved3;                  /* 0x1C */
1274 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1275   Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1276 
1277 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1278 
1279 
1280 /* IOC Page 8 */
1281 
1282 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1283 {
1284     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1285     U8                      NumDevsPerEnclosure;        /* 0x04 */
1286     U8                      Reserved1;                  /* 0x05 */
1287     U16                     Reserved2;                  /* 0x06 */
1288     U16                     MaxPersistentEntries;       /* 0x08 */
1289     U16                     MaxNumPhysicalMappedIDs;    /* 0x0A */
1290     U16                     Flags;                      /* 0x0C */
1291     U16                     Reserved3;                  /* 0x0E */
1292     U16                     IRVolumeMappingFlags;       /* 0x10 */
1293     U16                     Reserved4;                  /* 0x12 */
1294     U32                     Reserved5;                  /* 0x14 */
1295 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1296   Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1297 
1298 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1299 
1300 /* defines for IOC Page 8 Flags field */
1301 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1302 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1303 
1304 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1305 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1306 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1307 
1308 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1309 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1310 
1311 /* defines for IOC Page 8 IRVolumeMappingFlags */
1312 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1313 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1314 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1315 
1316 
1317 /****************************************************************************
1318 *   BIOS Config Pages
1319 ****************************************************************************/
1320 
1321 /* BIOS Page 1 */
1322 
1323 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1324 {
1325     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1326     U32                     BiosOptions;                /* 0x04 */
1327     U32                     IOCSettings;                /* 0x08 */
1328     U32                     Reserved1;                  /* 0x0C */
1329     U32                     DeviceSettings;             /* 0x10 */
1330     U16                     NumberOfDevices;            /* 0x14 */
1331     U16                     UEFIVersion;                /* 0x16 */
1332     U16                     IOTimeoutBlockDevicesNonRM; /* 0x18 */
1333     U16                     IOTimeoutSequential;        /* 0x1A */
1334     U16                     IOTimeoutOther;             /* 0x1C */
1335     U16                     IOTimeoutBlockDevicesRM;    /* 0x1E */
1336 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1337   Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1338 
1339 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x05)
1340 
1341 /* values for BIOS Page 1 BiosOptions field */
1342 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                  (0x000000F0)
1343 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                   (0x00000000)
1344 
1345 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION   (0x00000006)
1346 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII              (0x00000000)
1347 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII             (0x00000002)
1348 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII       (0x00000004)
1349 
1350 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                 (0x00000001)
1351 
1352 /* values for BIOS Page 1 IOCSettings field */
1353 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1354 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1355 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1356 
1357 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1358 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1359 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1360 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1361 
1362 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1363 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1364 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1365 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1366 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1367 
1368 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1369 
1370 /* values for BIOS Page 1 DeviceSettings field */
1371 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1372 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1373 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1374 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1375 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1376 
1377 /* defines for BIOS Page 1 UEFIVersion field */
1378 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1379 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1380 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1381 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1382 
1383 
1384 
1385 /* BIOS Page 2 */
1386 
1387 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1388 {
1389     U32         Reserved1;                              /* 0x00 */
1390     U32         Reserved2;                              /* 0x04 */
1391     U32         Reserved3;                              /* 0x08 */
1392     U32         Reserved4;                              /* 0x0C */
1393     U32         Reserved5;                              /* 0x10 */
1394     U32         Reserved6;                              /* 0x14 */
1395 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1396   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1397   Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1398 
1399 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1400 {
1401     U64         SASAddress;                             /* 0x00 */
1402     U8          LUN[8];                                 /* 0x08 */
1403     U32         Reserved1;                              /* 0x10 */
1404     U32         Reserved2;                              /* 0x14 */
1405 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1406   Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1407 
1408 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1409 {
1410     U64         EnclosureLogicalID;                     /* 0x00 */
1411     U32         Reserved1;                              /* 0x08 */
1412     U32         Reserved2;                              /* 0x0C */
1413     U16         SlotNumber;                             /* 0x10 */
1414     U16         Reserved3;                              /* 0x12 */
1415     U32         Reserved4;                              /* 0x14 */
1416 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1417   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1418   Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1419 
1420 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1421 {
1422     U64         DeviceName;                             /* 0x00 */
1423     U8          LUN[8];                                 /* 0x08 */
1424     U32         Reserved1;                              /* 0x10 */
1425     U32         Reserved2;                              /* 0x14 */
1426 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1427   Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1428 
1429 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1430 {
1431     MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1432     MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1433     MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1434     MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1435 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1436   Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1437 
1438 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1439 {
1440     MPI2_CONFIG_PAGE_HEADER     Header;                 /* 0x00 */
1441     U32                         Reserved1;              /* 0x04 */
1442     U32                         Reserved2;              /* 0x08 */
1443     U32                         Reserved3;              /* 0x0C */
1444     U32                         Reserved4;              /* 0x10 */
1445     U32                         Reserved5;              /* 0x14 */
1446     U32                         Reserved6;              /* 0x18 */
1447     U8                          ReqBootDeviceForm;      /* 0x1C */
1448     U8                          Reserved7;              /* 0x1D */
1449     U16                         Reserved8;              /* 0x1E */
1450     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /* 0x20 */
1451     U8                          ReqAltBootDeviceForm;   /* 0x38 */
1452     U8                          Reserved9;              /* 0x39 */
1453     U16                         Reserved10;             /* 0x3A */
1454     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /* 0x3C */
1455     U8                          CurrentBootDeviceForm;  /* 0x58 */
1456     U8                          Reserved11;             /* 0x59 */
1457     U16                         Reserved12;             /* 0x5A */
1458     MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /* 0x58 */
1459 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1460   Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1461 
1462 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1463 
1464 /* values for BIOS Page 2 BootDeviceForm fields */
1465 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1466 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1467 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1468 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1469 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1470 
1471 
1472 /* BIOS Page 3 */
1473 
1474 typedef struct _MPI2_ADAPTER_INFO
1475 {
1476     U8      PciBusNumber;                               /* 0x00 */
1477     U8      PciDeviceAndFunctionNumber;                 /* 0x01 */
1478     U16     AdapterFlags;                               /* 0x02 */
1479 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1480   Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1481 
1482 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1483 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1484 
1485 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1486 {
1487     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1488     U32                     GlobalFlags;                /* 0x04 */
1489     U32                     BiosVersion;                /* 0x08 */
1490     MPI2_ADAPTER_INFO       AdapterOrder[4];            /* 0x0C */
1491     U32                     Reserved1;                  /* 0x1C */
1492 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1493   Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1494 
1495 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x00)
1496 
1497 /* values for BIOS Page 3 GlobalFlags */
1498 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1499 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1500 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1501 
1502 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1503 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1504 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1505 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1506 
1507 
1508 /* BIOS Page 4 */
1509 
1510 /*
1511  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1512  * one and check the value returned for NumPhys at runtime.
1513  */
1514 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1515 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1516 #endif
1517 
1518 typedef struct _MPI2_BIOS4_ENTRY
1519 {
1520     U64                     ReassignmentWWID;       /* 0x00 */
1521     U64                     ReassignmentDeviceName; /* 0x08 */
1522 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1523   Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1524 
1525 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1526 {
1527     MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
1528     U8                      NumPhys;                            /* 0x04 */
1529     U8                      Reserved1;                          /* 0x05 */
1530     U16                     Reserved2;                          /* 0x06 */
1531     MPI2_BIOS4_ENTRY        Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /* 0x08 */
1532 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1533   Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1534 
1535 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1536 
1537 
1538 /****************************************************************************
1539 *   RAID Volume Config Pages
1540 ****************************************************************************/
1541 
1542 /* RAID Volume Page 0 */
1543 
1544 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1545 {
1546     U8                      RAIDSetNum;                 /* 0x00 */
1547     U8                      PhysDiskMap;                /* 0x01 */
1548     U8                      PhysDiskNum;                /* 0x02 */
1549     U8                      Reserved;                   /* 0x03 */
1550 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1551   Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1552 
1553 /* defines for the PhysDiskMap field */
1554 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1555 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1556 
1557 typedef struct _MPI2_RAIDVOL0_SETTINGS
1558 {
1559     U16                     Settings;                   /* 0x00 */
1560     U8                      HotSparePool;               /* 0x01 */
1561     U8                      Reserved;                   /* 0x02 */
1562 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1563   Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1564 
1565 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1566 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1567 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1568 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1569 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1570 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1571 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1572 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1573 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1574 
1575 /* RAID Volume Page 0 VolumeSettings defines */
1576 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1577 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1578 
1579 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1580 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1581 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1582 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1583 
1584 /*
1585  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1586  * one and check the value returned for NumPhysDisks at runtime.
1587  */
1588 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1589 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1590 #endif
1591 
1592 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1593 {
1594     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1595     U16                     DevHandle;                  /* 0x04 */
1596     U8                      VolumeState;                /* 0x06 */
1597     U8                      VolumeType;                 /* 0x07 */
1598     U32                     VolumeStatusFlags;          /* 0x08 */
1599     MPI2_RAIDVOL0_SETTINGS  VolumeSettings;             /* 0x0C */
1600     U64                     MaxLBA;                     /* 0x10 */
1601     U32                     StripeSize;                 /* 0x18 */
1602     U16                     BlockSize;                  /* 0x1C */
1603     U16                     Reserved1;                  /* 0x1E */
1604     U8                      SupportedPhysDisks;         /* 0x20 */
1605     U8                      ResyncRate;                 /* 0x21 */
1606     U16                     DataScrubDuration;          /* 0x22 */
1607     U8                      NumPhysDisks;               /* 0x24 */
1608     U8                      Reserved2;                  /* 0x25 */
1609     U8                      Reserved3;                  /* 0x26 */
1610     U8                      InactiveStatus;             /* 0x27 */
1611     MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1612 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1613   Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1614 
1615 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1616 
1617 /* values for RAID VolumeState */
1618 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1619 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1620 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1621 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1622 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1623 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1624 
1625 /* values for RAID VolumeType */
1626 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1627 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1628 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1629 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1630 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1631 
1632 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1633 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1634 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1635 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1636 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1637 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1638 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1639 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1640 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1641 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1642 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1643 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1644 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1645 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1646 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1647 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1648 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1649 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1650 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1651 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1652 
1653 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1654 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1655 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1656 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1657 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1658 
1659 /* values for RAID Volume Page 0 InactiveStatus field */
1660 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1661 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1662 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1663 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1664 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1665 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1666 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1667 
1668 
1669 /* RAID Volume Page 1 */
1670 
1671 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1672 {
1673     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1674     U16                     DevHandle;                  /* 0x04 */
1675     U16                     Reserved0;                  /* 0x06 */
1676     U8                      GUID[24];                   /* 0x08 */
1677     U8                      Name[16];                   /* 0x20 */
1678     U64                     WWID;                       /* 0x30 */
1679     U32                     Reserved1;                  /* 0x38 */
1680     U32                     Reserved2;                  /* 0x3C */
1681 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1682   Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1683 
1684 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1685 
1686 
1687 /****************************************************************************
1688 *   RAID Physical Disk Config Pages
1689 ****************************************************************************/
1690 
1691 /* RAID Physical Disk Page 0 */
1692 
1693 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1694 {
1695     U16                     Reserved1;                  /* 0x00 */
1696     U8                      HotSparePool;               /* 0x02 */
1697     U8                      Reserved2;                  /* 0x03 */
1698 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1699   Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1700 
1701 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1702 
1703 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1704 {
1705     U8                      VendorID[8];                /* 0x00 */
1706     U8                      ProductID[16];              /* 0x08 */
1707     U8                      ProductRevLevel[4];         /* 0x18 */
1708     U8                      SerialNum[32];              /* 0x1C */
1709 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1710   MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1711   Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1712 
1713 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1714 {
1715     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1716     U16                             DevHandle;                  /* 0x04 */
1717     U8                              Reserved1;                  /* 0x06 */
1718     U8                              PhysDiskNum;                /* 0x07 */
1719     MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;           /* 0x08 */
1720     U32                             Reserved2;                  /* 0x0C */
1721     MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;                /* 0x10 */
1722     U32                             Reserved3;                  /* 0x4C */
1723     U8                              PhysDiskState;              /* 0x50 */
1724     U8                              OfflineReason;              /* 0x51 */
1725     U8                              IncompatibleReason;         /* 0x52 */
1726     U8                              PhysDiskAttributes;         /* 0x53 */
1727     U32                             PhysDiskStatusFlags;        /* 0x54 */
1728     U64                             DeviceMaxLBA;               /* 0x58 */
1729     U64                             HostMaxLBA;                 /* 0x60 */
1730     U64                             CoercedMaxLBA;              /* 0x68 */
1731     U16                             BlockSize;                  /* 0x70 */
1732     U16                             Reserved5;                  /* 0x72 */
1733     U32                             Reserved6;                  /* 0x74 */
1734 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1735   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1736   Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1737 
1738 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1739 
1740 /* PhysDiskState defines */
1741 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1742 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1743 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1744 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1745 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1746 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1747 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1748 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1749 
1750 /* OfflineReason defines */
1751 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1752 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1753 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1754 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1755 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1756 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1757 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1758 
1759 /* IncompatibleReason defines */
1760 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1761 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1762 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1763 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1764 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1765 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1766 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1767 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1768 
1769 /* PhysDiskAttributes defines */
1770 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1771 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1772 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1773 
1774 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1775 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1776 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1777 
1778 /* PhysDiskStatusFlags defines */
1779 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1780 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1781 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1782 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1783 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1784 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1785 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1786 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1787 
1788 
1789 /* RAID Physical Disk Page 1 */
1790 
1791 /*
1792  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1793  * one and check the value returned for NumPhysDiskPaths at runtime.
1794  */
1795 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1796 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
1797 #endif
1798 
1799 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1800 {
1801     U16             DevHandle;          /* 0x00 */
1802     U16             Reserved1;          /* 0x02 */
1803     U64             WWID;               /* 0x04 */
1804     U64             OwnerWWID;          /* 0x0C */
1805     U8              OwnerIdentifier;    /* 0x14 */
1806     U8              Reserved2;          /* 0x15 */
1807     U16             Flags;              /* 0x16 */
1808 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1809   Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1810 
1811 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1812 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
1813 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
1814 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
1815 
1816 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1817 {
1818     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1819     U8                              NumPhysDiskPaths;           /* 0x04 */
1820     U8                              PhysDiskNum;                /* 0x05 */
1821     U16                             Reserved1;                  /* 0x06 */
1822     U32                             Reserved2;                  /* 0x08 */
1823     MPI2_RAIDPHYSDISK1_PATH         PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1824 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1825   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1826   Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1827 
1828 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
1829 
1830 
1831 /****************************************************************************
1832 *   values for fields used by several types of SAS Config Pages
1833 ****************************************************************************/
1834 
1835 /* values for NegotiatedLinkRates fields */
1836 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
1837 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
1838 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
1839 /* link rates used for Negotiated Physical and Logical Link Rate */
1840 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
1841 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
1842 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
1843 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
1844 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
1845 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
1846 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
1847 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
1848 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
1849 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
1850 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
1851 
1852 
1853 /* values for AttachedPhyInfo fields */
1854 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
1855 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
1856 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
1857 
1858 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
1859 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
1860 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
1861 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
1862 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
1863 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
1864 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
1865 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
1866 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
1867 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
1868 
1869 
1870 /* values for PhyInfo fields */
1871 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
1872 
1873 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
1874 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
1875 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
1876 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
1877 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
1878 
1879 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
1880 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
1881 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
1882 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
1883 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
1884 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
1885 
1886 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
1887 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
1888 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
1889 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
1890 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
1891 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
1892 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
1893 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
1894 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
1895 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
1896 
1897 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
1898 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
1899 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
1900 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
1901 
1902 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
1903 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
1904 
1905 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
1906 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
1907 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
1908 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
1909 
1910 
1911 /* values for SAS ProgrammedLinkRate fields */
1912 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
1913 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
1914 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
1915 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
1916 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
1917 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
1918 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
1919 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
1920 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
1921 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
1922 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
1923 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
1924 
1925 
1926 /* values for SAS HwLinkRate fields */
1927 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
1928 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
1929 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
1930 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
1931 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
1932 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
1933 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
1934 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
1935 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
1936 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
1937 
1938 
1939 
1940 /****************************************************************************
1941 *   SAS IO Unit Config Pages
1942 ****************************************************************************/
1943 
1944 /* SAS IO Unit Page 0 */
1945 
1946 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1947 {
1948     U8          Port;                   /* 0x00 */
1949     U8          PortFlags;              /* 0x01 */
1950     U8          PhyFlags;               /* 0x02 */
1951     U8          NegotiatedLinkRate;     /* 0x03 */
1952     U32         ControllerPhyDeviceInfo;/* 0x04 */
1953     U16         AttachedDevHandle;      /* 0x08 */
1954     U16         ControllerDevHandle;    /* 0x0A */
1955     U32         DiscoveryStatus;        /* 0x0C */
1956     U32         Reserved;               /* 0x10 */
1957 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1958   Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1959 
1960 /*
1961  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1962  * one and check the value returned for NumPhys at runtime.
1963  */
1964 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1965 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
1966 #endif
1967 
1968 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1969 {
1970     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1971     U32                                 Reserved1;                          /* 0x08 */
1972     U8                                  NumPhys;                            /* 0x0C */
1973     U8                                  Reserved2;                          /* 0x0D */
1974     U16                                 Reserved3;                          /* 0x0E */
1975     MPI2_SAS_IO_UNIT0_PHY_DATA          PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];  /* 0x10 */
1976 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1977   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1978   Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1979 
1980 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
1981 
1982 /* values for SAS IO Unit Page 0 PortFlags */
1983 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
1984 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
1985 
1986 /* values for SAS IO Unit Page 0 PhyFlags */
1987 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
1988 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
1989 
1990 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1991 
1992 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1993 
1994 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1995 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
1996 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
1997 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
1998 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
1999 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
2000 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
2001 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
2002 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2003 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
2004 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2005 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
2006 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2007 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2008 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2009 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2010 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2011 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2012 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2013 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2014 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2015 
2016 
2017 /* SAS IO Unit Page 1 */
2018 
2019 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
2020 {
2021     U8          Port;                       /* 0x00 */
2022     U8          PortFlags;                  /* 0x01 */
2023     U8          PhyFlags;                   /* 0x02 */
2024     U8          MaxMinLinkRate;             /* 0x03 */
2025     U32         ControllerPhyDeviceInfo;    /* 0x04 */
2026     U16         MaxTargetPortConnectTime;   /* 0x08 */
2027     U16         Reserved1;                  /* 0x0A */
2028 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2029   Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
2030 
2031 /*
2032  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2033  * one and check the value returned for NumPhys at runtime.
2034  */
2035 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2036 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2037 #endif
2038 
2039 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
2040 {
2041     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2042     U16                                 ControlFlags;                       /* 0x08 */
2043     U16                                 SASNarrowMaxQueueDepth;             /* 0x0A */
2044     U16                                 AdditionalControlFlags;             /* 0x0C */
2045     U16                                 SASWideMaxQueueDepth;               /* 0x0E */
2046     U8                                  NumPhys;                            /* 0x10 */
2047     U8                                  SATAMaxQDepth;                      /* 0x11 */
2048     U8                                  ReportDeviceMissingDelay;           /* 0x12 */
2049     U8                                  IODeviceMissingDelay;               /* 0x13 */
2050     MPI2_SAS_IO_UNIT1_PHY_DATA          PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /* 0x14 */
2051 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2052   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2053   Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
2054 
2055 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2056 
2057 /* values for SAS IO Unit Page 1 ControlFlags */
2058 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2059 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2060 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2061 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2062 
2063 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2064 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2065 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2066 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2067 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2068 
2069 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2070 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2071 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2072 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2073 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2074 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2075 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2076 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2077 
2078 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2079 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2080 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2081 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2082 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2083 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2084 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2085 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2086 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2087 
2088 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2089 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2090 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2091 
2092 /* values for SAS IO Unit Page 1 PortFlags */
2093 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2094 
2095 /* values for SAS IO Unit Page 1 PhyFlags */
2096 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2097 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2098 
2099 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
2100 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2101 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2102 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2103 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2104 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2105 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2106 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2107 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2108 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2109 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2110 
2111 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2112 
2113 
2114 /* SAS IO Unit Page 4 */
2115 
2116 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
2117 {
2118     U8          MaxTargetSpinup;            /* 0x00 */
2119     U8          SpinupDelay;                /* 0x01 */
2120     U8          SpinupFlags;                /* 0x02 */
2121     U8          Reserved1;                  /* 0x03 */
2122 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2123   Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2124 
2125 /* defines for SAS IO Unit Page 4 SpinupFlags */
2126 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2127 
2128 
2129 /*
2130  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2131  * one and check the value returned for NumPhys at runtime.
2132  */
2133 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2134 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2135 #endif
2136 
2137 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2138 {
2139     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
2140     MPI2_SAS_IOUNIT4_SPINUP_GROUP       SpinupGroupParameters[4];       /* 0x08 */
2141     U32                                 Reserved1;                      /* 0x18 */
2142     U32                                 Reserved2;                      /* 0x1C */
2143     U32                                 Reserved3;                      /* 0x20 */
2144     U8                                  BootDeviceWaitTime;             /* 0x24 */
2145     U8                                  Reserved4;                      /* 0x25 */
2146     U16                                 Reserved5;                      /* 0x26 */
2147     U8                                  NumPhys;                        /* 0x28 */
2148     U8                                  PEInitialSpinupDelay;           /* 0x29 */
2149     U8                                  PEReplyDelay;                   /* 0x2A */
2150     U8                                  Flags;                          /* 0x2B */
2151     U8                                  PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /* 0x2C */
2152 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2153   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2154   Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2155 
2156 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2157 
2158 /* defines for Flags field */
2159 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2160 
2161 /* defines for PHY field */
2162 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2163 
2164 
2165 /* SAS IO Unit Page 5 */
2166 
2167 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2168 {
2169     U8          ControlFlags;               /* 0x00 */
2170     U8          PortWidthModGroup;          /* 0x01 */
2171     U16         InactivityTimerExponent;    /* 0x02 */
2172     U8          SATAPartialTimeout;         /* 0x04 */
2173     U8          Reserved2;                  /* 0x05 */
2174     U8          SATASlumberTimeout;         /* 0x06 */
2175     U8          Reserved3;                  /* 0x07 */
2176     U8          SASPartialTimeout;          /* 0x08 */
2177     U8          Reserved4;                  /* 0x09 */
2178     U8          SASSlumberTimeout;          /* 0x0A */
2179     U8          Reserved5;                  /* 0x0B */
2180 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2181   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2182   Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2183 
2184 /* defines for ControlFlags field */
2185 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2186 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2187 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2188 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2189 
2190 /* defines for PortWidthModeGroup field */
2191 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2192 
2193 /* defines for InactivityTimerExponent field */
2194 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2195 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2196 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2197 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2198 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2199 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2200 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2201 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2202 
2203 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2204 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2205 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2206 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2207 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2208 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2209 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2210 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2211 
2212 /*
2213  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2214  * one and check the value returned for NumPhys at runtime.
2215  */
2216 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2217 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2218 #endif
2219 
2220 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
2221 {
2222     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2223     U8                                  NumPhys;                            /* 0x08 */
2224     U8                                  Reserved1;                          /* 0x09 */
2225     U16                                 Reserved2;                          /* 0x0A */
2226     U32                                 Reserved3;                          /* 0x0C */
2227     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS   SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];  /* 0x10 */
2228 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2229   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2230   Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2231 
2232 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2233 
2234 
2235 /* SAS IO Unit Page 6 */
2236 
2237 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2238 {
2239     U8          CurrentStatus;              /* 0x00 */
2240     U8          CurrentModulation;          /* 0x01 */
2241     U8          CurrentUtilization;         /* 0x02 */
2242     U8          Reserved1;                  /* 0x03 */
2243     U32         Reserved2;                  /* 0x04 */
2244 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2245   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2246   Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2247   MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2248 
2249 /* defines for CurrentStatus field */
2250 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2251 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2252 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2253 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2254 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2255 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2256 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2257 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2258 
2259 /* defines for CurrentModulation field */
2260 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2261 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2262 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2263 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2264 
2265 /*
2266  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2267  * one and check the value returned for NumGroups at runtime.
2268  */
2269 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2270 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2271 #endif
2272 
2273 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2274 {
2275     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2276     U32                                 Reserved1;                  /* 0x08 */
2277     U32                                 Reserved2;                  /* 0x0C */
2278     U8                                  NumGroups;                  /* 0x10 */
2279     U8                                  Reserved3;                  /* 0x11 */
2280     U16                                 Reserved4;                  /* 0x12 */
2281     MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2282         PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2283 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2284   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2285   Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2286 
2287 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2288 
2289 
2290 /* SAS IO Unit Page 7 */
2291 
2292 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2293 {
2294     U8          Flags;                      /* 0x00 */
2295     U8          Reserved1;                  /* 0x01 */
2296     U16         Reserved2;                  /* 0x02 */
2297     U8          Threshold75Pct;             /* 0x04 */
2298     U8          Threshold50Pct;             /* 0x05 */
2299     U8          Threshold25Pct;             /* 0x06 */
2300     U8          Reserved3;                  /* 0x07 */
2301 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2302   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2303   Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2304   MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2305 
2306 /* defines for Flags field */
2307 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2308 
2309 
2310 /*
2311  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2312  * one and check the value returned for NumGroups at runtime.
2313  */
2314 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2315 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2316 #endif
2317 
2318 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2319 {
2320     MPI2_CONFIG_EXTENDED_PAGE_HEADER            Header;             /* 0x00 */
2321     U8                                          SamplingInterval;   /* 0x08 */
2322     U8                                          WindowLength;       /* 0x09 */
2323     U16                                         Reserved1;          /* 0x0A */
2324     U32                                         Reserved2;          /* 0x0C */
2325     U32                                         Reserved3;          /* 0x10 */
2326     U8                                          NumGroups;          /* 0x14 */
2327     U8                                          Reserved4;          /* 0x15 */
2328     U16                                         Reserved5;          /* 0x16 */
2329     MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2330         PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2331 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2332   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2333   Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2334 
2335 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2336 
2337 
2338 /* SAS IO Unit Page 8 */
2339 
2340 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2341 {
2342     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
2343     U32                                 Reserved1;                      /* 0x08 */
2344     U32                                 PowerManagementCapabilities;    /* 0x0C */
2345     U8                                  TxRxSleepStatus;                /* 0x10 */ /* reserved in MPI 2.0 */
2346     U8                                  Reserved2;                      /* 0x11 */
2347     U16                                 Reserved3;                      /* 0x12 */
2348 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2349   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2350   Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2351 
2352 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2353 
2354 /* defines for PowerManagementCapabilities field */
2355 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2356 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2357 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2358 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2359 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2360 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2361 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2362 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2363 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2364 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2365 
2366 /* defines for TxRxSleepStatus field */
2367 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2368 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2369 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2370 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2371 
2372 
2373 
2374 /* SAS IO Unit Page 16 */
2375 
2376 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16
2377 {
2378     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2379     U64                                 TimeStamp;                          /* 0x08 */
2380     U32                                 Reserved1;                          /* 0x10 */
2381     U32                                 Reserved2;                          /* 0x14 */
2382     U32                                 FastPathPendedRequests;             /* 0x18 */
2383     U32                                 FastPathUnPendedRequests;           /* 0x1C */
2384     U32                                 FastPathHostRequestStarts;          /* 0x20 */
2385     U32                                 FastPathFirmwareRequestStarts;      /* 0x24 */
2386     U32                                 FastPathHostCompletions;            /* 0x28 */
2387     U32                                 FastPathFirmwareCompletions;        /* 0x2C */
2388     U32                                 NonFastPathRequestStarts;           /* 0x30 */
2389     U32                                 NonFastPathHostCompletions;         /* 0x30 */
2390 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2391   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2392   Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2393 
2394 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2395 
2396 
2397 /****************************************************************************
2398 *   SAS Expander Config Pages
2399 ****************************************************************************/
2400 
2401 /* SAS Expander Page 0 */
2402 
2403 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2404 {
2405     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2406     U8                                  PhysicalPort;               /* 0x08 */
2407     U8                                  ReportGenLength;            /* 0x09 */
2408     U16                                 EnclosureHandle;            /* 0x0A */
2409     U64                                 SASAddress;                 /* 0x0C */
2410     U32                                 DiscoveryStatus;            /* 0x14 */
2411     U16                                 DevHandle;                  /* 0x18 */
2412     U16                                 ParentDevHandle;            /* 0x1A */
2413     U16                                 ExpanderChangeCount;        /* 0x1C */
2414     U16                                 ExpanderRouteIndexes;       /* 0x1E */
2415     U8                                  NumPhys;                    /* 0x20 */
2416     U8                                  SASLevel;                   /* 0x21 */
2417     U16                                 Flags;                      /* 0x22 */
2418     U16                                 STPBusInactivityTimeLimit;  /* 0x24 */
2419     U16                                 STPMaxConnectTimeLimit;     /* 0x26 */
2420     U16                                 STP_SMP_NexusLossTime;      /* 0x28 */
2421     U16                                 MaxNumRoutedSasAddresses;   /* 0x2A */
2422     U64                                 ActiveZoneManagerSASAddress;/* 0x2C */
2423     U16                                 ZoneLockInactivityLimit;    /* 0x34 */
2424     U16                                 Reserved1;                  /* 0x36 */
2425     U8                                  TimeToReducedFunc;          /* 0x38 */
2426     U8                                  InitialTimeToReducedFunc;   /* 0x39 */
2427     U8                                  MaxReducedFuncTime;         /* 0x3A */
2428     U8                                  Reserved2;                  /* 0x3B */
2429 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2430   Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2431 
2432 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2433 
2434 /* values for SAS Expander Page 0 DiscoveryStatus field */
2435 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2436 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2437 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2438 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2439 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2440 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2441 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2442 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2443 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2444 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2445 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2446 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2447 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2448 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2449 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2450 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2451 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2452 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2453 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2454 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2455 
2456 /* values for SAS Expander Page 0 Flags field */
2457 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2458 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2459 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2460 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2461 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2462 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2463 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2464 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2465 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2466 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2467 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2468 
2469 
2470 /* SAS Expander Page 1 */
2471 
2472 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2473 {
2474     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2475     U8                                  PhysicalPort;               /* 0x08 */
2476     U8                                  Reserved1;                  /* 0x09 */
2477     U16                                 Reserved2;                  /* 0x0A */
2478     U8                                  NumPhys;                    /* 0x0C */
2479     U8                                  Phy;                        /* 0x0D */
2480     U16                                 NumTableEntriesProgrammed;  /* 0x0E */
2481     U8                                  ProgrammedLinkRate;         /* 0x10 */
2482     U8                                  HwLinkRate;                 /* 0x11 */
2483     U16                                 AttachedDevHandle;          /* 0x12 */
2484     U32                                 PhyInfo;                    /* 0x14 */
2485     U32                                 AttachedDeviceInfo;         /* 0x18 */
2486     U16                                 ExpanderDevHandle;          /* 0x1C */
2487     U8                                  ChangeCount;                /* 0x1E */
2488     U8                                  NegotiatedLinkRate;         /* 0x1F */
2489     U8                                  PhyIdentifier;              /* 0x20 */
2490     U8                                  AttachedPhyIdentifier;      /* 0x21 */
2491     U8                                  Reserved3;                  /* 0x22 */
2492     U8                                  DiscoveryInfo;              /* 0x23 */
2493     U32                                 AttachedPhyInfo;            /* 0x24 */
2494     U8                                  ZoneGroup;                  /* 0x28 */
2495     U8                                  SelfConfigStatus;           /* 0x29 */
2496     U16                                 Reserved4;                  /* 0x2A */
2497 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2498   Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2499 
2500 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2501 
2502 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2503 
2504 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2505 
2506 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2507 
2508 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2509 
2510 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2511 
2512 /* values for SAS Expander Page 1 DiscoveryInfo field */
2513 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2514 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2515 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2516 
2517 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2518 
2519 
2520 /****************************************************************************
2521 *   SAS Device Config Pages
2522 ****************************************************************************/
2523 
2524 /* SAS Device Page 0 */
2525 
2526 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2527 {
2528     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2529     U16                                 Slot;                   /* 0x08 */
2530     U16                                 EnclosureHandle;        /* 0x0A */
2531     U64                                 SASAddress;             /* 0x0C */
2532     U16                                 ParentDevHandle;        /* 0x14 */
2533     U8                                  PhyNum;                 /* 0x16 */
2534     U8                                  AccessStatus;           /* 0x17 */
2535     U16                                 DevHandle;              /* 0x18 */
2536     U8                                  AttachedPhyIdentifier;  /* 0x1A */
2537     U8                                  ZoneGroup;              /* 0x1B */
2538     U32                                 DeviceInfo;             /* 0x1C */
2539     U16                                 Flags;                  /* 0x20 */
2540     U8                                  PhysicalPort;           /* 0x22 */
2541     U8                                  MaxPortConnections;     /* 0x23 */
2542     U64                                 DeviceName;             /* 0x24 */
2543     U8                                  PortGroups;             /* 0x2C */
2544     U8                                  DmaGroup;               /* 0x2D */
2545     U8                                  ControlGroup;           /* 0x2E */
2546     U8                                  EnclosureLevel;         /* 0x2F */
2547     U8                                  ConnectorName[4];       /* 0x30 */
2548     U32                                 Reserved3;              /* 0x34 */
2549 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2550   Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2551 
2552 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
2553 
2554 /* values for SAS Device Page 0 AccessStatus field */
2555 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2556 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2557 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2558 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2559 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2560 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2561 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2562 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2563 /* specific values for SATA Init failures */
2564 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2565 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2566 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2567 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2568 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2569 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2570 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2571 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2572 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2573 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2574 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2575 
2576 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2577 
2578 /* values for SAS Device Page 0 Flags field */
2579 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2580 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2581 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2582 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2583 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2584 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2585 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2586 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2587 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2588 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2589 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2590 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2591 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2592 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
2593 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2594 
2595 
2596 /* SAS Device Page 1 */
2597 
2598 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2599 {
2600     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2601     U32                                 Reserved1;              /* 0x08 */
2602     U64                                 SASAddress;             /* 0x0C */
2603     U32                                 Reserved2;              /* 0x14 */
2604     U16                                 DevHandle;              /* 0x18 */
2605     U16                                 Reserved3;              /* 0x1A */
2606     U8                                  InitialRegDeviceFIS[20];/* 0x1C */
2607 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2608   Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2609 
2610 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2611 
2612 
2613 /****************************************************************************
2614 *   SAS PHY Config Pages
2615 ****************************************************************************/
2616 
2617 /* SAS PHY Page 0 */
2618 
2619 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2620 {
2621     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2622     U16                                 OwnerDevHandle;         /* 0x08 */
2623     U16                                 Reserved1;              /* 0x0A */
2624     U16                                 AttachedDevHandle;      /* 0x0C */
2625     U8                                  AttachedPhyIdentifier;  /* 0x0E */
2626     U8                                  Reserved2;              /* 0x0F */
2627     U32                                 AttachedPhyInfo;        /* 0x10 */
2628     U8                                  ProgrammedLinkRate;     /* 0x14 */
2629     U8                                  HwLinkRate;             /* 0x15 */
2630     U8                                  ChangeCount;            /* 0x16 */
2631     U8                                  Flags;                  /* 0x17 */
2632     U32                                 PhyInfo;                /* 0x18 */
2633     U8                                  NegotiatedLinkRate;     /* 0x1C */
2634     U8                                  Reserved3;              /* 0x1D */
2635     U16                                 Reserved4;              /* 0x1E */
2636 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2637   Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2638 
2639 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2640 
2641 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2642 
2643 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2644 
2645 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2646 
2647 /* values for SAS PHY Page 0 Flags field */
2648 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2649 
2650 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2651 
2652 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2653 
2654 
2655 /* SAS PHY Page 1 */
2656 
2657 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2658 {
2659     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2660     U32                                 Reserved1;                  /* 0x08 */
2661     U32                                 InvalidDwordCount;          /* 0x0C */
2662     U32                                 RunningDisparityErrorCount; /* 0x10 */
2663     U32                                 LossDwordSynchCount;        /* 0x14 */
2664     U32                                 PhyResetProblemCount;       /* 0x18 */
2665 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2666   Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2667 
2668 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
2669 
2670 
2671 /* SAS PHY Page 2 */
2672 
2673 typedef struct _MPI2_SASPHY2_PHY_EVENT
2674 {
2675     U8          PhyEventCode;       /* 0x00 */
2676     U8          Reserved1;          /* 0x01 */
2677     U16         Reserved2;          /* 0x02 */
2678     U32         PhyEventInfo;       /* 0x04 */
2679 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2680   Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2681 
2682 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2683 
2684 
2685 /*
2686  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2687  * one and check the value returned for NumPhyEvents at runtime.
2688  */
2689 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2690 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2691 #endif
2692 
2693 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2694 {
2695     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2696     U32                                 Reserved1;                  /* 0x08 */
2697     U8                                  NumPhyEvents;               /* 0x0C */
2698     U8                                  Reserved2;                  /* 0x0D */
2699     U16                                 Reserved3;                  /* 0x0E */
2700     MPI2_SASPHY2_PHY_EVENT              PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2701 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2702   Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2703 
2704 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
2705 
2706 
2707 /* SAS PHY Page 3 */
2708 
2709 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2710 {
2711     U8          PhyEventCode;       /* 0x00 */
2712     U8          Reserved1;          /* 0x01 */
2713     U16         Reserved2;          /* 0x02 */
2714     U8          CounterType;        /* 0x04 */
2715     U8          ThresholdWindow;    /* 0x05 */
2716     U8          TimeUnits;          /* 0x06 */
2717     U8          Reserved3;          /* 0x07 */
2718     U32         EventThreshold;     /* 0x08 */
2719     U16         ThresholdFlags;     /* 0x0C */
2720     U16         Reserved4;          /* 0x0E */
2721 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2722   Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2723 
2724 /* values for PhyEventCode field */
2725 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2726 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2727 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2728 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2729 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
2730 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
2731 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
2732 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
2733 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
2734 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
2735 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
2736 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
2737 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
2738 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
2739 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
2740 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
2741 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
2742 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
2743 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
2744 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
2745 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
2746 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
2747 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
2748 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
2749 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
2750 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
2751 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
2752 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
2753 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
2754 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
2755 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
2756 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
2757 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
2758 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
2759 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
2760 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
2761 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
2762 
2763 /* values for the CounterType field */
2764 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
2765 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
2766 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
2767 
2768 /* values for the TimeUnits field */
2769 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
2770 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
2771 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
2772 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
2773 
2774 /* values for the ThresholdFlags field */
2775 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
2776 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
2777 
2778 /*
2779  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2780  * one and check the value returned for NumPhyEvents at runtime.
2781  */
2782 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2783 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
2784 #endif
2785 
2786 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2787 {
2788     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2789     U32                                 Reserved1;                  /* 0x08 */
2790     U8                                  NumPhyEvents;               /* 0x0C */
2791     U8                                  Reserved2;                  /* 0x0D */
2792     U16                                 Reserved3;                  /* 0x0E */
2793     MPI2_SASPHY3_PHY_EVENT_CONFIG       PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2794 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2795   Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2796 
2797 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
2798 
2799 
2800 /* SAS PHY Page 4 */
2801 
2802 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2803 {
2804     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2805     U16                                 Reserved1;                  /* 0x08 */
2806     U8                                  Reserved2;                  /* 0x0A */
2807     U8                                  Flags;                      /* 0x0B */
2808     U8                                  InitialFrame[28];           /* 0x0C */
2809 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2810   Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2811 
2812 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
2813 
2814 /* values for the Flags field */
2815 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
2816 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
2817 
2818 
2819 
2820 
2821 /****************************************************************************
2822 *   SAS Port Config Pages
2823 ****************************************************************************/
2824 
2825 /* SAS Port Page 0 */
2826 
2827 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2828 {
2829     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2830     U8                                  PortNumber;                 /* 0x08 */
2831     U8                                  PhysicalPort;               /* 0x09 */
2832     U8                                  PortWidth;                  /* 0x0A */
2833     U8                                  PhysicalPortWidth;          /* 0x0B */
2834     U8                                  ZoneGroup;                  /* 0x0C */
2835     U8                                  Reserved1;                  /* 0x0D */
2836     U16                                 Reserved2;                  /* 0x0E */
2837     U64                                 SASAddress;                 /* 0x10 */
2838     U32                                 DeviceInfo;                 /* 0x18 */
2839     U32                                 Reserved3;                  /* 0x1C */
2840     U32                                 Reserved4;                  /* 0x20 */
2841 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2842   Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2843 
2844 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
2845 
2846 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2847 
2848 
2849 /****************************************************************************
2850 *   SAS Enclosure Config Pages
2851 ****************************************************************************/
2852 
2853 /* SAS Enclosure Page 0 */
2854 
2855 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2856 {
2857     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2858     U32                                 Reserved1;                  /* 0x08 */
2859     U64                                 EnclosureLogicalID;         /* 0x0C */
2860     U16                                 Flags;                      /* 0x14 */
2861     U16                                 EnclosureHandle;            /* 0x16 */
2862     U16                                 NumSlots;                   /* 0x18 */
2863     U16                                 StartSlot;                  /* 0x1A */
2864     U8                                  Reserved2;                  /* 0x1C */
2865     U8                                  EnclosureLevel;             /* 0x1D */
2866     U16                                 SEPDevHandle;               /* 0x1E */
2867     U32                                 Reserved3;                  /* 0x20 */
2868     U32                                 Reserved4;                  /* 0x24 */
2869 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2870   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2871   Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2872 
2873 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
2874 
2875 /* values for SAS Enclosure Page 0 Flags field */
2876 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
2877 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
2878 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
2879 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
2880 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
2881 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
2882 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
2883 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
2884 
2885 
2886 /****************************************************************************
2887 *   Log Config Page
2888 ****************************************************************************/
2889 
2890 /* Log Page 0 */
2891 
2892 /*
2893  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2894  * one and check the value returned for NumLogEntries at runtime.
2895  */
2896 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2897 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
2898 #endif
2899 
2900 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
2901 
2902 typedef struct _MPI2_LOG_0_ENTRY
2903 {
2904     U64         TimeStamp;                          /* 0x00 */
2905     U32         Reserved1;                          /* 0x08 */
2906     U16         LogSequence;                        /* 0x0C */
2907     U16         LogEntryQualifier;                  /* 0x0E */
2908     U8          VP_ID;                              /* 0x10 */
2909     U8          VF_ID;                              /* 0x11 */
2910     U16         Reserved2;                          /* 0x12 */
2911     U8          LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2912 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2913   Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2914 
2915 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2916 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
2917 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
2918 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
2919 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
2920 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
2921 
2922 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2923 {
2924     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2925     U32                                 Reserved1;                  /* 0x08 */
2926     U32                                 Reserved2;                  /* 0x0C */
2927     U16                                 NumLogEntries;              /* 0x10 */
2928     U16                                 Reserved3;                  /* 0x12 */
2929     MPI2_LOG_0_ENTRY                    LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2930 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2931   Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2932 
2933 #define MPI2_LOG_0_PAGEVERSION              (0x02)
2934 
2935 
2936 /****************************************************************************
2937 *   RAID Config Page
2938 ****************************************************************************/
2939 
2940 /* RAID Page 0 */
2941 
2942 /*
2943  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2944  * one and check the value returned for NumElements at runtime.
2945  */
2946 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2947 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
2948 #endif
2949 
2950 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2951 {
2952     U16                     ElementFlags;               /* 0x00 */
2953     U16                     VolDevHandle;               /* 0x02 */
2954     U8                      HotSparePool;               /* 0x04 */
2955     U8                      PhysDiskNum;                /* 0x05 */
2956     U16                     PhysDiskDevHandle;          /* 0x06 */
2957 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2958   MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2959   Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2960 
2961 /* values for the ElementFlags field */
2962 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
2963 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
2964 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
2965 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
2966 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
2967 
2968 
2969 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2970 {
2971     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2972     U8                                  NumHotSpares;               /* 0x08 */
2973     U8                                  NumPhysDisks;               /* 0x09 */
2974     U8                                  NumVolumes;                 /* 0x0A */
2975     U8                                  ConfigNum;                  /* 0x0B */
2976     U32                                 Flags;                      /* 0x0C */
2977     U8                                  ConfigGUID[24];             /* 0x10 */
2978     U32                                 Reserved1;                  /* 0x28 */
2979     U8                                  NumElements;                /* 0x2C */
2980     U8                                  Reserved2;                  /* 0x2D */
2981     U16                                 Reserved3;                  /* 0x2E */
2982     MPI2_RAIDCONFIG0_CONFIG_ELEMENT     ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2983 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2984   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2985   Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2986 
2987 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
2988 
2989 /* values for RAID Configuration Page 0 Flags field */
2990 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
2991 
2992 
2993 /****************************************************************************
2994 *   Driver Persistent Mapping Config Pages
2995 ****************************************************************************/
2996 
2997 /* Driver Persistent Mapping Page 0 */
2998 
2999 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
3000 {
3001     U64                                 PhysicalIdentifier;         /* 0x00 */
3002     U16                                 MappingInformation;         /* 0x08 */
3003     U16                                 DeviceIndex;                /* 0x0A */
3004     U32                                 PhysicalBitsMapping;        /* 0x0C */
3005     U32                                 Reserved1;                  /* 0x10 */
3006 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3007   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3008   Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
3009 
3010 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
3011 {
3012     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3013     MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;                      /* 0x08 */
3014 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3015   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3016   Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
3017 
3018 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3019 
3020 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
3021 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3022 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3023 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3024 
3025 
3026 /****************************************************************************
3027 *   Ethernet Config Pages
3028 ****************************************************************************/
3029 
3030 /* Ethernet Page 0 */
3031 
3032 /* IP address (union of IPv4 and IPv6) */
3033 typedef union _MPI2_ETHERNET_IP_ADDR
3034 {
3035     U32     IPv4Addr;
3036     U32     IPv6Addr[4];
3037 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
3038   Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
3039 
3040 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3041 
3042 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
3043 {
3044     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3045     U8                                  NumInterfaces;          /* 0x08 */
3046     U8                                  Reserved0;              /* 0x09 */
3047     U16                                 Reserved1;              /* 0x0A */
3048     U32                                 Status;                 /* 0x0C */
3049     U8                                  MediaState;             /* 0x10 */
3050     U8                                  Reserved2;              /* 0x11 */
3051     U16                                 Reserved3;              /* 0x12 */
3052     U8                                  MacAddress[6];          /* 0x14 */
3053     U8                                  Reserved4;              /* 0x1A */
3054     U8                                  Reserved5;              /* 0x1B */
3055     MPI2_ETHERNET_IP_ADDR               IpAddress;              /* 0x1C */
3056     MPI2_ETHERNET_IP_ADDR               SubnetMask;             /* 0x2C */
3057     MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;       /* 0x3C */
3058     MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;          /* 0x4C */
3059     MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;          /* 0x5C */
3060     MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;          /* 0x6C */
3061     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3062 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3063   Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
3064 
3065 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3066 
3067 /* values for Ethernet Page 0 Status field */
3068 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3069 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3070 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3071 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3072 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3073 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3074 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3075 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3076 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3077 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3078 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3079 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3080 
3081 /* values for Ethernet Page 0 MediaState field */
3082 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3083 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3084 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3085 
3086 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3087 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3088 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3089 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3090 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3091 
3092 
3093 /* Ethernet Page 1 */
3094 
3095 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
3096 {
3097     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3098     U32                                 Reserved0;              /* 0x08 */
3099     U32                                 Flags;                  /* 0x0C */
3100     U8                                  MediaState;             /* 0x10 */
3101     U8                                  Reserved1;              /* 0x11 */
3102     U16                                 Reserved2;              /* 0x12 */
3103     U8                                  MacAddress[6];          /* 0x14 */
3104     U8                                  Reserved3;              /* 0x1A */
3105     U8                                  Reserved4;              /* 0x1B */
3106     MPI2_ETHERNET_IP_ADDR               StaticIpAddress;        /* 0x1C */
3107     MPI2_ETHERNET_IP_ADDR               StaticSubnetMask;       /* 0x2C */
3108     MPI2_ETHERNET_IP_ADDR               StaticGatewayIpAddress; /* 0x3C */
3109     MPI2_ETHERNET_IP_ADDR               StaticDNS1IpAddress;    /* 0x4C */
3110     MPI2_ETHERNET_IP_ADDR               StaticDNS2IpAddress;    /* 0x5C */
3111     U32                                 Reserved5;              /* 0x6C */
3112     U32                                 Reserved6;              /* 0x70 */
3113     U32                                 Reserved7;              /* 0x74 */
3114     U32                                 Reserved8;              /* 0x78 */
3115     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3116 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3117   Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
3118 
3119 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3120 
3121 /* values for Ethernet Page 1 Flags field */
3122 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3123 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3124 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3125 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3126 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3127 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3128 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3129 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3130 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3131 
3132 /* values for Ethernet Page 1 MediaState field */
3133 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3134 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3135 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3136 
3137 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3138 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3139 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3140 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3141 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3142 
3143 
3144 /****************************************************************************
3145 *   Extended Manufacturing Config Pages
3146 ****************************************************************************/
3147 
3148 /*
3149  * Generic structure to use for product-specific extended manufacturing pages
3150  * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3151  * Page 60).
3152  */
3153 
3154 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
3155 {
3156     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3157     U32                                 ProductSpecificInfo;    /* 0x08 */
3158 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3159   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3160   Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3161 
3162 /* PageVersion should be provided by product-specific code */
3163 
3164 #endif
3165 
3166