1 /*- 2 * Copyright (c) 2013 LSI Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 2000-2013 LSI Corporation. 32 * 33 * 34 * Name: mpi2_ioc.h 35 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 36 * Creation Date: October 11, 2006 37 * 38 * mpi2_ioc.h Version: 02.00.24 39 * 40 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 41 * prefix are for use only on MPI v2.5 products, and must not be used 42 * with MPI v2.0 products. Unless otherwise noted, names beginning with 43 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 44 * 45 * Version History 46 * --------------- 47 * 48 * Date Version Description 49 * -------- -------- ------------------------------------------------------ 50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 51 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 52 * MaxTargets. 53 * Added TotalImageSize field to FWDownload Request. 54 * Added reserved words to FWUpload Request. 55 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 56 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 57 * request and replaced it with 58 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 59 * Replaced the MinReplyQueueDepth field of the IOCFacts 60 * reply with MaxReplyDescriptorPostQueueDepth. 61 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 62 * depth for the Reply Descriptor Post Queue. 63 * Added SASAddress field to Initiator Device Table 64 * Overflow Event data. 65 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 66 * for SAS Initiator Device Status Change Event data. 67 * Modified Reason Code defines for SAS Topology Change 68 * List Event data, including adding a bit for PHY Vacant 69 * status, and adding a mask for the Reason Code. 70 * Added define for 71 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 72 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 73 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 74 * the IOCFacts Reply. 75 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 76 * Moved MPI2_VERSION_UNION to mpi2.h. 77 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 78 * instead of enables, and added SASBroadcastPrimitiveMasks 79 * field. 80 * Added Log Entry Added Event and related structure. 81 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 82 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 83 * Added MaxVolumes and MaxPersistentEntries fields to 84 * IOCFacts reply. 85 * Added ProtocalFlags and IOCCapabilities fields to 86 * MPI2_FW_IMAGE_HEADER. 87 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 88 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 89 * a U16 (from a U32). 90 * Removed extra 's' from EventMasks name. 91 * 06-27-08 02.00.08 Fixed an offset in a comment. 92 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 93 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 94 * renamed MinReplyFrameSize to ReplyFrameSize. 95 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 96 * Added two new RAIDOperation values for Integrated RAID 97 * Operations Status Event data. 98 * Added four new IR Configuration Change List Event data 99 * ReasonCode values. 100 * Added two new ReasonCode defines for SAS Device Status 101 * Change Event data. 102 * Added three new DiscoveryStatus bits for the SAS 103 * Discovery event data. 104 * Added Multiplexing Status Change bit to the PhyStatus 105 * field of the SAS Topology Change List event data. 106 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 107 * BootFlags are now product-specific. 108 * Added defines for the indivdual signature bytes 109 * for MPI2_INIT_IMAGE_FOOTER. 110 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 111 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 112 * define. 113 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 114 * define. 115 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 116 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 117 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 118 * Added two new reason codes for SAS Device Status Change 119 * Event. 120 * Added new event: SAS PHY Counter. 121 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 122 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 123 * Added new product id family for 2208. 124 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 125 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 126 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 127 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 128 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 129 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 130 * Added Host Based Discovery Phy Event data. 131 * Added defines for ProductID Product field 132 * (MPI2_FW_HEADER_PID_). 133 * Modified values for SAS ProductID Family 134 * (MPI2_FW_HEADER_PID_FAMILY_). 135 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 136 * Added PowerManagementControl Request structures and 137 * defines. 138 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 139 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 140 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 141 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 142 * SASNotifyPrimitiveMasks field to 143 * MPI2_EVENT_NOTIFICATION_REQUEST. 144 * Added Temperature Threshold Event. 145 * Added Host Message Event. 146 * Added Send Host Message request and reply. 147 * 05-25-11 02.00.18 For Extended Image Header, added 148 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 149 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 150 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 151 * 08-24-11 02.00.19 Added PhysicalPort field to 152 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 153 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 154 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 155 * 03-29-12 02.00.21 Added a product specific range to event values. 156 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 157 * Added ElapsedSeconds field to 158 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 159 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 160 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 161 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 162 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 163 * Added Encrypted Hash Extended Image. 164 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 165 * -------------------------------------------------------------------------- 166 */ 167 168 #ifndef MPI2_IOC_H 169 #define MPI2_IOC_H 170 171 /***************************************************************************** 172 * 173 * IOC Messages 174 * 175 *****************************************************************************/ 176 177 /**************************************************************************** 178 * IOCInit message 179 ****************************************************************************/ 180 181 /* IOCInit Request message */ 182 typedef struct _MPI2_IOC_INIT_REQUEST 183 { 184 U8 WhoInit; /* 0x00 */ 185 U8 Reserved1; /* 0x01 */ 186 U8 ChainOffset; /* 0x02 */ 187 U8 Function; /* 0x03 */ 188 U16 Reserved2; /* 0x04 */ 189 U8 Reserved3; /* 0x06 */ 190 U8 MsgFlags; /* 0x07 */ 191 U8 VP_ID; /* 0x08 */ 192 U8 VF_ID; /* 0x09 */ 193 U16 Reserved4; /* 0x0A */ 194 U16 MsgVersion; /* 0x0C */ 195 U16 HeaderVersion; /* 0x0E */ 196 U32 Reserved5; /* 0x10 */ 197 U16 Reserved6; /* 0x14 */ 198 U8 Reserved7; /* 0x16 */ 199 U8 HostMSIxVectors; /* 0x17 */ 200 U16 Reserved8; /* 0x18 */ 201 U16 SystemRequestFrameSize; /* 0x1A */ 202 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 203 U16 ReplyFreeQueueDepth; /* 0x1E */ 204 U32 SenseBufferAddressHigh; /* 0x20 */ 205 U32 SystemReplyAddressHigh; /* 0x24 */ 206 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 207 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 208 U64 ReplyFreeQueueAddress; /* 0x38 */ 209 U64 TimeStamp; /* 0x40 */ 210 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 211 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 212 213 /* WhoInit values */ 214 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 215 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 216 #define MPI2_WHOINIT_ROM_BIOS (0x02) 217 #define MPI2_WHOINIT_PCI_PEER (0x03) 218 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 219 #define MPI2_WHOINIT_MANUFACTURER (0x05) 220 221 /* MsgFlags */ 222 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 223 224 /* MsgVersion */ 225 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 226 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 227 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 228 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 229 230 /* HeaderVersion */ 231 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 232 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 233 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 234 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 235 236 /* minimum depth for a Reply Descriptor Post Queue */ 237 #define MPI2_RDPQ_DEPTH_MIN (16) 238 239 /* Reply Descriptor Post Queue Array Entry */ 240 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY 241 { 242 U64 RDPQBaseAddress; /* 0x00 */ 243 U32 Reserved1; /* 0x08 */ 244 U32 Reserved2; /* 0x0C */ 245 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 246 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 247 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry; 248 249 /* IOCInit Reply message */ 250 typedef struct _MPI2_IOC_INIT_REPLY 251 { 252 U8 WhoInit; /* 0x00 */ 253 U8 Reserved1; /* 0x01 */ 254 U8 MsgLength; /* 0x02 */ 255 U8 Function; /* 0x03 */ 256 U16 Reserved2; /* 0x04 */ 257 U8 Reserved3; /* 0x06 */ 258 U8 MsgFlags; /* 0x07 */ 259 U8 VP_ID; /* 0x08 */ 260 U8 VF_ID; /* 0x09 */ 261 U16 Reserved4; /* 0x0A */ 262 U16 Reserved5; /* 0x0C */ 263 U16 IOCStatus; /* 0x0E */ 264 U32 IOCLogInfo; /* 0x10 */ 265 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 266 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 267 268 269 /**************************************************************************** 270 * IOCFacts message 271 ****************************************************************************/ 272 273 /* IOCFacts Request message */ 274 typedef struct _MPI2_IOC_FACTS_REQUEST 275 { 276 U16 Reserved1; /* 0x00 */ 277 U8 ChainOffset; /* 0x02 */ 278 U8 Function; /* 0x03 */ 279 U16 Reserved2; /* 0x04 */ 280 U8 Reserved3; /* 0x06 */ 281 U8 MsgFlags; /* 0x07 */ 282 U8 VP_ID; /* 0x08 */ 283 U8 VF_ID; /* 0x09 */ 284 U16 Reserved4; /* 0x0A */ 285 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 286 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 287 288 289 /* IOCFacts Reply message */ 290 typedef struct _MPI2_IOC_FACTS_REPLY 291 { 292 U16 MsgVersion; /* 0x00 */ 293 U8 MsgLength; /* 0x02 */ 294 U8 Function; /* 0x03 */ 295 U16 HeaderVersion; /* 0x04 */ 296 U8 IOCNumber; /* 0x06 */ 297 U8 MsgFlags; /* 0x07 */ 298 U8 VP_ID; /* 0x08 */ 299 U8 VF_ID; /* 0x09 */ 300 U16 Reserved1; /* 0x0A */ 301 U16 IOCExceptions; /* 0x0C */ 302 U16 IOCStatus; /* 0x0E */ 303 U32 IOCLogInfo; /* 0x10 */ 304 U8 MaxChainDepth; /* 0x14 */ 305 U8 WhoInit; /* 0x15 */ 306 U8 NumberOfPorts; /* 0x16 */ 307 U8 MaxMSIxVectors; /* 0x17 */ 308 U16 RequestCredit; /* 0x18 */ 309 U16 ProductID; /* 0x1A */ 310 U32 IOCCapabilities; /* 0x1C */ 311 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 312 U16 IOCRequestFrameSize; /* 0x24 */ 313 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ 314 U16 MaxInitiators; /* 0x28 */ 315 U16 MaxTargets; /* 0x2A */ 316 U16 MaxSasExpanders; /* 0x2C */ 317 U16 MaxEnclosures; /* 0x2E */ 318 U16 ProtocolFlags; /* 0x30 */ 319 U16 HighPriorityCredit; /* 0x32 */ 320 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 321 U8 ReplyFrameSize; /* 0x36 */ 322 U8 MaxVolumes; /* 0x37 */ 323 U16 MaxDevHandle; /* 0x38 */ 324 U16 MaxPersistentEntries; /* 0x3A */ 325 U16 MinDevHandle; /* 0x3C */ 326 U16 Reserved4; /* 0x3E */ 327 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 328 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 329 330 /* MsgVersion */ 331 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 332 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 333 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 334 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 335 336 /* HeaderVersion */ 337 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 338 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 339 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 340 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 341 342 /* IOCExceptions */ 343 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 344 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 345 346 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 347 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 348 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 349 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 350 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 351 352 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 353 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 354 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 355 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 356 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 357 358 /* defines for WhoInit field are after the IOCInit Request */ 359 360 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 361 362 /* IOCCapabilities */ 363 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 364 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 365 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 366 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 367 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 368 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 369 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 370 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 371 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 372 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 373 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 374 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 375 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 376 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 377 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 378 379 /* ProtocolFlags */ 380 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 381 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 382 383 384 /**************************************************************************** 385 * PortFacts message 386 ****************************************************************************/ 387 388 /* PortFacts Request message */ 389 typedef struct _MPI2_PORT_FACTS_REQUEST 390 { 391 U16 Reserved1; /* 0x00 */ 392 U8 ChainOffset; /* 0x02 */ 393 U8 Function; /* 0x03 */ 394 U16 Reserved2; /* 0x04 */ 395 U8 PortNumber; /* 0x06 */ 396 U8 MsgFlags; /* 0x07 */ 397 U8 VP_ID; /* 0x08 */ 398 U8 VF_ID; /* 0x09 */ 399 U16 Reserved3; /* 0x0A */ 400 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 401 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 402 403 /* PortFacts Reply message */ 404 typedef struct _MPI2_PORT_FACTS_REPLY 405 { 406 U16 Reserved1; /* 0x00 */ 407 U8 MsgLength; /* 0x02 */ 408 U8 Function; /* 0x03 */ 409 U16 Reserved2; /* 0x04 */ 410 U8 PortNumber; /* 0x06 */ 411 U8 MsgFlags; /* 0x07 */ 412 U8 VP_ID; /* 0x08 */ 413 U8 VF_ID; /* 0x09 */ 414 U16 Reserved3; /* 0x0A */ 415 U16 Reserved4; /* 0x0C */ 416 U16 IOCStatus; /* 0x0E */ 417 U32 IOCLogInfo; /* 0x10 */ 418 U8 Reserved5; /* 0x14 */ 419 U8 PortType; /* 0x15 */ 420 U16 Reserved6; /* 0x16 */ 421 U16 MaxPostedCmdBuffers; /* 0x18 */ 422 U16 Reserved7; /* 0x1A */ 423 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 424 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 425 426 /* PortType values */ 427 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 428 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 429 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 430 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 431 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 432 433 434 /**************************************************************************** 435 * PortEnable message 436 ****************************************************************************/ 437 438 /* PortEnable Request message */ 439 typedef struct _MPI2_PORT_ENABLE_REQUEST 440 { 441 U16 Reserved1; /* 0x00 */ 442 U8 ChainOffset; /* 0x02 */ 443 U8 Function; /* 0x03 */ 444 U8 Reserved2; /* 0x04 */ 445 U8 PortFlags; /* 0x05 */ 446 U8 Reserved3; /* 0x06 */ 447 U8 MsgFlags; /* 0x07 */ 448 U8 VP_ID; /* 0x08 */ 449 U8 VF_ID; /* 0x09 */ 450 U16 Reserved4; /* 0x0A */ 451 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 452 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 453 454 455 /* PortEnable Reply message */ 456 typedef struct _MPI2_PORT_ENABLE_REPLY 457 { 458 U16 Reserved1; /* 0x00 */ 459 U8 MsgLength; /* 0x02 */ 460 U8 Function; /* 0x03 */ 461 U8 Reserved2; /* 0x04 */ 462 U8 PortFlags; /* 0x05 */ 463 U8 Reserved3; /* 0x06 */ 464 U8 MsgFlags; /* 0x07 */ 465 U8 VP_ID; /* 0x08 */ 466 U8 VF_ID; /* 0x09 */ 467 U16 Reserved4; /* 0x0A */ 468 U16 Reserved5; /* 0x0C */ 469 U16 IOCStatus; /* 0x0E */ 470 U32 IOCLogInfo; /* 0x10 */ 471 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 472 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 473 474 475 /**************************************************************************** 476 * EventNotification message 477 ****************************************************************************/ 478 479 /* EventNotification Request message */ 480 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 481 482 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 483 { 484 U16 Reserved1; /* 0x00 */ 485 U8 ChainOffset; /* 0x02 */ 486 U8 Function; /* 0x03 */ 487 U16 Reserved2; /* 0x04 */ 488 U8 Reserved3; /* 0x06 */ 489 U8 MsgFlags; /* 0x07 */ 490 U8 VP_ID; /* 0x08 */ 491 U8 VF_ID; /* 0x09 */ 492 U16 Reserved4; /* 0x0A */ 493 U32 Reserved5; /* 0x0C */ 494 U32 Reserved6; /* 0x10 */ 495 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 496 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 497 U16 SASNotifyPrimitiveMasks; /* 0x26 */ 498 U32 Reserved8; /* 0x28 */ 499 } MPI2_EVENT_NOTIFICATION_REQUEST, 500 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 501 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 502 503 504 /* EventNotification Reply message */ 505 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 506 { 507 U16 EventDataLength; /* 0x00 */ 508 U8 MsgLength; /* 0x02 */ 509 U8 Function; /* 0x03 */ 510 U16 Reserved1; /* 0x04 */ 511 U8 AckRequired; /* 0x06 */ 512 U8 MsgFlags; /* 0x07 */ 513 U8 VP_ID; /* 0x08 */ 514 U8 VF_ID; /* 0x09 */ 515 U16 Reserved2; /* 0x0A */ 516 U16 Reserved3; /* 0x0C */ 517 U16 IOCStatus; /* 0x0E */ 518 U32 IOCLogInfo; /* 0x10 */ 519 U16 Event; /* 0x14 */ 520 U16 Reserved4; /* 0x16 */ 521 U32 EventContext; /* 0x18 */ 522 U32 EventData[1]; /* 0x1C */ 523 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 524 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 525 526 /* AckRequired */ 527 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 528 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 529 530 /* Event */ 531 #define MPI2_EVENT_LOG_DATA (0x0001) 532 #define MPI2_EVENT_STATE_CHANGE (0x0002) 533 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 534 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 535 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 536 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 537 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 538 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 539 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 540 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 541 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 542 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 543 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 544 #define MPI2_EVENT_IR_VOLUME (0x001E) 545 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 546 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 547 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 548 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 549 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 550 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 551 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 552 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 553 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 554 #define MPI2_EVENT_HOST_MESSAGE (0x0028) 555 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 556 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 557 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 558 559 560 /* Log Entry Added Event data */ 561 562 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 563 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 564 565 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 566 { 567 U64 TimeStamp; /* 0x00 */ 568 U32 Reserved1; /* 0x08 */ 569 U16 LogSequence; /* 0x0C */ 570 U16 LogEntryQualifier; /* 0x0E */ 571 U8 VP_ID; /* 0x10 */ 572 U8 VF_ID; /* 0x11 */ 573 U16 Reserved2; /* 0x12 */ 574 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 575 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 576 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 577 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 578 579 580 /* GPIO Interrupt Event data */ 581 582 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 583 { 584 U8 GPIONum; /* 0x00 */ 585 U8 Reserved1; /* 0x01 */ 586 U16 Reserved2; /* 0x02 */ 587 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 588 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 589 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 590 591 592 /* Temperature Threshold Event data */ 593 594 typedef struct _MPI2_EVENT_DATA_TEMPERATURE 595 { 596 U16 Status; /* 0x00 */ 597 U8 SensorNum; /* 0x02 */ 598 U8 Reserved1; /* 0x03 */ 599 U16 CurrentTemperature; /* 0x04 */ 600 U16 Reserved2; /* 0x06 */ 601 U32 Reserved3; /* 0x08 */ 602 U32 Reserved4; /* 0x0C */ 603 } MPI2_EVENT_DATA_TEMPERATURE, 604 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE, 605 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t; 606 607 /* Temperature Threshold Event data Status bits */ 608 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 609 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 610 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 611 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 612 613 614 /* Host Message Event data */ 615 616 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE 617 { 618 U8 SourceVF_ID; /* 0x00 */ 619 U8 Reserved1; /* 0x01 */ 620 U16 Reserved2; /* 0x02 */ 621 U32 Reserved3; /* 0x04 */ 622 U32 HostData[1]; /* 0x08 */ 623 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 624 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; 625 626 627 /* Power Performance Change Event */ 628 629 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE 630 { 631 U8 CurrentPowerMode; /* 0x00 */ 632 U8 PreviousPowerMode; /* 0x01 */ 633 U16 Reserved1; /* 0x02 */ 634 } MPI2_EVENT_DATA_POWER_PERF_CHANGE, 635 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 636 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t; 637 638 /* defines for CurrentPowerMode and PreviousPowerMode fields */ 639 #define MPI2_EVENT_PM_INIT_MASK (0xC0) 640 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 641 #define MPI2_EVENT_PM_INIT_HOST (0x40) 642 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 643 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 644 645 #define MPI2_EVENT_PM_MODE_MASK (0x07) 646 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 647 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 648 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 649 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 650 #define MPI2_EVENT_PM_MODE_STANDBY (0x06) 651 652 653 /* Hard Reset Received Event data */ 654 655 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 656 { 657 U8 Reserved1; /* 0x00 */ 658 U8 Port; /* 0x01 */ 659 U16 Reserved2; /* 0x02 */ 660 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 661 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 662 Mpi2EventDataHardResetReceived_t, 663 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 664 665 666 /* Task Set Full Event data */ 667 /* this event is obsolete */ 668 669 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 670 { 671 U16 DevHandle; /* 0x00 */ 672 U16 CurrentDepth; /* 0x02 */ 673 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 674 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 675 676 677 /* SAS Device Status Change Event data */ 678 679 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 680 { 681 U16 TaskTag; /* 0x00 */ 682 U8 ReasonCode; /* 0x02 */ 683 U8 PhysicalPort; /* 0x03 */ 684 U8 ASC; /* 0x04 */ 685 U8 ASCQ; /* 0x05 */ 686 U16 DevHandle; /* 0x06 */ 687 U32 Reserved2; /* 0x08 */ 688 U64 SASAddress; /* 0x0C */ 689 U8 LUN[8]; /* 0x14 */ 690 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 691 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 692 Mpi2EventDataSasDeviceStatusChange_t, 693 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 694 695 /* SAS Device Status Change Event data ReasonCode values */ 696 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 697 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 698 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 699 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 700 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 701 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 702 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 703 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 704 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 705 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 706 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 707 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 708 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 709 710 711 /* Integrated RAID Operation Status Event data */ 712 713 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 714 { 715 U16 VolDevHandle; /* 0x00 */ 716 U16 Reserved1; /* 0x02 */ 717 U8 RAIDOperation; /* 0x04 */ 718 U8 PercentComplete; /* 0x05 */ 719 U16 Reserved2; /* 0x06 */ 720 U32 ElapsedSeconds; /* 0x08 */ 721 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 722 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 723 Mpi2EventDataIrOperationStatus_t, 724 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 725 726 /* Integrated RAID Operation Status Event data RAIDOperation values */ 727 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 728 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 729 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 730 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 731 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 732 733 734 /* Integrated RAID Volume Event data */ 735 736 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 737 { 738 U16 VolDevHandle; /* 0x00 */ 739 U8 ReasonCode; /* 0x02 */ 740 U8 Reserved1; /* 0x03 */ 741 U32 NewValue; /* 0x04 */ 742 U32 PreviousValue; /* 0x08 */ 743 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 744 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 745 746 /* Integrated RAID Volume Event data ReasonCode values */ 747 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 748 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 749 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 750 751 752 /* Integrated RAID Physical Disk Event data */ 753 754 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 755 { 756 U16 Reserved1; /* 0x00 */ 757 U8 ReasonCode; /* 0x02 */ 758 U8 PhysDiskNum; /* 0x03 */ 759 U16 PhysDiskDevHandle; /* 0x04 */ 760 U16 Reserved2; /* 0x06 */ 761 U16 Slot; /* 0x08 */ 762 U16 EnclosureHandle; /* 0x0A */ 763 U32 NewValue; /* 0x0C */ 764 U32 PreviousValue; /* 0x10 */ 765 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 766 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 767 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 768 769 /* Integrated RAID Physical Disk Event data ReasonCode values */ 770 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 771 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 772 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 773 774 775 /* Integrated RAID Configuration Change List Event data */ 776 777 /* 778 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 779 * one and check NumElements at runtime. 780 */ 781 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 782 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 783 #endif 784 785 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 786 { 787 U16 ElementFlags; /* 0x00 */ 788 U16 VolDevHandle; /* 0x02 */ 789 U8 ReasonCode; /* 0x04 */ 790 U8 PhysDiskNum; /* 0x05 */ 791 U16 PhysDiskDevHandle; /* 0x06 */ 792 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 793 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 794 795 /* IR Configuration Change List Event data ElementFlags values */ 796 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 797 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 798 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 799 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 800 801 /* IR Configuration Change List Event data ReasonCode values */ 802 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 803 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 804 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 805 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 806 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 807 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 808 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 809 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 810 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 811 812 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 813 { 814 U8 NumElements; /* 0x00 */ 815 U8 Reserved1; /* 0x01 */ 816 U8 Reserved2; /* 0x02 */ 817 U8 ConfigNum; /* 0x03 */ 818 U32 Flags; /* 0x04 */ 819 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 820 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 821 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 822 Mpi2EventDataIrConfigChangeList_t, 823 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 824 825 /* IR Configuration Change List Event data Flags values */ 826 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 827 828 829 /* SAS Discovery Event data */ 830 831 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 832 { 833 U8 Flags; /* 0x00 */ 834 U8 ReasonCode; /* 0x01 */ 835 U8 PhysicalPort; /* 0x02 */ 836 U8 Reserved1; /* 0x03 */ 837 U32 DiscoveryStatus; /* 0x04 */ 838 } MPI2_EVENT_DATA_SAS_DISCOVERY, 839 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 840 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 841 842 /* SAS Discovery Event data Flags values */ 843 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 844 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 845 846 /* SAS Discovery Event data ReasonCode values */ 847 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 848 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 849 850 /* SAS Discovery Event data DiscoveryStatus values */ 851 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 852 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 853 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 854 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 855 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 856 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 857 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 858 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 859 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 860 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 861 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 862 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 863 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 864 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 865 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 866 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 867 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 868 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 869 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 870 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 871 872 873 /* SAS Broadcast Primitive Event data */ 874 875 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 876 { 877 U8 PhyNum; /* 0x00 */ 878 U8 Port; /* 0x01 */ 879 U8 PortWidth; /* 0x02 */ 880 U8 Primitive; /* 0x03 */ 881 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 882 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 883 Mpi2EventDataSasBroadcastPrimitive_t, 884 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 885 886 /* defines for the Primitive field */ 887 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 888 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 889 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 890 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 891 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 892 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 893 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 894 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 895 896 897 /* SAS Notify Primitive Event data */ 898 899 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE 900 { 901 U8 PhyNum; /* 0x00 */ 902 U8 Port; /* 0x01 */ 903 U8 Reserved1; /* 0x02 */ 904 U8 Primitive; /* 0x03 */ 905 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 906 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 907 Mpi2EventDataSasNotifyPrimitive_t, 908 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t; 909 910 /* defines for the Primitive field */ 911 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 912 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 913 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 914 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 915 916 917 /* SAS Initiator Device Status Change Event data */ 918 919 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 920 { 921 U8 ReasonCode; /* 0x00 */ 922 U8 PhysicalPort; /* 0x01 */ 923 U16 DevHandle; /* 0x02 */ 924 U64 SASAddress; /* 0x04 */ 925 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 926 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 927 Mpi2EventDataSasInitDevStatusChange_t, 928 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 929 930 /* SAS Initiator Device Status Change event ReasonCode values */ 931 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 932 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 933 934 935 /* SAS Initiator Device Table Overflow Event data */ 936 937 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 938 { 939 U16 MaxInit; /* 0x00 */ 940 U16 CurrentInit; /* 0x02 */ 941 U64 SASAddress; /* 0x04 */ 942 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 943 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 944 Mpi2EventDataSasInitTableOverflow_t, 945 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 946 947 948 /* SAS Topology Change List Event data */ 949 950 /* 951 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 952 * one and check NumEntries at runtime. 953 */ 954 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 955 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 956 #endif 957 958 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 959 { 960 U16 AttachedDevHandle; /* 0x00 */ 961 U8 LinkRate; /* 0x02 */ 962 U8 PhyStatus; /* 0x03 */ 963 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 964 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 965 966 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 967 { 968 U16 EnclosureHandle; /* 0x00 */ 969 U16 ExpanderDevHandle; /* 0x02 */ 970 U8 NumPhys; /* 0x04 */ 971 U8 Reserved1; /* 0x05 */ 972 U16 Reserved2; /* 0x06 */ 973 U8 NumEntries; /* 0x08 */ 974 U8 StartPhyNum; /* 0x09 */ 975 U8 ExpStatus; /* 0x0A */ 976 U8 PhysicalPort; /* 0x0B */ 977 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 978 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 979 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 980 Mpi2EventDataSasTopologyChangeList_t, 981 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 982 983 /* values for the ExpStatus field */ 984 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 985 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 986 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 987 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 988 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 989 990 /* defines for the LinkRate field */ 991 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 992 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 993 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 994 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 995 996 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 997 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 998 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 999 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1000 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1001 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1002 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1003 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1004 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1005 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1006 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1007 1008 /* values for the PhyStatus field */ 1009 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1010 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1011 /* values for the PhyStatus ReasonCode sub-field */ 1012 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1013 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1014 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1015 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1016 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1017 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1018 1019 1020 /* SAS Enclosure Device Status Change Event data */ 1021 1022 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 1023 { 1024 U16 EnclosureHandle; /* 0x00 */ 1025 U8 ReasonCode; /* 0x02 */ 1026 U8 PhysicalPort; /* 0x03 */ 1027 U64 EnclosureLogicalID; /* 0x04 */ 1028 U16 NumSlots; /* 0x0C */ 1029 U16 StartSlot; /* 0x0E */ 1030 U32 PhyBits; /* 0x10 */ 1031 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1032 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1033 Mpi2EventDataSasEnclDevStatusChange_t, 1034 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 1035 1036 /* SAS Enclosure Device Status Change event ReasonCode values */ 1037 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1038 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1039 1040 1041 /* SAS PHY Counter Event data */ 1042 1043 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 1044 { 1045 U64 TimeStamp; /* 0x00 */ 1046 U32 Reserved1; /* 0x08 */ 1047 U8 PhyEventCode; /* 0x0C */ 1048 U8 PhyNum; /* 0x0D */ 1049 U16 Reserved2; /* 0x0E */ 1050 U32 PhyEventInfo; /* 0x10 */ 1051 U8 CounterType; /* 0x14 */ 1052 U8 ThresholdWindow; /* 0x15 */ 1053 U8 TimeUnits; /* 0x16 */ 1054 U8 Reserved3; /* 0x17 */ 1055 U32 EventThreshold; /* 0x18 */ 1056 U16 ThresholdFlags; /* 0x1C */ 1057 U16 Reserved4; /* 0x1E */ 1058 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1059 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1060 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 1061 1062 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 1063 1064 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1065 1066 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1067 1068 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1069 1070 1071 /* SAS Quiesce Event data */ 1072 1073 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 1074 { 1075 U8 ReasonCode; /* 0x00 */ 1076 U8 Reserved1; /* 0x01 */ 1077 U16 Reserved2; /* 0x02 */ 1078 U32 Reserved3; /* 0x04 */ 1079 } MPI2_EVENT_DATA_SAS_QUIESCE, 1080 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1081 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 1082 1083 /* SAS Quiesce Event data ReasonCode values */ 1084 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1085 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1086 1087 1088 /* Host Based Discovery Phy Event data */ 1089 1090 typedef struct _MPI2_EVENT_HBD_PHY_SAS 1091 { 1092 U8 Flags; /* 0x00 */ 1093 U8 NegotiatedLinkRate; /* 0x01 */ 1094 U8 PhyNum; /* 0x02 */ 1095 U8 PhysicalPort; /* 0x03 */ 1096 U32 Reserved1; /* 0x04 */ 1097 U8 InitialFrame[28]; /* 0x08 */ 1098 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 1099 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 1100 1101 /* values for the Flags field */ 1102 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1103 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1104 1105 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 1106 1107 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 1108 { 1109 MPI2_EVENT_HBD_PHY_SAS Sas; 1110 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1111 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 1112 1113 typedef struct _MPI2_EVENT_DATA_HBD_PHY 1114 { 1115 U8 DescriptorType; /* 0x00 */ 1116 U8 Reserved1; /* 0x01 */ 1117 U16 Reserved2; /* 0x02 */ 1118 U32 Reserved3; /* 0x04 */ 1119 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1120 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1121 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1122 1123 /* values for the DescriptorType field */ 1124 #define MPI2_EVENT_HBD_DT_SAS (0x01) 1125 1126 1127 1128 /**************************************************************************** 1129 * EventAck message 1130 ****************************************************************************/ 1131 1132 /* EventAck Request message */ 1133 typedef struct _MPI2_EVENT_ACK_REQUEST 1134 { 1135 U16 Reserved1; /* 0x00 */ 1136 U8 ChainOffset; /* 0x02 */ 1137 U8 Function; /* 0x03 */ 1138 U16 Reserved2; /* 0x04 */ 1139 U8 Reserved3; /* 0x06 */ 1140 U8 MsgFlags; /* 0x07 */ 1141 U8 VP_ID; /* 0x08 */ 1142 U8 VF_ID; /* 0x09 */ 1143 U16 Reserved4; /* 0x0A */ 1144 U16 Event; /* 0x0C */ 1145 U16 Reserved5; /* 0x0E */ 1146 U32 EventContext; /* 0x10 */ 1147 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1148 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1149 1150 1151 /* EventAck Reply message */ 1152 typedef struct _MPI2_EVENT_ACK_REPLY 1153 { 1154 U16 Reserved1; /* 0x00 */ 1155 U8 MsgLength; /* 0x02 */ 1156 U8 Function; /* 0x03 */ 1157 U16 Reserved2; /* 0x04 */ 1158 U8 Reserved3; /* 0x06 */ 1159 U8 MsgFlags; /* 0x07 */ 1160 U8 VP_ID; /* 0x08 */ 1161 U8 VF_ID; /* 0x09 */ 1162 U16 Reserved4; /* 0x0A */ 1163 U16 Reserved5; /* 0x0C */ 1164 U16 IOCStatus; /* 0x0E */ 1165 U32 IOCLogInfo; /* 0x10 */ 1166 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1167 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1168 1169 1170 /**************************************************************************** 1171 * SendHostMessage message 1172 ****************************************************************************/ 1173 1174 /* SendHostMessage Request message */ 1175 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST 1176 { 1177 U16 HostDataLength; /* 0x00 */ 1178 U8 ChainOffset; /* 0x02 */ 1179 U8 Function; /* 0x03 */ 1180 U16 Reserved1; /* 0x04 */ 1181 U8 Reserved2; /* 0x06 */ 1182 U8 MsgFlags; /* 0x07 */ 1183 U8 VP_ID; /* 0x08 */ 1184 U8 VF_ID; /* 0x09 */ 1185 U16 Reserved3; /* 0x0A */ 1186 U8 Reserved4; /* 0x0C */ 1187 U8 DestVF_ID; /* 0x0D */ 1188 U16 Reserved5; /* 0x0E */ 1189 U32 Reserved6; /* 0x10 */ 1190 U32 Reserved7; /* 0x14 */ 1191 U32 Reserved8; /* 0x18 */ 1192 U32 Reserved9; /* 0x1C */ 1193 U32 Reserved10; /* 0x20 */ 1194 U32 HostData[1]; /* 0x24 */ 1195 } MPI2_SEND_HOST_MESSAGE_REQUEST, 1196 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1197 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t; 1198 1199 1200 /* SendHostMessage Reply message */ 1201 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY 1202 { 1203 U16 HostDataLength; /* 0x00 */ 1204 U8 MsgLength; /* 0x02 */ 1205 U8 Function; /* 0x03 */ 1206 U16 Reserved1; /* 0x04 */ 1207 U8 Reserved2; /* 0x06 */ 1208 U8 MsgFlags; /* 0x07 */ 1209 U8 VP_ID; /* 0x08 */ 1210 U8 VF_ID; /* 0x09 */ 1211 U16 Reserved3; /* 0x0A */ 1212 U16 Reserved4; /* 0x0C */ 1213 U16 IOCStatus; /* 0x0E */ 1214 U32 IOCLogInfo; /* 0x10 */ 1215 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1216 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t; 1217 1218 1219 /**************************************************************************** 1220 * FWDownload message 1221 ****************************************************************************/ 1222 1223 /* MPI v2.0 FWDownload Request message */ 1224 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1225 { 1226 U8 ImageType; /* 0x00 */ 1227 U8 Reserved1; /* 0x01 */ 1228 U8 ChainOffset; /* 0x02 */ 1229 U8 Function; /* 0x03 */ 1230 U16 Reserved2; /* 0x04 */ 1231 U8 Reserved3; /* 0x06 */ 1232 U8 MsgFlags; /* 0x07 */ 1233 U8 VP_ID; /* 0x08 */ 1234 U8 VF_ID; /* 0x09 */ 1235 U16 Reserved4; /* 0x0A */ 1236 U32 TotalImageSize; /* 0x0C */ 1237 U32 Reserved5; /* 0x10 */ 1238 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1239 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1240 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1241 1242 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1243 1244 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1245 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1246 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1247 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1248 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1249 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1250 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1251 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1252 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ 1253 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1254 1255 /* MPI v2.0 FWDownload TransactionContext Element */ 1256 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1257 { 1258 U8 Reserved1; /* 0x00 */ 1259 U8 ContextSize; /* 0x01 */ 1260 U8 DetailsLength; /* 0x02 */ 1261 U8 Flags; /* 0x03 */ 1262 U32 Reserved2; /* 0x04 */ 1263 U32 ImageOffset; /* 0x08 */ 1264 U32 ImageSize; /* 0x0C */ 1265 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1266 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1267 1268 1269 /* MPI v2.5 FWDownload Request message */ 1270 typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1271 { 1272 U8 ImageType; /* 0x00 */ 1273 U8 Reserved1; /* 0x01 */ 1274 U8 ChainOffset; /* 0x02 */ 1275 U8 Function; /* 0x03 */ 1276 U16 Reserved2; /* 0x04 */ 1277 U8 Reserved3; /* 0x06 */ 1278 U8 MsgFlags; /* 0x07 */ 1279 U8 VP_ID; /* 0x08 */ 1280 U8 VF_ID; /* 0x09 */ 1281 U16 Reserved4; /* 0x0A */ 1282 U32 TotalImageSize; /* 0x0C */ 1283 U32 Reserved5; /* 0x10 */ 1284 U32 Reserved6; /* 0x14 */ 1285 U32 ImageOffset; /* 0x18 */ 1286 U32 ImageSize; /* 0x1C */ 1287 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1288 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1289 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1290 1291 1292 /* FWDownload Reply message */ 1293 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1294 { 1295 U8 ImageType; /* 0x00 */ 1296 U8 Reserved1; /* 0x01 */ 1297 U8 MsgLength; /* 0x02 */ 1298 U8 Function; /* 0x03 */ 1299 U16 Reserved2; /* 0x04 */ 1300 U8 Reserved3; /* 0x06 */ 1301 U8 MsgFlags; /* 0x07 */ 1302 U8 VP_ID; /* 0x08 */ 1303 U8 VF_ID; /* 0x09 */ 1304 U16 Reserved4; /* 0x0A */ 1305 U16 Reserved5; /* 0x0C */ 1306 U16 IOCStatus; /* 0x0E */ 1307 U32 IOCLogInfo; /* 0x10 */ 1308 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1309 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1310 1311 1312 /**************************************************************************** 1313 * FWUpload message 1314 ****************************************************************************/ 1315 1316 /* MPI v2.0 FWUpload Request message */ 1317 typedef struct _MPI2_FW_UPLOAD_REQUEST 1318 { 1319 U8 ImageType; /* 0x00 */ 1320 U8 Reserved1; /* 0x01 */ 1321 U8 ChainOffset; /* 0x02 */ 1322 U8 Function; /* 0x03 */ 1323 U16 Reserved2; /* 0x04 */ 1324 U8 Reserved3; /* 0x06 */ 1325 U8 MsgFlags; /* 0x07 */ 1326 U8 VP_ID; /* 0x08 */ 1327 U8 VF_ID; /* 0x09 */ 1328 U16 Reserved4; /* 0x0A */ 1329 U32 Reserved5; /* 0x0C */ 1330 U32 Reserved6; /* 0x10 */ 1331 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1332 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1333 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1334 1335 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1336 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1337 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1338 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1339 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1340 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1341 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1342 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1343 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1344 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1345 1346 /* MPI v2.0 FWUpload TransactionContext Element */ 1347 typedef struct _MPI2_FW_UPLOAD_TCSGE 1348 { 1349 U8 Reserved1; /* 0x00 */ 1350 U8 ContextSize; /* 0x01 */ 1351 U8 DetailsLength; /* 0x02 */ 1352 U8 Flags; /* 0x03 */ 1353 U32 Reserved2; /* 0x04 */ 1354 U32 ImageOffset; /* 0x08 */ 1355 U32 ImageSize; /* 0x0C */ 1356 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1357 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1358 1359 1360 /* MPI v2.5 FWUpload Request message */ 1361 typedef struct _MPI25_FW_UPLOAD_REQUEST 1362 { 1363 U8 ImageType; /* 0x00 */ 1364 U8 Reserved1; /* 0x01 */ 1365 U8 ChainOffset; /* 0x02 */ 1366 U8 Function; /* 0x03 */ 1367 U16 Reserved2; /* 0x04 */ 1368 U8 Reserved3; /* 0x06 */ 1369 U8 MsgFlags; /* 0x07 */ 1370 U8 VP_ID; /* 0x08 */ 1371 U8 VF_ID; /* 0x09 */ 1372 U16 Reserved4; /* 0x0A */ 1373 U32 Reserved5; /* 0x0C */ 1374 U32 Reserved6; /* 0x10 */ 1375 U32 Reserved7; /* 0x14 */ 1376 U32 ImageOffset; /* 0x18 */ 1377 U32 ImageSize; /* 0x1C */ 1378 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1379 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1380 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1381 1382 1383 /* FWUpload Reply message */ 1384 typedef struct _MPI2_FW_UPLOAD_REPLY 1385 { 1386 U8 ImageType; /* 0x00 */ 1387 U8 Reserved1; /* 0x01 */ 1388 U8 MsgLength; /* 0x02 */ 1389 U8 Function; /* 0x03 */ 1390 U16 Reserved2; /* 0x04 */ 1391 U8 Reserved3; /* 0x06 */ 1392 U8 MsgFlags; /* 0x07 */ 1393 U8 VP_ID; /* 0x08 */ 1394 U8 VF_ID; /* 0x09 */ 1395 U16 Reserved4; /* 0x0A */ 1396 U16 Reserved5; /* 0x0C */ 1397 U16 IOCStatus; /* 0x0E */ 1398 U32 IOCLogInfo; /* 0x10 */ 1399 U32 ActualImageSize; /* 0x14 */ 1400 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1401 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1402 1403 1404 /* FW Image Header */ 1405 typedef struct _MPI2_FW_IMAGE_HEADER 1406 { 1407 U32 Signature; /* 0x00 */ 1408 U32 Signature0; /* 0x04 */ 1409 U32 Signature1; /* 0x08 */ 1410 U32 Signature2; /* 0x0C */ 1411 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1412 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1413 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1414 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1415 U16 VendorID; /* 0x20 */ 1416 U16 ProductID; /* 0x22 */ 1417 U16 ProtocolFlags; /* 0x24 */ 1418 U16 Reserved26; /* 0x26 */ 1419 U32 IOCCapabilities; /* 0x28 */ 1420 U32 ImageSize; /* 0x2C */ 1421 U32 NextImageHeaderOffset; /* 0x30 */ 1422 U32 Checksum; /* 0x34 */ 1423 U32 Reserved38; /* 0x38 */ 1424 U32 Reserved3C; /* 0x3C */ 1425 U32 Reserved40; /* 0x40 */ 1426 U32 Reserved44; /* 0x44 */ 1427 U32 Reserved48; /* 0x48 */ 1428 U32 Reserved4C; /* 0x4C */ 1429 U32 Reserved50; /* 0x50 */ 1430 U32 Reserved54; /* 0x54 */ 1431 U32 Reserved58; /* 0x58 */ 1432 U32 Reserved5C; /* 0x5C */ 1433 U32 Reserved60; /* 0x60 */ 1434 U32 FirmwareVersionNameWhat; /* 0x64 */ 1435 U8 FirmwareVersionName[32]; /* 0x68 */ 1436 U32 VendorNameWhat; /* 0x88 */ 1437 U8 VendorName[32]; /* 0x8C */ 1438 U32 PackageNameWhat; /* 0x88 */ 1439 U8 PackageName[32]; /* 0x8C */ 1440 U32 ReservedD0; /* 0xD0 */ 1441 U32 ReservedD4; /* 0xD4 */ 1442 U32 ReservedD8; /* 0xD8 */ 1443 U32 ReservedDC; /* 0xDC */ 1444 U32 ReservedE0; /* 0xE0 */ 1445 U32 ReservedE4; /* 0xE4 */ 1446 U32 ReservedE8; /* 0xE8 */ 1447 U32 ReservedEC; /* 0xEC */ 1448 U32 ReservedF0; /* 0xF0 */ 1449 U32 ReservedF4; /* 0xF4 */ 1450 U32 ReservedF8; /* 0xF8 */ 1451 U32 ReservedFC; /* 0xFC */ 1452 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1453 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1454 1455 /* Signature field */ 1456 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1457 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1458 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1459 1460 /* Signature0 field */ 1461 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1462 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1463 1464 /* Signature1 field */ 1465 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1466 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1467 1468 /* Signature2 field */ 1469 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1470 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1471 1472 1473 /* defines for using the ProductID field */ 1474 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1475 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1476 1477 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1478 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1479 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1480 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1481 1482 1483 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1484 /* SAS ProductID Family bits */ 1485 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1486 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1487 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1488 1489 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1490 1491 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1492 1493 1494 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1495 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1496 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1497 1498 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1499 1500 #define MPI2_FW_HEADER_SIZE (0x100) 1501 1502 1503 /* Extended Image Header */ 1504 typedef struct _MPI2_EXT_IMAGE_HEADER 1505 1506 { 1507 U8 ImageType; /* 0x00 */ 1508 U8 Reserved1; /* 0x01 */ 1509 U16 Reserved2; /* 0x02 */ 1510 U32 Checksum; /* 0x04 */ 1511 U32 ImageSize; /* 0x08 */ 1512 U32 NextImageHeaderOffset; /* 0x0C */ 1513 U32 PackageVersion; /* 0x10 */ 1514 U32 Reserved3; /* 0x14 */ 1515 U32 Reserved4; /* 0x18 */ 1516 U32 Reserved5; /* 0x1C */ 1517 U8 IdentifyString[32]; /* 0x20 */ 1518 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1519 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1520 1521 /* useful offsets */ 1522 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1523 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1524 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1525 1526 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1527 1528 /* defines for the ImageType field */ 1529 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1530 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1531 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1532 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1533 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1534 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1535 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1536 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1537 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */ 1538 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) 1539 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) 1540 1541 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */ 1542 1543 1544 1545 /* FLASH Layout Extended Image Data */ 1546 1547 /* 1548 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1549 * one and check RegionsPerLayout at runtime. 1550 */ 1551 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1552 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1553 #endif 1554 1555 /* 1556 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1557 * one and check NumberOfLayouts at runtime. 1558 */ 1559 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1560 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1561 #endif 1562 1563 typedef struct _MPI2_FLASH_REGION 1564 { 1565 U8 RegionType; /* 0x00 */ 1566 U8 Reserved1; /* 0x01 */ 1567 U16 Reserved2; /* 0x02 */ 1568 U32 RegionOffset; /* 0x04 */ 1569 U32 RegionSize; /* 0x08 */ 1570 U32 Reserved3; /* 0x0C */ 1571 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1572 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1573 1574 typedef struct _MPI2_FLASH_LAYOUT 1575 { 1576 U32 FlashSize; /* 0x00 */ 1577 U32 Reserved1; /* 0x04 */ 1578 U32 Reserved2; /* 0x08 */ 1579 U32 Reserved3; /* 0x0C */ 1580 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1581 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1582 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1583 1584 typedef struct _MPI2_FLASH_LAYOUT_DATA 1585 { 1586 U8 ImageRevision; /* 0x00 */ 1587 U8 Reserved1; /* 0x01 */ 1588 U8 SizeOfRegion; /* 0x02 */ 1589 U8 Reserved2; /* 0x03 */ 1590 U16 NumberOfLayouts; /* 0x04 */ 1591 U16 RegionsPerLayout; /* 0x06 */ 1592 U16 MinimumSectorAlignment; /* 0x08 */ 1593 U16 Reserved3; /* 0x0A */ 1594 U32 Reserved4; /* 0x0C */ 1595 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1596 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1597 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1598 1599 /* defines for the RegionType field */ 1600 #define MPI2_FLASH_REGION_UNUSED (0x00) 1601 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1602 #define MPI2_FLASH_REGION_BIOS (0x02) 1603 #define MPI2_FLASH_REGION_NVDATA (0x03) 1604 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1605 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1606 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1607 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1608 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1609 #define MPI2_FLASH_REGION_INIT (0x0A) 1610 1611 /* ImageRevision */ 1612 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1613 1614 1615 1616 /* Supported Devices Extended Image Data */ 1617 1618 /* 1619 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1620 * one and check NumberOfDevices at runtime. 1621 */ 1622 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1623 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1624 #endif 1625 1626 typedef struct _MPI2_SUPPORTED_DEVICE 1627 { 1628 U16 DeviceID; /* 0x00 */ 1629 U16 VendorID; /* 0x02 */ 1630 U16 DeviceIDMask; /* 0x04 */ 1631 U16 Reserved1; /* 0x06 */ 1632 U8 LowPCIRev; /* 0x08 */ 1633 U8 HighPCIRev; /* 0x09 */ 1634 U16 Reserved2; /* 0x0A */ 1635 U32 Reserved3; /* 0x0C */ 1636 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1637 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1638 1639 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1640 { 1641 U8 ImageRevision; /* 0x00 */ 1642 U8 Reserved1; /* 0x01 */ 1643 U8 NumberOfDevices; /* 0x02 */ 1644 U8 Reserved2; /* 0x03 */ 1645 U32 Reserved3; /* 0x04 */ 1646 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1647 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1648 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1649 1650 /* ImageRevision */ 1651 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1652 1653 1654 /* Init Extended Image Data */ 1655 1656 typedef struct _MPI2_INIT_IMAGE_FOOTER 1657 1658 { 1659 U32 BootFlags; /* 0x00 */ 1660 U32 ImageSize; /* 0x04 */ 1661 U32 Signature0; /* 0x08 */ 1662 U32 Signature1; /* 0x0C */ 1663 U32 Signature2; /* 0x10 */ 1664 U32 ResetVector; /* 0x14 */ 1665 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1666 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1667 1668 /* defines for the BootFlags field */ 1669 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1670 1671 /* defines for the ImageSize field */ 1672 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1673 1674 /* defines for the Signature0 field */ 1675 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1676 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1677 1678 /* defines for the Signature1 field */ 1679 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1680 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1681 1682 /* defines for the Signature2 field */ 1683 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1684 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1685 1686 /* Signature fields as individual bytes */ 1687 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1688 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1689 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1690 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1691 1692 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1693 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1694 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1695 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1696 1697 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1698 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1699 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1700 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1701 1702 /* defines for the ResetVector field */ 1703 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1704 1705 1706 /* Encrypted Hash Extended Image Data */ 1707 1708 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY 1709 { 1710 U8 HashImageType; /* 0x00 */ 1711 U8 HashAlgorithm; /* 0x01 */ 1712 U8 EncryptionAlgorithm; /* 0x02 */ 1713 U8 Reserved1; /* 0x03 */ 1714 U32 Reserved2; /* 0x04 */ 1715 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ 1716 } MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY, 1717 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t; 1718 1719 /* values for HashImageType */ 1720 #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) 1721 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) 1722 #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) 1723 1724 /* values for HashAlgorithm */ 1725 #define MPI25_HASH_ALGORITHM_UNUSED (0x00) 1726 #define MPI25_HASH_ALGORITHM_SHA256 (0x01) 1727 1728 /* values for EncryptionAlgorithm */ 1729 #define MPI25_ENCRYPTION_ALG_UNUSED (0x00) 1730 #define MPI25_ENCRYPTION_ALG_RSA256 (0x01) 1731 1732 typedef struct _MPI25_ENCRYPTED_HASH_DATA 1733 { 1734 U8 ImageVersion; /* 0x00 */ 1735 U8 NumHash; /* 0x01 */ 1736 U16 Reserved1; /* 0x02 */ 1737 U32 Reserved2; /* 0x04 */ 1738 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */ 1739 } MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA, 1740 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t; 1741 1742 /**************************************************************************** 1743 * PowerManagementControl message 1744 ****************************************************************************/ 1745 1746 /* PowerManagementControl Request message */ 1747 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1748 { 1749 U8 Feature; /* 0x00 */ 1750 U8 Reserved1; /* 0x01 */ 1751 U8 ChainOffset; /* 0x02 */ 1752 U8 Function; /* 0x03 */ 1753 U16 Reserved2; /* 0x04 */ 1754 U8 Reserved3; /* 0x06 */ 1755 U8 MsgFlags; /* 0x07 */ 1756 U8 VP_ID; /* 0x08 */ 1757 U8 VF_ID; /* 0x09 */ 1758 U16 Reserved4; /* 0x0A */ 1759 U8 Parameter1; /* 0x0C */ 1760 U8 Parameter2; /* 0x0D */ 1761 U8 Parameter3; /* 0x0E */ 1762 U8 Parameter4; /* 0x0F */ 1763 U32 Reserved5; /* 0x10 */ 1764 U32 Reserved6; /* 0x14 */ 1765 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1766 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1767 1768 /* defines for the Feature field */ 1769 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1770 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1771 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */ 1772 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1773 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */ 1774 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1775 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1776 1777 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1778 /* Parameter1 contains a PHY number */ 1779 /* Parameter2 indicates power condition action using these defines */ 1780 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1781 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1782 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1783 /* Parameter3 and Parameter4 are reserved */ 1784 1785 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1786 /* Parameter1 contains SAS port width modulation group number */ 1787 /* Parameter2 indicates IOC action using these defines */ 1788 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1789 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1790 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1791 /* Parameter3 indicates desired modulation level using these defines */ 1792 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1793 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1794 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1795 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1796 /* Parameter4 is reserved */ 1797 1798 /* this next set (_PCIE_LINK) is obsolete */ 1799 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1800 /* Parameter1 indicates desired PCIe link speed using these defines */ 1801 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */ 1802 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */ 1803 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */ 1804 /* Parameter2 indicates desired PCIe link width using these defines */ 1805 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */ 1806 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */ 1807 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */ 1808 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */ 1809 /* Parameter3 and Parameter4 are reserved */ 1810 1811 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1812 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1813 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1814 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1815 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1816 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1817 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1818 1819 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */ 1820 /* Parameter1 indicates host action regarding global power management mode */ 1821 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 1822 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 1823 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 1824 /* Parameter2 indicates the requested global power management mode */ 1825 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 1826 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 1827 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 1828 /* Parameter3 and Parameter4 are reserved */ 1829 1830 1831 /* PowerManagementControl Reply message */ 1832 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1833 { 1834 U8 Feature; /* 0x00 */ 1835 U8 Reserved1; /* 0x01 */ 1836 U8 MsgLength; /* 0x02 */ 1837 U8 Function; /* 0x03 */ 1838 U16 Reserved2; /* 0x04 */ 1839 U8 Reserved3; /* 0x06 */ 1840 U8 MsgFlags; /* 0x07 */ 1841 U8 VP_ID; /* 0x08 */ 1842 U8 VF_ID; /* 0x09 */ 1843 U16 Reserved4; /* 0x0A */ 1844 U16 Reserved5; /* 0x0C */ 1845 U16 IOCStatus; /* 0x0E */ 1846 U32 IOCLogInfo; /* 0x10 */ 1847 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1848 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1849 1850 1851 #endif 1852 1853