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Searched refs:MII_STATUS_100_BASE_T4 (Results 1 – 8 of 8) sorted by relevance

/titanic_41/usr/src/uts/common/io/sfe/
H A Dsfe_mii.h77 (MII_STATUS_100_BASE_T4 | \
H A Dsfe_util.c3460 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4); in gem_param_get()
3680 if (val && (dp->mii_status & MII_STATUS_100_BASE_T4) == 0) { in gem_param_set()
3811 SETFUNC((dp->mii_status & MII_STATUS_100_BASE_T4) && in gem_nd_setup()
4021 if (dp->mii_status & MII_STATUS_100_BASE_T4) { in gem_mac_xcvr_inuse()
4520 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4); in gem_m_getstat()
4939 dp->anadv_100t4 &= BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4); in gem_do_attach()
/titanic_41/usr/src/uts/common/sys/
H A Dmiiregs.h66 #define MII_STATUS_100_BASE_T4 (1<<15) macro
/titanic_41/usr/src/uts/intel/io/dnet/
H A Ddnet_mii.c196 MII_STATUS_100_BASE_T4)) && phydata->fix_speed == 0) { in mii_init_phy()
/titanic_41/usr/src/uts/common/io/mii/
H A Dmii.c1697 ph->phy_cap_100_t4 = !!(bmsr & MII_STATUS_100_BASE_T4); in _mii_probe_phy()
1725 if (bmsr & MII_STATUS_100_BASE_T4) { in _mii_probe_phy()
/titanic_41/usr/src/uts/common/io/vr/
H A Dvr.c752 if ((vrp->chip.mii.status & MII_STATUS_100_BASE_T4) == 0) in vr_param_init()
2346 v = (vrp->chip.mii.status & MII_STATUS_100_BASE_T4) != 0; in vr_mac_getstat()
3331 MII_STATUS_100_BASE_T4) != 0; in vr_mac_propinfo()
/titanic_41/usr/src/uts/common/io/bfe/
H A Dbfe.c609 if (bmsr & MII_STATUS_100_BASE_T4) { in bfe_startup_phy()
1438 v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASE_T4) != 0; in bfe_mac_getstat()
/titanic_41/usr/src/uts/common/io/mxfe/
H A Dmxfe.c1290 if (bmsr & MII_STATUS_100_BASE_T4) { in mxfe_startphymii()
1344 if (!(bmsr & MII_STATUS_100_BASE_T4)) { in mxfe_startphymii()