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Searched refs:MII_BMCR (Results 1 – 10 of 10) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dmv88e1xxx.c79 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET); in mv88e1xxx_reset()
82 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_reset()
157 (void) simple_mdio_read(phy, MII_BMCR, &ctl); in mv88e1xxx_set_speed_duplex()
172 (void) simple_mdio_write(phy, MII_BMCR, ctl); in mv88e1xxx_set_speed_duplex()
193 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_autoneg_enable()
196 (void) simple_mdio_write(cphy, MII_BMCR, ctl); in mv88e1xxx_autoneg_enable()
214 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_autoneg_disable()
216 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART); in mv88e1xxx_autoneg_disable()
222 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART); in mv88e1xxx_autoneg_restart()
261 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK); in mv88e1xxx_set_loopback()
[all …]
H A Dch_compat.h44 #ifndef MII_BMCR
47 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/titanic_41/usr/src/grub/grub-0.97/netboot/
H A Dmii.h15 #define MII_BMCR 0x00 /* Basic mode control register */ macro
H A Drtl8139.c105 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, enumerator
213 fullduplex = inw(nic->ioaddr + MII_BMCR) & BMCRDuplex; in rtl8139_probe()
H A Dtg3.c278 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
284 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
424 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
649 tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); in tg3_phy_copper_begin()
771 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
772 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
1221 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_setup_fiber_phy()
2503 err |= tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
H A Dsundance.c698 mdio_write(nic, sdc->phys[0], MII_BMCR, mii_ctl); in sundance_probe()
725 mii_ctl = mdio_read(nic, sdc->phys[0], MII_BMCR); in sundance_probe()
H A Dforcedeth.c369 #define MII_BMCR 0x00 /* Basic mode control register */ macro
H A Dtg3.h80 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/titanic_41/usr/src/uts/common/io/cxgbe/t4nex/
H A Dosdep.h47 #define MII_BMCR 0x00 macro
/titanic_41/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.h123 #define MII_BMCR 0x00 /* Basic mode control register */ macro