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Searched refs:MII_ABILITY_100BASE_TX (Results 1 – 11 of 11) sorted by relevance

/titanic_41/usr/src/uts/common/io/sfe/
H A Dsfe_mii.h105 MII_ABILITY_100BASE_TX | \
H A Dsfe_util.c2157 val |= MII_ABILITY_100BASE_TX; in gem_mii_config_default()
2483 if (lpable & MII_ABILITY_100BASE_TX) { in gem_mii_link_check()
2526 } else if (val & MII_ABILITY_100BASE_TX) { in gem_mii_link_check()
3548 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_TX); in gem_param_get()
4467 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_TX); in gem_m_getstat()
/titanic_41/usr/src/uts/common/sys/
H A Dmiiregs.h95 #define MII_ABILITY_100BASE_TX (1<<7) macro
/titanic_41/usr/src/uts/common/io/vr/
H A Dvr.c722 vrp->param.anadv_en |= MII_ABILITY_100BASE_TX; in vr_param_init()
747 vrp->param.an_phymask &= ~MII_ABILITY_100BASE_TX; in vr_param_init()
2314 v = (vrp->chip.mii.anadv & MII_ABILITY_100BASE_TX) != 0; in vr_mac_getstat()
2456 v = (vrp->chip.mii.lpable & MII_ABILITY_100BASE_TX) != 0; in vr_mac_getstat()
2688 MII_ABILITY_100BASE_TX) != 0) { in vr_link_init()
2746 } else if ((mask & MII_ABILITY_100BASE_TX) != 0) { in vr_link_state()
3197 MII_ABILITY_100BASE_TX) != 0; in vr_mac_getprop()
3231 MII_ABILITY_100BASE_TX) != 0; in vr_mac_getprop()
3462 ~MII_ABILITY_100BASE_TX; in vr_mac_setprop()
3465 MII_ABILITY_100BASE_TX; in vr_mac_setprop()
/titanic_41/usr/src/uts/common/io/bfe/
H A Dbfe.c568 MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX | in bfe_startup_phy()
624 anar |= MII_ABILITY_100BASE_TX; in bfe_startup_phy()
628 anar |= MII_ABILITY_100BASE_TX; in bfe_startup_phy()
790 } else if (anar & anlpar & MII_ABILITY_100BASE_TX) { in bfe_check_link()
1405 v = (bfe->bfe_mii_anar & MII_ABILITY_100BASE_TX) != 0; in bfe_mac_getstat()
1522 v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_TX) != 0; in bfe_mac_getstat()
/titanic_41/usr/src/uts/intel/io/dnet/
H A Ddnet_mii.c833 } else if (mask & MII_ABILITY_100BASE_TX) { in getspeed_NS83840()
959 } else if (mask & MII_ABILITY_100BASE_TX) { in getspeed_generic()
/titanic_41/usr/src/uts/common/io/mxfe/
H A Dmxfe.c1129 } else if ((anlpar & MII_ABILITY_100BASE_TX) && in mxfe_checklinknway()
1340 MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX | in mxfe_startphymii()
1379 anar |= MII_ABILITY_100BASE_TX; in mxfe_startphymii()
1540 } else if (anar & anlpar & MII_ABILITY_100BASE_TX) { in mxfe_checklinkmii()
2849 *val = (mxfep->mxfe_anlpar & MII_ABILITY_100BASE_TX) ? 1 : 0; in mxfe_m_stat()
/titanic_41/usr/src/uts/common/io/nge/
H A Dnge_xmii.c445 anar |= MII_ABILITY_100BASE_TX; in nge_update_copper()
/titanic_41/usr/src/uts/common/io/bge/
H A Dbge_mii.c1061 anar |= MII_ABILITY_100BASE_TX; in bge_update_copper()
1249 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); in bge_check_copper()
/titanic_41/usr/src/uts/common/io/mii/
H A Dmii.c1331 anar |= MII_ABILITY_100BASE_TX; in phy_start()
1536 ph->phy_lp_100_hdx = !!(lpar & MII_ABILITY_100BASE_TX); in phy_check()
/titanic_41/usr/src/uts/common/io/rge/
H A Drge_chip.c543 anar |= MII_ABILITY_100BASE_TX; in rge_phy_update()