Searched refs:MII_ABILITY_100BASE_T4 (Results 1 – 8 of 8) sorted by relevance
103 (MII_ABILITY_100BASE_T4 | \
2151 val |= MII_ABILITY_100BASE_T4; in gem_mii_config_default()2522 } else if (val & MII_ABILITY_100BASE_T4) { in gem_mii_link_check()3540 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4); in gem_param_get()4528 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4); in gem_m_getstat()
97 #define MII_ABILITY_100BASE_T4 (1<<9) macro
720 vrp->param.anadv_en |= MII_ABILITY_100BASE_T4; in vr_param_init()753 vrp->param.an_phymask &= ~MII_ABILITY_100BASE_T4; in vr_param_init()2306 v = (vrp->chip.mii.anadv & MII_ABILITY_100BASE_T4) != 0; in vr_mac_getstat()2440 v = (vrp->chip.mii.lpable & MII_ABILITY_100BASE_T4) != 0; in vr_mac_getstat()2742 } else if ((mask & MII_ABILITY_100BASE_T4) != 0) { in vr_link_state()3202 MII_ABILITY_100BASE_T4) != 0; in vr_mac_getprop()3236 MII_ABILITY_100BASE_T4) != 0; in vr_mac_getprop()3471 ~MII_ABILITY_100BASE_T4; in vr_mac_setprop()3474 MII_ABILITY_100BASE_T4; in vr_mac_setprop()
830 } else if (mask & MII_ABILITY_100BASE_T4) { in getspeed_NS83840()956 } else if (mask & MII_ABILITY_100BASE_T4) { in getspeed_generic()
567 anar &= ~(MII_ABILITY_100BASE_T4 | in bfe_startup_phy()612 anar |= MII_ABILITY_100BASE_T4; in bfe_startup_phy()616 anar |= MII_ABILITY_100BASE_T4; in bfe_startup_phy()787 } else if (anar & anlpar & MII_ABILITY_100BASE_T4) { in bfe_check_link()1514 v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_T4) != 0; in bfe_mac_getstat()
1339 anar &= ~(MII_ABILITY_100BASE_T4 | in mxfe_startphymii()1371 anar |= MII_ABILITY_100BASE_T4; in mxfe_startphymii()1537 } else if (anar & anlpar & MII_ABILITY_100BASE_T4) { in mxfe_checklinkmii()2792 *val = (mxfep->mxfe_anlpar & MII_ABILITY_100BASE_T4) ? 1 : 0; in mxfe_m_stat()
1334 anar |= MII_ABILITY_100BASE_T4; in phy_start()1537 ph->phy_lp_100_t4 = !!(lpar & MII_ABILITY_100BASE_T4); in phy_check()