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Searched refs:MDIO_WC_REG_XGXS_X2_CONTROL3 (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h575 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 macro
/titanic_41/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c4144 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); in elink_warpcore_enable_AN_KR()
14808 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); in elink_warpcore_common_init()