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Searched refs:MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h423 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 macro
/titanic_41/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c3781 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; in elink_ext_phy_set_pause()
11838 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; in elink_54618se_config_init()