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Searched refs:MC_AM_REG_DRAMLIM_0 (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/intel/sys/
H A Dmc_amd.h175 #define MC_AM_REG_DRAMLIM_0 0x44 /* Offset for DRAM Limit 0 */ macro
/titanic_41/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_drv.c691 MC_AM_REG_DRAMLIM_0 + nodeid * MC_AM_REG_DRAM_INCR); in mc_mkprops_addrmap()